Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434743
K.F. Omar, A. M. El-Gindy, M.R. El-Ghoneimy
In this paper, we consider the MC-CDMA system, which is a combination of the multi-carrier modulation technique and the CDMA, multiple access technique. The performance of the system is investigated over AWGN channels as well as over Rayleigh multi-path fading channels. We show that for a given spreading factor, the performance of the system degrades as the number of the sub-carriers increases. Furthermore, the performance of the system is evaluated when a RAKE receiver is used. Finally, the problem of carrier frequency offset is studied. We show that, the performance of the system degrades rapidly as the ratio between the carrier frequency offset and the carrier spacing exceeds a certain ratio, and the system becomes more sensitive to carrier frequency offset as the number of the sub-carriers increases. Results are given in terms of SER obtained by means of computer simulations.
{"title":"The effect of carrier frequency offset for MC-CDMA systems over Rayleigh multi-path fading channels","authors":"K.F. Omar, A. M. El-Gindy, M.R. El-Ghoneimy","doi":"10.1109/ICM.2004.1434743","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434743","url":null,"abstract":"In this paper, we consider the MC-CDMA system, which is a combination of the multi-carrier modulation technique and the CDMA, multiple access technique. The performance of the system is investigated over AWGN channels as well as over Rayleigh multi-path fading channels. We show that for a given spreading factor, the performance of the system degrades as the number of the sub-carriers increases. Furthermore, the performance of the system is evaluated when a RAKE receiver is used. Finally, the problem of carrier frequency offset is studied. We show that, the performance of the system degrades rapidly as the ratio between the carrier frequency offset and the carrier spacing exceeds a certain ratio, and the system becomes more sensitive to carrier frequency offset as the number of the sub-carriers increases. Results are given in terms of SER obtained by means of computer simulations.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114524271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434228
A. Valizadeh, M. Saheb Zamani, B. Sadeghian, Farhad Mehdipour, B. Najafi
Reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using field programmable gate arrays (FPGAs), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applications, including encryption, which involve repetitive computation, and have inherent parallelism, are specifically well suited to the use of FPGAs. In this paper, we implemented four DES-like algorithms namely DES, DESX, Biham-DES, and S/sup n/ DES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. This kind of implementation not only has high flexibility but also has an acceptable encryption rate compared with the fastest implementation of DES.
{"title":"A high performance reconfigurable implementation of DES-like algorithms","authors":"A. Valizadeh, M. Saheb Zamani, B. Sadeghian, Farhad Mehdipour, B. Najafi","doi":"10.1109/ICM.2004.1434228","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434228","url":null,"abstract":"Reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using field programmable gate arrays (FPGAs), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applications, including encryption, which involve repetitive computation, and have inherent parallelism, are specifically well suited to the use of FPGAs. In this paper, we implemented four DES-like algorithms namely DES, DESX, Biham-DES, and S/sup n/ DES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. This kind of implementation not only has high flexibility but also has an acceptable encryption rate compared with the fastest implementation of DES.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"494 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115104330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434241
D. Deschacht, A. Lopez
Rapid progress in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. In this paper, we show the influence of inductance and routing orientation on crosstalk voltage by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and the other with the drivers in opposite directions. For a typical DSM (deep-sub-micron) process, we show that when standard distributed RC models are used and inductive effects and routing orientation are ignored, large errors can occur in the prediction and evaluation of the crosstalk voltage: the discrepancy rates can reach a mean value of 23% for the same direction and 52% for the opposite direction for the near-end crosstalk and 44% for the same direction and 39% for the opposite direction for the far-end crosstalk. The routing orientation can lead to a mean difference of 35% for the near-end crosstalk and 24% for the far-end crosstalk.
{"title":"Crosstalk evaluation: the influence of inductance and routing orientation","authors":"D. Deschacht, A. Lopez","doi":"10.1109/ICM.2004.1434241","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434241","url":null,"abstract":"Rapid progress in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. In this paper, we show the influence of inductance and routing orientation on crosstalk voltage by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and the other with the drivers in opposite directions. For a typical DSM (deep-sub-micron) process, we show that when standard distributed RC models are used and inductive effects and routing orientation are ignored, large errors can occur in the prediction and evaluation of the crosstalk voltage: the discrepancy rates can reach a mean value of 23% for the same direction and 52% for the opposite direction for the near-end crosstalk and 44% for the same direction and 39% for the opposite direction for the far-end crosstalk. The routing orientation can lead to a mean difference of 35% for the near-end crosstalk and 24% for the far-end crosstalk.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123198515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434199
F. Touati
Simple low-noise, low-power, and gain-controlled 0.35 /spl mu/m SiGe UWB amplifiers for 3.1-10.6 GHz radios are presented. Simulation results of common-base BiCMOS LNAs give a gain controlled from 3.8 up to 15.5 dB over a bandwidth range from 10.6 down to 3.1 GHz, respectively. These LNAs achieved a noise figure that is less than 5.5 dB and power dissipation less than 6.6 mW under a power supply of /spl plusmn/1.5 V. Also, a common-gate CMOS LNA is designed to operate over all the frequency range 3.1-10.6 GHz with a 10.2 dB gain, which is flat to within /spl plusmn/0.3 dB, a noise figure of 5.1 dB, power dissipation of 5.6 mW, and a 1-dB compression point of about -23 dBm in a 50 /spl Omega/-input system. The results stand high when compared to recent published figures.
{"title":"Design of 0.35 /spl mu/m SiGe LNAs for UWB communications systems","authors":"F. Touati","doi":"10.1109/ICM.2004.1434199","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434199","url":null,"abstract":"Simple low-noise, low-power, and gain-controlled 0.35 /spl mu/m SiGe UWB amplifiers for 3.1-10.6 GHz radios are presented. Simulation results of common-base BiCMOS LNAs give a gain controlled from 3.8 up to 15.5 dB over a bandwidth range from 10.6 down to 3.1 GHz, respectively. These LNAs achieved a noise figure that is less than 5.5 dB and power dissipation less than 6.6 mW under a power supply of /spl plusmn/1.5 V. Also, a common-gate CMOS LNA is designed to operate over all the frequency range 3.1-10.6 GHz with a 10.2 dB gain, which is flat to within /spl plusmn/0.3 dB, a noise figure of 5.1 dB, power dissipation of 5.6 mW, and a 1-dB compression point of about -23 dBm in a 50 /spl Omega/-input system. The results stand high when compared to recent published figures.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123547405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434717
Azadeh Zahabi, O. Shoaei, Y. Koolivand, H. Shamsi
A two-stage optimization approach for the design of /spl Sigma//spl Delta/ modulators using genetic algorithm has been proposed. The method utilizes a new idea called gene-dependent fitness function, which takes some circuit-level non-idealities into account in the evaluation of the cost function. The combination of an equation-based and a high-level simulation-based genetic algorithm have been reduced conversion speed and consumed CPU time of the modulator design, significantly. Using the proposed approach, the optimized order, oversampling ratio and the DAC bit number to meet the specified specifications is obtained. This speedups the design process without extra time-consuming circuit simulations and transient analysis.
{"title":"An algorithmic optimization method for design of /spl Sigma//spl Delta/ modulators","authors":"Azadeh Zahabi, O. Shoaei, Y. Koolivand, H. Shamsi","doi":"10.1109/ICM.2004.1434717","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434717","url":null,"abstract":"A two-stage optimization approach for the design of /spl Sigma//spl Delta/ modulators using genetic algorithm has been proposed. The method utilizes a new idea called gene-dependent fitness function, which takes some circuit-level non-idealities into account in the evaluation of the cost function. The combination of an equation-based and a high-level simulation-based genetic algorithm have been reduced conversion speed and consumed CPU time of the modulator design, significantly. Using the proposed approach, the optimized order, oversampling ratio and the DAC bit number to meet the specified specifications is obtained. This speedups the design process without extra time-consuming circuit simulations and transient analysis.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114954225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434706
M. Salehi, K. Saleh, H. Kalantari, M. Naderi, H. Pedram
This paper introduces an innovative high-level method to estimate energy consumption of a well known family of asynchronous circuits at CSP level, therefore removing the need for performing time consuming SPICE simulation. Our method is based on transition count and helps the PCHB/PCFB template based QDI asynchronous circuit designers to have an early estimation of power with the accuracy of more than 80%. This estimation, obtained from commercial functional simulators, may lead to power optimization of the circuit in high levels of design.
{"title":"High-level energy estimation of template-based QDI asynchronous circuits based on transition counting","authors":"M. Salehi, K. Saleh, H. Kalantari, M. Naderi, H. Pedram","doi":"10.1109/ICM.2004.1434706","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434706","url":null,"abstract":"This paper introduces an innovative high-level method to estimate energy consumption of a well known family of asynchronous circuits at CSP level, therefore removing the need for performing time consuming SPICE simulation. Our method is based on transition count and helps the PCHB/PCFB template based QDI asynchronous circuit designers to have an early estimation of power with the accuracy of more than 80%. This estimation, obtained from commercial functional simulators, may lead to power optimization of the circuit in high levels of design.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129586325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434594
N. Gorse, M. Metzger, J. Lapalme, E. Aboulhamid, Y. Savarie, G. Nicolescu
As electronic systems reach tremendous complexity, new CAD tools are needed to cope with their design and verification. ESys.Net, a new design environment under development at Universite de Montreal proposes an elegant solution for modeling and simulation. This paper presents the extension of this environment with a complete verification layer based on linear temporal logic. This is a major enhancement to ESys.Net, since it allows designers to use it not only for modeling and simulation but also for verification.
{"title":"Enhancing ESys.Net with a semi-formal verification layer","authors":"N. Gorse, M. Metzger, J. Lapalme, E. Aboulhamid, Y. Savarie, G. Nicolescu","doi":"10.1109/ICM.2004.1434594","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434594","url":null,"abstract":"As electronic systems reach tremendous complexity, new CAD tools are needed to cope with their design and verification. ESys.Net, a new design environment under development at Universite de Montreal proposes an elegant solution for modeling and simulation. This paper presents the extension of this environment with a complete verification layer based on linear temporal logic. This is a major enhancement to ESys.Net, since it allows designers to use it not only for modeling and simulation but also for verification.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131460002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434232
F.M. Yasin, A. Tio, M.S. Islam, M. Reaz, M. Sulaiman
In this paper, we present the realization of a fuzzy logic-based temperature controller intended for industrial application on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The system is built of four major modules called fuzzification, inference, implication and defuzzification. The composition method selected for the fuzzy model is the max-min composition while the Mamdani min operator was chosen as the implication method. Each module is modeled individually using behavioral VHDL and combined using structural VHDL. The timing analysis for the validation, functionality and performance of the model is performed using Aldec active HDL, and the logic synthesis was performed using Synplify. Simulation results show that the model has been tested successfully. The inferred maximum operating frequency is 5 MHz with a critical path of 199.3 ns.
{"title":"The hardware design of temperature controller based on fuzzy logic for industrial application employing FPGA","authors":"F.M. Yasin, A. Tio, M.S. Islam, M. Reaz, M. Sulaiman","doi":"10.1109/ICM.2004.1434232","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434232","url":null,"abstract":"In this paper, we present the realization of a fuzzy logic-based temperature controller intended for industrial application on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The system is built of four major modules called fuzzification, inference, implication and defuzzification. The composition method selected for the fuzzy model is the max-min composition while the Mamdani min operator was chosen as the implication method. Each module is modeled individually using behavioral VHDL and combined using structural VHDL. The timing analysis for the validation, functionality and performance of the model is performed using Aldec active HDL, and the logic synthesis was performed using Synplify. Simulation results show that the model has been tested successfully. The inferred maximum operating frequency is 5 MHz with a critical path of 199.3 ns.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130230067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434737
M. Loulou, K. Neji, C. Mabrouk, A. Fakhfakh, M. Fakhfakh, N. Masmoudi
A novel approach to the design of hearing aids system is shown. It is based on the use of switched current circuit to design analogue programmable filter. The idea consists of using the possibility to control SI circuit parameter by varying switching frequency. Indeed, SI circuits are designed using digital CMOS process since it uses only transistors to perform basic processing blocks. Our effort was focused on the design of a digitally controlling circuit in CMOS technology. We proposed a prosthesis system based on a set of audio SI filters distributed on the 8 kHz audio band. Each filter parameters are controlled by a digitally programmable PLL based frequency synthesizer and a switched weighted gain stages. The whole system is designed using only CMOS process.
{"title":"New approach to a digitally programmable analogue VLSI cochlea prosthesis and its implementation with SI technique","authors":"M. Loulou, K. Neji, C. Mabrouk, A. Fakhfakh, M. Fakhfakh, N. Masmoudi","doi":"10.1109/ICM.2004.1434737","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434737","url":null,"abstract":"A novel approach to the design of hearing aids system is shown. It is based on the use of switched current circuit to design analogue programmable filter. The idea consists of using the possibility to control SI circuit parameter by varying switching frequency. Indeed, SI circuits are designed using digital CMOS process since it uses only transistors to perform basic processing blocks. Our effort was focused on the design of a digitally controlling circuit in CMOS technology. We proposed a prosthesis system based on a set of audio SI filters distributed on the 8 kHz audio band. Each filter parameters are controlled by a digitally programmable PLL based frequency synthesizer and a switched weighted gain stages. The whole system is designed using only CMOS process.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127693998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434243
C. Cantalini, G. Ferri, N. Guerrini, S. Santucci
In this work, we present a low-voltage (/spl plusmn/0.75 V) low-power (0.7 mW) current mode-based integrated interface for resistive gas sensors. The proposed interface, which includes a grounded resistive sensor, shows the capability of compensation of non-idealities of passive and active components, in particular the voltage offset. The sensitivity value has been set to about 16 mV/K/spl Omega/, while theoretical resolution is about 135 /spl Omega/, to which corresponds a gas resolution lower than 1.5 ppm.
{"title":"A low-voltage low-power current-mode gas sensor integrated interface","authors":"C. Cantalini, G. Ferri, N. Guerrini, S. Santucci","doi":"10.1109/ICM.2004.1434243","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434243","url":null,"abstract":"In this work, we present a low-voltage (/spl plusmn/0.75 V) low-power (0.7 mW) current mode-based integrated interface for resistive gas sensors. The proposed interface, which includes a grounded resistive sensor, shows the capability of compensation of non-idealities of passive and active components, in particular the voltage offset. The sensitivity value has been set to about 16 mV/K/spl Omega/, while theoretical resolution is about 135 /spl Omega/, to which corresponds a gas resolution lower than 1.5 ppm.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126955713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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