Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434580
Jun Xu, R. Sotudeh
System-on-chip (SoC) design is facing increasing difficulties in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over the conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. The combination of these two technologies therefore could be an optimal solution for the interconnection of SoC. In this paper, we focus on the implementation of packet-switch with asynchronous technology. The results of experiments run to evaluate several aspects of the packet-switch implementation are presented.
{"title":"Asynchronous packet-switch for SoC","authors":"Jun Xu, R. Sotudeh","doi":"10.1109/ICM.2004.1434580","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434580","url":null,"abstract":"System-on-chip (SoC) design is facing increasing difficulties in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over the conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. The combination of these two technologies therefore could be an optimal solution for the interconnection of SoC. In this paper, we focus on the implementation of packet-switch with asynchronous technology. The results of experiments run to evaluate several aspects of the packet-switch implementation are presented.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131670126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434594
N. Gorse, M. Metzger, J. Lapalme, E. Aboulhamid, Y. Savarie, G. Nicolescu
As electronic systems reach tremendous complexity, new CAD tools are needed to cope with their design and verification. ESys.Net, a new design environment under development at Universite de Montreal proposes an elegant solution for modeling and simulation. This paper presents the extension of this environment with a complete verification layer based on linear temporal logic. This is a major enhancement to ESys.Net, since it allows designers to use it not only for modeling and simulation but also for verification.
{"title":"Enhancing ESys.Net with a semi-formal verification layer","authors":"N. Gorse, M. Metzger, J. Lapalme, E. Aboulhamid, Y. Savarie, G. Nicolescu","doi":"10.1109/ICM.2004.1434594","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434594","url":null,"abstract":"As electronic systems reach tremendous complexity, new CAD tools are needed to cope with their design and verification. ESys.Net, a new design environment under development at Universite de Montreal proposes an elegant solution for modeling and simulation. This paper presents the extension of this environment with a complete verification layer based on linear temporal logic. This is a major enhancement to ESys.Net, since it allows designers to use it not only for modeling and simulation but also for verification.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131460002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434593
A. Chehab, A. Kayssi, A. Nazer, N. Aaraj
We propose a method for testing dynamic CMOS circuits using the transient power supply current, i/sub DDT/. The method is based on setting the primary inputs of the circuit under test, switching the clock signal and monitoring the peak magnitude of i/sub DDT/. If the magnitude lies outside a predetermined range, a defect is inferred. We target resistive open defects that can either cause the circuit to fail, or introduce unacceptable delay and hence result in degraded circuit performance. We propose two methods for generating test vectors for i/sub DDT/ testing. One method is based on random vector generation while the second uses a SAT-solver. Fault simulation results on domino CMOS circuits show a high rate of detection for resistive open faults that cannot be otherwise detected using the traditional voltage or I/sub DDQ/ testing. We also show that by using a normalization procedure, the defects can be detected with a single threshold setup in the presence of leakage and process variations that normally hinder the detection capability of current-based testing techniques.
{"title":"Transient current testing of dynamic CMOS circuits in the presence of leakage and process variation","authors":"A. Chehab, A. Kayssi, A. Nazer, N. Aaraj","doi":"10.1109/ICM.2004.1434593","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434593","url":null,"abstract":"We propose a method for testing dynamic CMOS circuits using the transient power supply current, i/sub DDT/. The method is based on setting the primary inputs of the circuit under test, switching the clock signal and monitoring the peak magnitude of i/sub DDT/. If the magnitude lies outside a predetermined range, a defect is inferred. We target resistive open defects that can either cause the circuit to fail, or introduce unacceptable delay and hence result in degraded circuit performance. We propose two methods for generating test vectors for i/sub DDT/ testing. One method is based on random vector generation while the second uses a SAT-solver. Fault simulation results on domino CMOS circuits show a high rate of detection for resistive open faults that cannot be otherwise detected using the traditional voltage or I/sub DDQ/ testing. We also show that by using a normalization procedure, the defects can be detected with a single threshold setup in the presence of leakage and process variations that normally hinder the detection capability of current-based testing techniques.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133516967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434255
S. Ouadjaout, D. Houzet
The goal of our paper is to allow a rapid integration of SystemC IPs with several abstraction levels, in order to reduce the SoC design cost and time to market window. Our challenge is finding a way which allows the communication between IPs from different sources without changing their code or understand their interface of communication. We introduce in this article our design flow which include our own adaptation methodology of functional IP interface translation towards VCI interface. This methodology is performed through a custom SystemC adapters library.
{"title":"Rapid integration of reusable functional IPs with SystemC VCI adapters","authors":"S. Ouadjaout, D. Houzet","doi":"10.1109/ICM.2004.1434255","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434255","url":null,"abstract":"The goal of our paper is to allow a rapid integration of SystemC IPs with several abstraction levels, in order to reduce the SoC design cost and time to market window. Our challenge is finding a way which allows the communication between IPs from different sources without changing their code or understand their interface of communication. We introduce in this article our design flow which include our own adaptation methodology of functional IP interface translation towards VCI interface. This methodology is performed through a custom SystemC adapters library.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434777
A. Portero, O. Navas, J. Carrabina
In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and can be automated (through systems synthesis). A MPEG demonstrator based on video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 | ITU-T H.262H (also know as "MPEG2 video"), for the main profile and main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures. It has been developed a MPEG compressor based on DCT (discrete cosine transform) through two different methodologies. First one, it is based in Matlab DSP builder from Altera that is a down up methodology, based on component instantiation. And the other, it is a top down methodology based on behavioural SystemC description and synthesized with SystemC behavioural compiler from synopsys.
{"title":"HW-SW design methodologies used for a MPEG video compressor synthesis","authors":"A. Portero, O. Navas, J. Carrabina","doi":"10.1109/ICM.2004.1434777","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434777","url":null,"abstract":"In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and can be automated (through systems synthesis). A MPEG demonstrator based on video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 | ITU-T H.262H (also know as \"MPEG2 video\"), for the main profile and main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures. It has been developed a MPEG compressor based on DCT (discrete cosine transform) through two different methodologies. First one, it is based in Matlab DSP builder from Altera that is a down up methodology, based on component instantiation. And the other, it is a top down methodology based on behavioural SystemC description and synthesized with SystemC behavioural compiler from synopsys.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434717
Azadeh Zahabi, O. Shoaei, Y. Koolivand, H. Shamsi
A two-stage optimization approach for the design of /spl Sigma//spl Delta/ modulators using genetic algorithm has been proposed. The method utilizes a new idea called gene-dependent fitness function, which takes some circuit-level non-idealities into account in the evaluation of the cost function. The combination of an equation-based and a high-level simulation-based genetic algorithm have been reduced conversion speed and consumed CPU time of the modulator design, significantly. Using the proposed approach, the optimized order, oversampling ratio and the DAC bit number to meet the specified specifications is obtained. This speedups the design process without extra time-consuming circuit simulations and transient analysis.
{"title":"An algorithmic optimization method for design of /spl Sigma//spl Delta/ modulators","authors":"Azadeh Zahabi, O. Shoaei, Y. Koolivand, H. Shamsi","doi":"10.1109/ICM.2004.1434717","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434717","url":null,"abstract":"A two-stage optimization approach for the design of /spl Sigma//spl Delta/ modulators using genetic algorithm has been proposed. The method utilizes a new idea called gene-dependent fitness function, which takes some circuit-level non-idealities into account in the evaluation of the cost function. The combination of an equation-based and a high-level simulation-based genetic algorithm have been reduced conversion speed and consumed CPU time of the modulator design, significantly. Using the proposed approach, the optimized order, oversampling ratio and the DAC bit number to meet the specified specifications is obtained. This speedups the design process without extra time-consuming circuit simulations and transient analysis.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114954225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434228
A. Valizadeh, M. Saheb Zamani, B. Sadeghian, Farhad Mehdipour, B. Najafi
Reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using field programmable gate arrays (FPGAs), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applications, including encryption, which involve repetitive computation, and have inherent parallelism, are specifically well suited to the use of FPGAs. In this paper, we implemented four DES-like algorithms namely DES, DESX, Biham-DES, and S/sup n/ DES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. This kind of implementation not only has high flexibility but also has an acceptable encryption rate compared with the fastest implementation of DES.
{"title":"A high performance reconfigurable implementation of DES-like algorithms","authors":"A. Valizadeh, M. Saheb Zamani, B. Sadeghian, Farhad Mehdipour, B. Najafi","doi":"10.1109/ICM.2004.1434228","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434228","url":null,"abstract":"Reconfigurable computing has grown to become an important and large field of research. It offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using field programmable gate arrays (FPGAs), which can be configured after fabrication to take advantage of a hardware design but still maintain the flexibility of software. Particular applications, including encryption, which involve repetitive computation, and have inherent parallelism, are specifically well suited to the use of FPGAs. In this paper, we implemented four DES-like algorithms namely DES, DESX, Biham-DES, and S/sup n/ DES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. This kind of implementation not only has high flexibility but also has an acceptable encryption rate compared with the fastest implementation of DES.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"494 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115104330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434241
D. Deschacht, A. Lopez
Rapid progress in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. In this paper, we show the influence of inductance and routing orientation on crosstalk voltage by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and the other with the drivers in opposite directions. For a typical DSM (deep-sub-micron) process, we show that when standard distributed RC models are used and inductive effects and routing orientation are ignored, large errors can occur in the prediction and evaluation of the crosstalk voltage: the discrepancy rates can reach a mean value of 23% for the same direction and 52% for the opposite direction for the near-end crosstalk and 44% for the same direction and 39% for the opposite direction for the far-end crosstalk. The routing orientation can lead to a mean difference of 35% for the near-end crosstalk and 24% for the far-end crosstalk.
{"title":"Crosstalk evaluation: the influence of inductance and routing orientation","authors":"D. Deschacht, A. Lopez","doi":"10.1109/ICM.2004.1434241","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434241","url":null,"abstract":"Rapid progress in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. In this paper, we show the influence of inductance and routing orientation on crosstalk voltage by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and the other with the drivers in opposite directions. For a typical DSM (deep-sub-micron) process, we show that when standard distributed RC models are used and inductive effects and routing orientation are ignored, large errors can occur in the prediction and evaluation of the crosstalk voltage: the discrepancy rates can reach a mean value of 23% for the same direction and 52% for the opposite direction for the near-end crosstalk and 44% for the same direction and 39% for the opposite direction for the far-end crosstalk. The routing orientation can lead to a mean difference of 35% for the near-end crosstalk and 24% for the far-end crosstalk.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123198515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434199
F. Touati
Simple low-noise, low-power, and gain-controlled 0.35 /spl mu/m SiGe UWB amplifiers for 3.1-10.6 GHz radios are presented. Simulation results of common-base BiCMOS LNAs give a gain controlled from 3.8 up to 15.5 dB over a bandwidth range from 10.6 down to 3.1 GHz, respectively. These LNAs achieved a noise figure that is less than 5.5 dB and power dissipation less than 6.6 mW under a power supply of /spl plusmn/1.5 V. Also, a common-gate CMOS LNA is designed to operate over all the frequency range 3.1-10.6 GHz with a 10.2 dB gain, which is flat to within /spl plusmn/0.3 dB, a noise figure of 5.1 dB, power dissipation of 5.6 mW, and a 1-dB compression point of about -23 dBm in a 50 /spl Omega/-input system. The results stand high when compared to recent published figures.
{"title":"Design of 0.35 /spl mu/m SiGe LNAs for UWB communications systems","authors":"F. Touati","doi":"10.1109/ICM.2004.1434199","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434199","url":null,"abstract":"Simple low-noise, low-power, and gain-controlled 0.35 /spl mu/m SiGe UWB amplifiers for 3.1-10.6 GHz radios are presented. Simulation results of common-base BiCMOS LNAs give a gain controlled from 3.8 up to 15.5 dB over a bandwidth range from 10.6 down to 3.1 GHz, respectively. These LNAs achieved a noise figure that is less than 5.5 dB and power dissipation less than 6.6 mW under a power supply of /spl plusmn/1.5 V. Also, a common-gate CMOS LNA is designed to operate over all the frequency range 3.1-10.6 GHz with a 10.2 dB gain, which is flat to within /spl plusmn/0.3 dB, a noise figure of 5.1 dB, power dissipation of 5.6 mW, and a 1-dB compression point of about -23 dBm in a 50 /spl Omega/-input system. The results stand high when compared to recent published figures.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123547405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434270
F. Sattar, M. Mufti
This paper presents hardware design of a Rayleigh fading simulator that efficiently generates Gaussian variates with Jakes power spectral density. The architecture is based on Komninakis design consisting of a fixed IIR filter followed by a polyphase interpolator for different Doppler rates. The hardware simulator facilitates real time error performance evaluation of wireless channels in Rayleigh fading environments. It also offers the potential of improving the evaluation speed by orders of magnitude over a software based simulation.
{"title":"VLSI architecture of Rayleigh fading simulator based on IIR filter and polyphase interpolator","authors":"F. Sattar, M. Mufti","doi":"10.1109/ICM.2004.1434270","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434270","url":null,"abstract":"This paper presents hardware design of a Rayleigh fading simulator that efficiently generates Gaussian variates with Jakes power spectral density. The architecture is based on Komninakis design consisting of a fixed IIR filter followed by a polyphase interpolator for different Doppler rates. The hardware simulator facilitates real time error performance evaluation of wireless channels in Rayleigh fading environments. It also offers the potential of improving the evaluation speed by orders of magnitude over a software based simulation.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123995231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：