Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434703
T. Sasada, S. Ichikawa, T. Kanai
To evaluate the characteristics of commercial memory devices, Japan Aerospace Exploration Agency (JAXA) launched a solid state recorder (SSR) on the mission demonstration test satellite-1 (MDS-1 or "Tsubasa") into geo-stationary transfer orbit (GTO) in February 2002. Passing through the Van Allen Belt exposed MDS-1 to severe radioactive rays in every orbit. This flight experiment measured the rate of single-event-upsets (SEUs) on a large number of stacked 64 Mbit dynamic random access memory (DRAM), and the distribution of total ionizing dose (TID) effects. As a result, we can calculate the actual SEU rate, and we confirmed the capabilities of two types of on-the-fly error detection and correction (EDAC) mechanisms. This paper presents the results of the space experiment of SSR, especially focusing on SEU analysis.
{"title":"In-flight measurement of space radiation effects on commercial DRAM","authors":"T. Sasada, S. Ichikawa, T. Kanai","doi":"10.1109/ICM.2004.1434703","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434703","url":null,"abstract":"To evaluate the characteristics of commercial memory devices, Japan Aerospace Exploration Agency (JAXA) launched a solid state recorder (SSR) on the mission demonstration test satellite-1 (MDS-1 or \"Tsubasa\") into geo-stationary transfer orbit (GTO) in February 2002. Passing through the Van Allen Belt exposed MDS-1 to severe radioactive rays in every orbit. This flight experiment measured the rate of single-event-upsets (SEUs) on a large number of stacked 64 Mbit dynamic random access memory (DRAM), and the distribution of total ionizing dose (TID) effects. As a result, we can calculate the actual SEU rate, and we confirmed the capabilities of two types of on-the-fly error detection and correction (EDAC) mechanisms. This paper presents the results of the space experiment of SSR, especially focusing on SEU analysis.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124331551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434722
H. Faiedh, Z. Gafsi, K. Torki, K. Besbes
In this paper, we propose a fully digital hardware implementation of neural networks. We describe the functioning of a digital artificial neuron and we propose a general architecture of a generic neural network. An example of a static neural network is given to show the efficiency of the implementation.
{"title":"Digital hardware implementation of a neural network used for classification","authors":"H. Faiedh, Z. Gafsi, K. Torki, K. Besbes","doi":"10.1109/ICM.2004.1434722","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434722","url":null,"abstract":"In this paper, we propose a fully digital hardware implementation of neural networks. We describe the functioning of a digital artificial neuron and we propose a general architecture of a generic neural network. An example of a static neural network is given to show the efficiency of the implementation.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127556601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434746
H. Marouane, A. Kachouri, L. Kamoun
Software radio technology makes possible the implementation of highly flexible receivers architectures that employ sophisticated signal processing algorithms such as those required for equalization. The implementation of advanced DS-CDMA receivers based on adaptive filter principles is becoming an area of considerable interest. The focus of the paper is the introduction of a dynamically reconfigurable architecture and an adaptive linear receiver for CDMA systems in mobile communication. This paper, presents a flexible single-user receiver that can support a variety of applications and analyses the convergence behaviour of the least mean square (LMS) filter when used in an adaptive code division multiple access (CDMA) detector consisting of a tapped delay line with adjustable tap weights.
{"title":"LMS adaptive filter single-user receiver","authors":"H. Marouane, A. Kachouri, L. Kamoun","doi":"10.1109/ICM.2004.1434746","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434746","url":null,"abstract":"Software radio technology makes possible the implementation of highly flexible receivers architectures that employ sophisticated signal processing algorithms such as those required for equalization. The implementation of advanced DS-CDMA receivers based on adaptive filter principles is becoming an area of considerable interest. The focus of the paper is the introduction of a dynamically reconfigurable architecture and an adaptive linear receiver for CDMA systems in mobile communication. This paper, presents a flexible single-user receiver that can support a variety of applications and analyses the convergence behaviour of the least mean square (LMS) filter when used in an adaptive code division multiple access (CDMA) detector consisting of a tapped delay line with adjustable tap weights.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121920172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434254
S. Hessabi, A. M. Gharehbaghi, B. H. Yaran, M. Goudarzi
In this paper, we integrate a verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification after system synthesis. We have defined a set of system-level assertions. These assertions are automatically converted to monitor hardware or monitor software during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertion, and hence, can he used to verify the system after HW/SW synthesis. This way, not only system-level assertions are reused in lower-levels of abstraction, but also run-time verification of system is provided. In this paper, we show the system-level assertions and their synthesis method in our object-oriented system-level synthesis methodology.
{"title":"Integrating assertion-based verification into system-level synthesis methodology","authors":"S. Hessabi, A. M. Gharehbaghi, B. H. Yaran, M. Goudarzi","doi":"10.1109/ICM.2004.1434254","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434254","url":null,"abstract":"In this paper, we integrate a verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification after system synthesis. We have defined a set of system-level assertions. These assertions are automatically converted to monitor hardware or monitor software during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertion, and hence, can he used to verify the system after HW/SW synthesis. This way, not only system-level assertions are reused in lower-levels of abstraction, but also run-time verification of system is provided. In this paper, we show the system-level assertions and their synthesis method in our object-oriented system-level synthesis methodology.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121686599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434217
N. Deve, A. Kouki, V. Nerguizian
This paper proposes a novel spiral topology for a reconfigurable stub tuner with radio-frequency micro electro mechanical system (RF MEMS) switches. The flexibility of the configuration permits the transformation from single to double and triple stub tuning covering a wide range of impedance values. Moreover, the number of switches present in the tuner dictates the range of loads to be matched. The design produces 2048 different impedances. The design of a spirally rolled parallel coplanar waveguide (CPW) transmission line tuner is presented along with simulation results. The proposed tuner provides real-time reconfiguration and matching for RF loads that could change during system operation. Real time intelligent algorithm would be used to control electronically the tuner. This proposed design would be used for military and high performance circuit applications for future low-cost and low-power intelligent RF micro systems and systems-on-chip.
{"title":"A compact size reconfigurable 1-3 GHz impedance tuner suitable for RF MEMS applications","authors":"N. Deve, A. Kouki, V. Nerguizian","doi":"10.1109/ICM.2004.1434217","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434217","url":null,"abstract":"This paper proposes a novel spiral topology for a reconfigurable stub tuner with radio-frequency micro electro mechanical system (RF MEMS) switches. The flexibility of the configuration permits the transformation from single to double and triple stub tuning covering a wide range of impedance values. Moreover, the number of switches present in the tuner dictates the range of loads to be matched. The design produces 2048 different impedances. The design of a spirally rolled parallel coplanar waveguide (CPW) transmission line tuner is presented along with simulation results. The proposed tuner provides real-time reconfiguration and matching for RF loads that could change during system operation. Real time intelligent algorithm would be used to control electronically the tuner. This proposed design would be used for military and high performance circuit applications for future low-cost and low-power intelligent RF micro systems and systems-on-chip.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"51 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132227979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434736
F. Rodes, O. Chevalerias, E. Garnier, M. Favre, D. Bastard
This paper presents how to design a RF transmitter with only two CMOS digital inverters. The RF oscillator is controlled by a fundamental mode quartz crystal operating in load resonance. The RF amplifier consists of one CMOS inverter, having the capability to produce an output power of 10 mW. An 8 elements matching and filtering network has been designed in order to match the CMOS transmitter's output to a 50 /spl Omega/ antenna, and to comply with the European telecommunication regulations.
{"title":"Design of a FSK RF transmitter with CMOS digital inverters","authors":"F. Rodes, O. Chevalerias, E. Garnier, M. Favre, D. Bastard","doi":"10.1109/ICM.2004.1434736","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434736","url":null,"abstract":"This paper presents how to design a RF transmitter with only two CMOS digital inverters. The RF oscillator is controlled by a fundamental mode quartz crystal operating in load resonance. The RF amplifier consists of one CMOS inverter, having the capability to produce an output power of 10 mW. An 8 elements matching and filtering network has been designed in order to match the CMOS transmitter's output to a 50 /spl Omega/ antenna, and to comply with the European telecommunication regulations.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130000305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434582
F. Abbes, E. Casseau, M. Abid, P. Coussy, J.B. Legoff
Integrating intellectual property (IP) components into system-on-chip (SoC) designs requires the use of a generic parameterizable hardware/software interface to increase reuse efficiently, quality and productivity of SoC design. In this paper, we propose a design approach for wrapping the cycle accurate bit accurate (CABA) interface of hardware IPs. This interface integrates many communication and synchronization mechanisms with respect to the virtual component interface (VCI) protocol from VSIA to fulfill IP designer and IP integrator requirements.
{"title":"IP integration methodology for SoC design","authors":"F. Abbes, E. Casseau, M. Abid, P. Coussy, J.B. Legoff","doi":"10.1109/ICM.2004.1434582","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434582","url":null,"abstract":"Integrating intellectual property (IP) components into system-on-chip (SoC) designs requires the use of a generic parameterizable hardware/software interface to increase reuse efficiently, quality and productivity of SoC design. In this paper, we propose a design approach for wrapping the cycle accurate bit accurate (CABA) interface of hardware IPs. This interface integrates many communication and synchronization mechanisms with respect to the virtual component interface (VCI) protocol from VSIA to fulfill IP designer and IP integrator requirements.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434721
L. Noury, H. Mehrez, F. Durbin, Tissot A
With increased complexity and shorter development cycle of hardware, designers cannot afford to redesign similar subcomponents. They have to focus on the global design, and must extract a validated netlist from the specification of some classic component, thus insuring good performance and adaptation to their needs. In this paper, we present the design methodology for a FIR filter netlist generator, the FIR filter being one of the most frequently used device in digital signal processing. Starting from mathematical equation and specification parameters, we include arithmetic knowledge in the generator, allowing architecture choices based on filter properties and realistic parameters values. We also provide a rounding option and a validation framework.
{"title":"Use of multiple numeration systems for architecture and design of a high performance FIR filter netlist generator","authors":"L. Noury, H. Mehrez, F. Durbin, Tissot A","doi":"10.1109/ICM.2004.1434721","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434721","url":null,"abstract":"With increased complexity and shorter development cycle of hardware, designers cannot afford to redesign similar subcomponents. They have to focus on the global design, and must extract a validated netlist from the specification of some classic component, thus insuring good performance and adaptation to their needs. In this paper, we present the design methodology for a FIR filter netlist generator, the FIR filter being one of the most frequently used device in digital signal processing. Starting from mathematical equation and specification parameters, we include arithmetic knowledge in the generator, allowing architecture choices based on filter properties and realistic parameters values. We also provide a rounding option and a validation framework.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133039113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434276
X. Zhao, R. Chebli, M. Sawan
In this paper, a new design for a voltage-controlled ring oscillator (VCO) is presented. Implemented in 0.8 /spl mu/m high-voltage CMOS/DMOS technology provided by DALSA semiconductor with 5 V power supply, this circuit uses relatively devices dimensions and low stages number to operate at low frequency. The new VCO combines three control methods to vary the oscillation frequency. The proposed VCO topology exhibits a very wide tuning range from 13 Hz to 407 MHz with good transient characteristics, which is difficult to get from the conventional VCO. Its power consumption at the maximum oscillation frequency is 29.2 mW.
{"title":"A wide tuning range voltage-controlled ring oscillator dedicated to ultrasound transmitter","authors":"X. Zhao, R. Chebli, M. Sawan","doi":"10.1109/ICM.2004.1434276","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434276","url":null,"abstract":"In this paper, a new design for a voltage-controlled ring oscillator (VCO) is presented. Implemented in 0.8 /spl mu/m high-voltage CMOS/DMOS technology provided by DALSA semiconductor with 5 V power supply, this circuit uses relatively devices dimensions and low stages number to operate at low frequency. The new VCO combines three control methods to vary the oscillation frequency. The proposed VCO topology exhibits a very wide tuning range from 13 Hz to 407 MHz with good transient characteristics, which is difficult to get from the conventional VCO. Its power consumption at the maximum oscillation frequency is 29.2 mW.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133449548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434251
L. de Carvalho Ferreira, T. Pimenta
This work describes a simple topology for implementing a low voltage rail-to-rail CMOS Miller OTA with differential pair using bulk driven and DC shifters. Since the transistors work on weak inversion, the topology requires a 600 mV power supply and consumes only 420 nW on the 0.35 /spl mu/m TSMC CMOS process. The voltage swing and the frequency response are almost independent of the power supply voltage that can change from 600 mV to 3.3 V (limit of this technology).
{"title":"An ultra low-voltage CMOS OTA Miller with rail-to-rail operation","authors":"L. de Carvalho Ferreira, T. Pimenta","doi":"10.1109/ICM.2004.1434251","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434251","url":null,"abstract":"This work describes a simple topology for implementing a low voltage rail-to-rail CMOS Miller OTA with differential pair using bulk driven and DC shifters. Since the transistors work on weak inversion, the topology requires a 600 mV power supply and consumes only 420 nW on the 0.35 /spl mu/m TSMC CMOS process. The voltage swing and the frequency response are almost independent of the power supply voltage that can change from 600 mV to 3.3 V (limit of this technology).","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131275766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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