Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434255
S. Ouadjaout, D. Houzet
The goal of our paper is to allow a rapid integration of SystemC IPs with several abstraction levels, in order to reduce the SoC design cost and time to market window. Our challenge is finding a way which allows the communication between IPs from different sources without changing their code or understand their interface of communication. We introduce in this article our design flow which include our own adaptation methodology of functional IP interface translation towards VCI interface. This methodology is performed through a custom SystemC adapters library.
{"title":"Rapid integration of reusable functional IPs with SystemC VCI adapters","authors":"S. Ouadjaout, D. Houzet","doi":"10.1109/ICM.2004.1434255","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434255","url":null,"abstract":"The goal of our paper is to allow a rapid integration of SystemC IPs with several abstraction levels, in order to reduce the SoC design cost and time to market window. Our challenge is finding a way which allows the communication between IPs from different sources without changing their code or understand their interface of communication. We introduce in this article our design flow which include our own adaptation methodology of functional IP interface translation towards VCI interface. This methodology is performed through a custom SystemC adapters library.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434229
K. Manochehri, S. Pourmozafari
Montgomery modular multiplication algorithm is commonly used in implementations of the RSA cryptosystem or other cryptosystems based on modular arithmetic. There are several architectures for speed up its calculations. In this paper, we use carry save adder (CSA) architecture and pipeline it to increase its performance. We show that this architecture has greater performance for FPGA design than other architectures. Hence, it is appropriate for RSA processors based on FPGAs.
{"title":"Fast Montgomery modular multiplication by pipelined CSA architecture","authors":"K. Manochehri, S. Pourmozafari","doi":"10.1109/ICM.2004.1434229","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434229","url":null,"abstract":"Montgomery modular multiplication algorithm is commonly used in implementations of the RSA cryptosystem or other cryptosystems based on modular arithmetic. There are several architectures for speed up its calculations. In this paper, we use carry save adder (CSA) architecture and pipeline it to increase its performance. We show that this architecture has greater performance for FPGA design than other architectures. Hence, it is appropriate for RSA processors based on FPGAs.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122824297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434784
M. Issam, G. Guy, A. Mohamed, P.J. Luc
Generally, system designers use their own experience to define SoC architecture. However, the system design space is growing increasingly, due to the great choice of potential hardware and software resources. This characteristic leads to raise the complexity of defining an efficient and flexible architecture for actual and future systems. Hence, fast, automatic (or interactive) and efficient exploration of the system design space is mandatory. To define an appropriate architecture for an application, a thorough analysis of the application is necessary. In this paper, we define several metrics that allow analyzing the system characteristics at a high level of abstraction. They enable also to evaluate the impact on the system performances of tasks clustering. As the proposed metrics have an important impact on the final system performances they are considered during the first steps of the design flow before any architecture definition and hardware-software partitioning. Several experimental results performed on an UMTS application demonstrate the efficiency of these metrics to exhibit the main characteristics of an application. The results also show the benefit of considering during the first steps of the design flow different metrics in order to build an architecture that leads to an efficient implementation of the application.
{"title":"Metrics for multiprocessor system on chip","authors":"M. Issam, G. Guy, A. Mohamed, P.J. Luc","doi":"10.1109/ICM.2004.1434784","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434784","url":null,"abstract":"Generally, system designers use their own experience to define SoC architecture. However, the system design space is growing increasingly, due to the great choice of potential hardware and software resources. This characteristic leads to raise the complexity of defining an efficient and flexible architecture for actual and future systems. Hence, fast, automatic (or interactive) and efficient exploration of the system design space is mandatory. To define an appropriate architecture for an application, a thorough analysis of the application is necessary. In this paper, we define several metrics that allow analyzing the system characteristics at a high level of abstraction. They enable also to evaluate the impact on the system performances of tasks clustering. As the proposed metrics have an important impact on the final system performances they are considered during the first steps of the design flow before any architecture definition and hardware-software partitioning. Several experimental results performed on an UMTS application demonstrate the efficiency of these metrics to exhibit the main characteristics of an application. The results also show the benefit of considering during the first steps of the design flow different metrics in order to build an architecture that leads to an efficient implementation of the application.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116866916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434716
R. Benachour, S. Latreche, M. Latreche, C. Gontrand
Recent developments in very-large-scale integration (VLSI) technology have radically affected the design process based on DSP. Thus, in recent years, the development of application specific integrated circuit (ASIC) has made possible to integrate complex analog, digital and power circuits. The integration design of power electronic for the induction machines (IM) control is a difficult spot. This later is based on multiple fields which includes: power electronics, control algorithm, analog/digital design, electromagnetic compatibility (EMC)... etc. The principal stage is an analysis based on a behavioural model to realise, with an association of multiple level's descriptions. This later includes the average model of the voltage inverter.
{"title":"An average model for power integration design","authors":"R. Benachour, S. Latreche, M. Latreche, C. Gontrand","doi":"10.1109/ICM.2004.1434716","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434716","url":null,"abstract":"Recent developments in very-large-scale integration (VLSI) technology have radically affected the design process based on DSP. Thus, in recent years, the development of application specific integrated circuit (ASIC) has made possible to integrate complex analog, digital and power circuits. The integration design of power electronic for the induction machines (IM) control is a difficult spot. This later is based on multiple fields which includes: power electronics, control algorithm, analog/digital design, electromagnetic compatibility (EMC)... etc. The principal stage is an analysis based on a behavioural model to realise, with an association of multiple level's descriptions. This later includes the average model of the voltage inverter.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115380499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1093/ietele/e88-c.6.1122
E. Fathi, A. Behnam, P. Hashemi, B. Esfandyarpour, M. Fathipour
An asymmetric dual metal stack gate (DMSG) SOI MOSFET transistor has been investigated for its enhanced electrical characteristics. A 2-D physical model has been proposed and its results have been confirmed by those obtained by simulation. These results predict better short channel effects such as drain induced barrier lowering (DIBL) characteristics and hot carrier effects for this device compared to those for the conventional SOI MOSFET.
研究了一种非对称双金属堆叠栅极(DMSG) SOI MOSFET晶体管的增强电学特性。提出了一种二维物理模型，并与仿真结果相吻合。这些结果预测，与传统的SOI MOSFET相比，该器件具有更好的短通道效应，如漏极诱导势垒降低(DIBL)特性和热载子效应。
{"title":"The influence of the stacked and double material gate structures on the short channel effects in SOI MOSFETs","authors":"E. Fathi, A. Behnam, P. Hashemi, B. Esfandyarpour, M. Fathipour","doi":"10.1093/ietele/e88-c.6.1122","DOIUrl":"https://doi.org/10.1093/ietele/e88-c.6.1122","url":null,"abstract":"An asymmetric dual metal stack gate (DMSG) SOI MOSFET transistor has been investigated for its enhanced electrical characteristics. A 2-D physical model has been proposed and its results have been confirmed by those obtained by simulation. These results predict better short channel effects such as drain induced barrier lowering (DIBL) characteristics and hot carrier effects for this device compared to those for the conventional SOI MOSFET.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114788721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434704
M. Aslam
The thermosonic gold wire bonding is a common technology in microelectronics industry for reliable bonding. The bondability of metallisation on soft material like polyimide (PI) is a matter of concern, especially when the bond pads are made of thin coating of platinum material. Nano-indentation technique is commonly used to measure surface properties of thin film coatings, such as Young's modulus and hardness within sub-micron scale. Four different samples were produced by sputtering different thickness of Pt on polyimide substrate to study the behaviour of thickness versus applied load of indentor. The nano-indentation data regarding "load versus displacement" and "hardness versus displacement" for all the four samples were collected and deformation behaviour and mechanical properties of thin film platinum material had been investigated. In this paper, the analysis of platinum pads has been carried out and it was observed that the samples with 300 nm platinum layer on polyimide were bonded well as compared to 100 nm thickness of platinum material.
{"title":"Analysis of platinum bond pads on polyimide soft substrate for wire bonding with Au wire using nano-indentation technique","authors":"M. Aslam","doi":"10.1109/ICM.2004.1434704","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434704","url":null,"abstract":"The thermosonic gold wire bonding is a common technology in microelectronics industry for reliable bonding. The bondability of metallisation on soft material like polyimide (PI) is a matter of concern, especially when the bond pads are made of thin coating of platinum material. Nano-indentation technique is commonly used to measure surface properties of thin film coatings, such as Young's modulus and hardness within sub-micron scale. Four different samples were produced by sputtering different thickness of Pt on polyimide substrate to study the behaviour of thickness versus applied load of indentor. The nano-indentation data regarding \"load versus displacement\" and \"hardness versus displacement\" for all the four samples were collected and deformation behaviour and mechanical properties of thin film platinum material had been investigated. In this paper, the analysis of platinum pads has been carried out and it was observed that the samples with 300 nm platinum layer on polyimide were bonded well as compared to 100 nm thickness of platinum material.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127155171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434744
S. Poriazis
The behavior of the 1:6 phased demultiplexer (PDMUX6) circuit is analyzed. The circuit demultiplexes the input clock signal into six phased output signals by streaming sets of twelve clock phases. A phase difference equal to the half period of the clock is maintained between consecutive output transitions. The VHDL description of the PDMUX6 cell is given and the simulation and synthesis results are generated. A 2-level tree-like structure is built by applying the phased outputs of the PDMUX6 cell into the corresponding clock inputs of six cell replicas that extend the circuit behavior. The EXOR6 gate is attached to the PDMUX6 cell output ports and is aggregating all the phases that the phased clock signals are carrying while preserving their phase associations.
{"title":"The 1:6 phased demultiplexer circuit","authors":"S. Poriazis","doi":"10.1109/ICM.2004.1434744","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434744","url":null,"abstract":"The behavior of the 1:6 phased demultiplexer (PDMUX6) circuit is analyzed. The circuit demultiplexes the input clock signal into six phased output signals by streaming sets of twelve clock phases. A phase difference equal to the half period of the clock is maintained between consecutive output transitions. The VHDL description of the PDMUX6 cell is given and the simulation and synthesis results are generated. A 2-level tree-like structure is built by applying the phased outputs of the PDMUX6 cell into the corresponding clock inputs of six cell replicas that extend the circuit behavior. The EXOR6 gate is attached to the PDMUX6 cell output ports and is aggregating all the phases that the phased clock signals are carrying while preserving their phase associations.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126104112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434201
F. Thabet, J.-B. Le Goff, P. Coussy, E. Martin
Modern systems become more and more complex and tendency turn to the integration on one single chip: system on chip (SoC). SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware/software systems. This paper describes a method of stepwise communication refinement with SystemC, starting from an algorithmic description and progressively adding implementation details for both data type and timing constraints. We show the effectiveness of our approach with an experiment based on a discrete cosine transform DCT algorithm.
{"title":"A methodology for timing and structural communication refinement in DSP systems","authors":"F. Thabet, J.-B. Le Goff, P. Coussy, E. Martin","doi":"10.1109/ICM.2004.1434201","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434201","url":null,"abstract":"Modern systems become more and more complex and tendency turn to the integration on one single chip: system on chip (SoC). SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware/software systems. This paper describes a method of stepwise communication refinement with SystemC, starting from an algorithmic description and progressively adding implementation details for both data type and timing constraints. We show the effectiveness of our approach with an experiment based on a discrete cosine transform DCT algorithm.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128128422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434747
S. H. Sfar, I. Bennour, S. Kamel, A. Beganne, R. Tourki
System models with level of abstractions higher than behavior-level and register-transfer-level are essential to handle the increasing complexity of system on chip (SoC) designs. Recently, many system level abstraction models have been developed. The first part of this paper presents the most stable of these models and their behind design methodologies. The second part shows how these models and methodologies are used for MicroNetwork designs.
{"title":"System level abstraction models and application to MicroNetwork design","authors":"S. H. Sfar, I. Bennour, S. Kamel, A. Beganne, R. Tourki","doi":"10.1109/ICM.2004.1434747","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434747","url":null,"abstract":"System models with level of abstractions higher than behavior-level and register-transfer-level are essential to handle the increasing complexity of system on chip (SoC) designs. Recently, many system level abstraction models have been developed. The first part of this paper presents the most stable of these models and their behind design methodologies. The second part shows how these models and methodologies are used for MicroNetwork designs.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122744519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434730
D. Benatia, M. Benslama
In this paper, we propose a new approach for bulk and leaky detection of an acoustic microwave signal. For this reason, we have used a wavelet transform as a numerical analysis method. The originality of this model consists of the local analysis signal singularities where abrupt events appear and hence access to hidden information by using the scale of this transform as up scaling parameters. These singularities inform us of the presence of bulk and leaky waves.
{"title":"Detection of bulk and leaky acoustic microwaves in piezoelectric crystal by wavelet technique","authors":"D. Benatia, M. Benslama","doi":"10.1109/ICM.2004.1434730","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434730","url":null,"abstract":"In this paper, we propose a new approach for bulk and leaky detection of an acoustic microwave signal. For this reason, we have used a wavelet transform as a numerical analysis method. The originality of this model consists of the local analysis signal singularities where abrupt events appear and hence access to hidden information by using the scale of this transform as up scaling parameters. These singularities inform us of the presence of bulk and leaky waves.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"77 2 Suppl 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123230740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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