Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434578
S. Ben Salem, A. Fakhfakh, M. Loulou, P. Loumeau, N. Masmoudi
In this paper, we present a design of a CMOS current conveyor. Thus, the first step in our design was to improve static and dynamic behavior of second generation current conveyors. The translinear implementation in CMOS technology was first studied. We notice that it presents a lower RX than those of Y and Z. However, this value (about 1 k/spl Omega/) may reduces the RF design's performances such as filters and oscillators, so it became necessary to make an implementation of a new improved CCII structure for RF design's implementation. This new structure is used as a basic building block of a tunable current and voltage mode band-pass filter. The Q-factor and the central frequency can be electronically controlled by mean of DC bias current. To validate this result, a Pspice simulation results are presented showing very interesting frequency and Q factor performances (the central frequency is tunable in the range of 1.2-1.6 GHz and Q from 80 to 313).
{"title":"A 2.5 V 0.35 /spl mu/m CMOS current conveyor and high frequency high-Q band-pass filter","authors":"S. Ben Salem, A. Fakhfakh, M. Loulou, P. Loumeau, N. Masmoudi","doi":"10.1109/ICM.2004.1434578","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434578","url":null,"abstract":"In this paper, we present a design of a CMOS current conveyor. Thus, the first step in our design was to improve static and dynamic behavior of second generation current conveyors. The translinear implementation in CMOS technology was first studied. We notice that it presents a lower RX than those of Y and Z. However, this value (about 1 k/spl Omega/) may reduces the RF design's performances such as filters and oscillators, so it became necessary to make an implementation of a new improved CCII structure for RF design's implementation. This new structure is used as a basic building block of a tunable current and voltage mode band-pass filter. The Q-factor and the central frequency can be electronically controlled by mean of DC bias current. To validate this result, a Pspice simulation results are presented showing very interesting frequency and Q factor performances (the central frequency is tunable in the range of 1.2-1.6 GHz and Q from 80 to 313).","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123809401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434239
M. Fakhfakh, M. Loulou, N. Masmoudi
Optimally designing switched current (SI) memory cells is a very tedious process. In addition, it is usually limited to the design of ideal cells. Thus, in this paper, we deal with fully optimizing these cells and particularly real cells. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design these cells. Also, besides maximizing performances and minimizing famous error sources, we focus on optimally sizing transistors forming switches and bias currents. The optimization procedure, developed in C++ software, allows automatic design of the cell. It is also highlighted in the followings. The cell designed with the use of CMOS 0.35 /spl mu/m process under a single 3.3 V power voltage supply, achieves more than 83.6 dB as a dynamic range and reaches less than 3.5 ns as settling time.
{"title":"An improved heuristic for optimizing SI memory cells application: a fully optimized SI class AB grounded gate cell","authors":"M. Fakhfakh, M. Loulou, N. Masmoudi","doi":"10.1109/ICM.2004.1434239","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434239","url":null,"abstract":"Optimally designing switched current (SI) memory cells is a very tedious process. In addition, it is usually limited to the design of ideal cells. Thus, in this paper, we deal with fully optimizing these cells and particularly real cells. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design these cells. Also, besides maximizing performances and minimizing famous error sources, we focus on optimally sizing transistors forming switches and bias currents. The optimization procedure, developed in C++ software, allows automatic design of the cell. It is also highlighted in the followings. The cell designed with the use of CMOS 0.35 /spl mu/m process under a single 3.3 V power voltage supply, achieves more than 83.6 dB as a dynamic range and reaches less than 3.5 ns as settling time.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434227
M. Masmoudi, I. Song, F. Karray, M. Masmoudi, N. Derbel
The objective of this study concerns the design and implementation of a complete intelligent mechatronic system. The basic idea uses the concept of car maneuvers; control (fuzzy logic controller) and sensor-based behaviors together merged to implement the wall-following control algorithm. The fuzzy logic control algorithm (FLC) was considered as the heart of the controller due to the advantage of its easy implementation on an FPGA (field programmable gate array). The FLC is implemented on a compact custom FPGA board, which provides a powerful reconfigurable hardware platform and software design, at the same time. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the prototype car for a task of wall-following and obstacle avoidance. Experimental results on a car-like robot show that the algorithm proposed can successfully navigate the robot to follow the wall in an unknown and changing environment.
{"title":"FPGA implementation of fuzzy wall-following control","authors":"M. Masmoudi, I. Song, F. Karray, M. Masmoudi, N. Derbel","doi":"10.1109/ICM.2004.1434227","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434227","url":null,"abstract":"The objective of this study concerns the design and implementation of a complete intelligent mechatronic system. The basic idea uses the concept of car maneuvers; control (fuzzy logic controller) and sensor-based behaviors together merged to implement the wall-following control algorithm. The fuzzy logic control algorithm (FLC) was considered as the heart of the controller due to the advantage of its easy implementation on an FPGA (field programmable gate array). The FLC is implemented on a compact custom FPGA board, which provides a powerful reconfigurable hardware platform and software design, at the same time. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the prototype car for a task of wall-following and obstacle avoidance. Experimental results on a car-like robot show that the algorithm proposed can successfully navigate the robot to follow the wall in an unknown and changing environment.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115010817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434772
A. Boudabous, F. Ghozzi, M. W. Kharrat, Nouri Masmoudi
In this paper, we present a new design of hyperbolic functions in order to implement logarithm and exponential functions using CORDIC algorithm (coordinate rotation digital computer). FPGA enable effective implementation of CORDIC algorithm in hardware, which is usually associated with "shift & add" hardware primitives. A comparison with Taylor precision was done to choose the best equation precision order. To valid CORDIC implementation, correction was introduced to remain in logarithm and exponential convergence range. We present simulation and synthesis results and comparison using ModelSim and Synplify/spl I.bar/Pro Xilinx tools.
{"title":"Implementation of hyperbolic functions using CORDIC algorithm","authors":"A. Boudabous, F. Ghozzi, M. W. Kharrat, Nouri Masmoudi","doi":"10.1109/ICM.2004.1434772","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434772","url":null,"abstract":"In this paper, we present a new design of hyperbolic functions in order to implement logarithm and exponential functions using CORDIC algorithm (coordinate rotation digital computer). FPGA enable effective implementation of CORDIC algorithm in hardware, which is usually associated with \"shift & add\" hardware primitives. A comparison with Taylor precision was done to choose the best equation precision order. To valid CORDIC implementation, correction was introduced to remain in logarithm and exponential convergence range. We present simulation and synthesis results and comparison using ModelSim and Synplify/spl I.bar/Pro Xilinx tools.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132387036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434720
H. Loukil, F. Ghozzi, A. Samet, M. A. Ben Ayed, N. Masmoudi
In MPEG and VCEG standards, motion estimation is used to eliminate the temporal redundancy. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a reconfigurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present the design of a motion estimation circuit and its hardware implementation on FPGA based on "full search block matching" algorithm according to H.263 standard. We specified, simulated, and synthesized SAD's engine with VHDL description. The proposed design is implemented on a "stratix" FPGA using EPIS10B672C6 component. Our simulations confirm the functionality of the algorithm using "ModelSim" simulator and synthesis using the "Quartus" software provided by ALTERA. This study represents a mean stone for FPGA implementation of motion estimation algorithms.
{"title":"Hardware implementation of block matching algorithm with FPGA technology","authors":"H. Loukil, F. Ghozzi, A. Samet, M. A. Ben Ayed, N. Masmoudi","doi":"10.1109/ICM.2004.1434720","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434720","url":null,"abstract":"In MPEG and VCEG standards, motion estimation is used to eliminate the temporal redundancy. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a reconfigurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present the design of a motion estimation circuit and its hardware implementation on FPGA based on \"full search block matching\" algorithm according to H.263 standard. We specified, simulated, and synthesized SAD's engine with VHDL description. The proposed design is implemented on a \"stratix\" FPGA using EPIS10B672C6 component. Our simulations confirm the functionality of the algorithm using \"ModelSim\" simulator and synthesis using the \"Quartus\" software provided by ALTERA. This study represents a mean stone for FPGA implementation of motion estimation algorithms.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115096857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434718
A. Bouzidi, A. Bouazzi, B. Rezig
In this work, we simulate and optimize the photocurrent densities in a model of an n-p-n-p type thin film multilayer silicon solar cell. The equations giving the photocurrent density produced in each abscissa of the structure was developed. We used Matlab software to simulate and optimize the different parameters of the model. The results of simulation show that the optimized n-p-n-p silicon multilayer solar cell could deliver a photocurrent density of more than 47 mA/cm/sup 2/. We also show that the most important components of the total photocurrent densities are due to the minority carrier collection which happens on both side of the three space charge regions tailored inside the cell.
{"title":"Simulation of a n-p-n-p silicon multilayer solar cell","authors":"A. Bouzidi, A. Bouazzi, B. Rezig","doi":"10.1109/ICM.2004.1434718","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434718","url":null,"abstract":"In this work, we simulate and optimize the photocurrent densities in a model of an n-p-n-p type thin film multilayer silicon solar cell. The equations giving the photocurrent density produced in each abscissa of the structure was developed. We used Matlab software to simulate and optimize the different parameters of the model. The results of simulation show that the optimized n-p-n-p silicon multilayer solar cell could deliver a photocurrent density of more than 47 mA/cm/sup 2/. We also show that the most important components of the total photocurrent densities are due to the minority carrier collection which happens on both side of the three space charge regions tailored inside the cell.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116182403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434213
A. Madan, G. S. Sandha
Localized heating of different areas in integrated circuits induces thermal gradient currents to flow across the semiconductor chip, which results in non-ideal performance characteristics. This paper introduces thermal gradient corrections in a novel, hardware implementable way in terms of overhead requirement and power consumption over the existing models which involves use of CCVS and VCVS for corrections to the MOS device as well as the integrated circuit to annul any distortion due to thermal gradient issues. Thus, this work has advantages of large-scale integration due to highly reduced lower area overhead. The corrections are based on quantitative analysis of the thermal gradients flowing in an integrated circuit.
{"title":"Reduced area overhead thermal gradient correction for a MOS IC","authors":"A. Madan, G. S. Sandha","doi":"10.1109/ICM.2004.1434213","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434213","url":null,"abstract":"Localized heating of different areas in integrated circuits induces thermal gradient currents to flow across the semiconductor chip, which results in non-ideal performance characteristics. This paper introduces thermal gradient corrections in a novel, hardware implementable way in terms of overhead requirement and power consumption over the existing models which involves use of CCVS and VCVS for corrections to the MOS device as well as the integrated circuit to annul any distortion due to thermal gradient issues. Thus, this work has advantages of large-scale integration due to highly reduced lower area overhead. The corrections are based on quantitative analysis of the thermal gradients flowing in an integrated circuit.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434211
M. Simion, A. Angelescu, I. Kleps, M. Miu, M. Avram, F. Craciunoiu, T. Ignat, A. Bragaru
Over the past years there have been a number of recent advances in the fields of miniaturized chemical reactions, including the construction of fully integrated 'lab-on-chip' system. The term of biochip has been used in various contexts, but can be defined as "microelectronic device used for processing (delivery, analyses, or detection) of biological molecules and species". This paper describes a micro fluidic biochip realized on silicon wafers using standard micro fabrication techniques. The biochip is designed to be complex and versatile; it contains: reservoirs (wells), microchannels and the main microreactor for the biological material. The cell behaviour in the test reactors can be optically monitored during the exhibition to various stimuli such as drug solutions, electric impulses, or change of the temperature. Two or three electrodes are foreseen in order to investigate the electrical and electrochemical activity of the biological material. On the backside of the chip heating resistances would assure a constant body fluid temperature or other temperature cycles.
{"title":"Micro fluidic biochip for bio-medical application","authors":"M. Simion, A. Angelescu, I. Kleps, M. Miu, M. Avram, F. Craciunoiu, T. Ignat, A. Bragaru","doi":"10.1109/ICM.2004.1434211","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434211","url":null,"abstract":"Over the past years there have been a number of recent advances in the fields of miniaturized chemical reactions, including the construction of fully integrated 'lab-on-chip' system. The term of biochip has been used in various contexts, but can be defined as \"microelectronic device used for processing (delivery, analyses, or detection) of biological molecules and species\". This paper describes a micro fluidic biochip realized on silicon wafers using standard micro fabrication techniques. The biochip is designed to be complex and versatile; it contains: reservoirs (wells), microchannels and the main microreactor for the biological material. The cell behaviour in the test reactors can be optically monitored during the exhibition to various stimuli such as drug solutions, electric impulses, or change of the temperature. Two or three electrodes are foreseen in order to investigate the electrical and electrochemical activity of the biological material. On the backside of the chip heating resistances would assure a constant body fluid temperature or other temperature cycles.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133114795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434708
M. Saneei, A. Afzali-Kusha, Z. Navabi
This paper proposes a new low power technique, called SBR (sign bit reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers based on this scheme, the dynamic power consumption of digital filters based on CMOS logic system can be reduced considerably compared to those based on 2's complement implementation. To verify the efficacy of the SBR, a 16-bit multiplier was implemented by the scheme. The results for voice data show an average of 29% to 35% switching reduction compared to the 2's complement implementation. For 16-bit random data, the scheme decreases the switching of 16-bit multipliers by an average of 21%. Finally, the application of the technique to a 16-bit data bus leads to 9.9% to 14.5% switching reduction on average.
{"title":"A low power technique based on sign bit reduction","authors":"M. Saneei, A. Afzali-Kusha, Z. Navabi","doi":"10.1109/ICM.2004.1434708","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434708","url":null,"abstract":"This paper proposes a new low power technique, called SBR (sign bit reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers based on this scheme, the dynamic power consumption of digital filters based on CMOS logic system can be reduced considerably compared to those based on 2's complement implementation. To verify the efficacy of the SBR, a 16-bit multiplier was implemented by the scheme. The results for voice data show an average of 29% to 35% switching reduction compared to the 2's complement implementation. For 16-bit random data, the scheme decreases the switching of 16-bit multipliers by an average of 21%. Finally, the application of the technique to a 16-bit data bus leads to 9.9% to 14.5% switching reduction on average.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"12 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125720283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434212
L. de Carvalho Ferreira, T. Pimenta
This work describes a methodology for the extraction of DC parameters of MOS transistors on weak inversion from BSIM3v3 model. Once the optimum model for manual calculations has been defined, the parameters are obtained using the minimum square method. The results show that the proposed method improves the precision of the transistors 'dimensions' calculations, by giving a determination index r/sup 3/ to the I vs V relation, which is 99.31% of the worst case, when compared to the BSIM3v3.
{"title":"The use of extracted BSIM3v3 MOS parameters for fast design of circuits on weak inversion","authors":"L. de Carvalho Ferreira, T. Pimenta","doi":"10.1109/ICM.2004.1434212","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434212","url":null,"abstract":"This work describes a methodology for the extraction of DC parameters of MOS transistors on weak inversion from BSIM3v3 model. Once the optimum model for manual calculations has been defined, the parameters are obtained using the minimum square method. The results show that the proposed method improves the precision of the transistors 'dimensions' calculations, by giving a determination index r/sup 3/ to the I vs V relation, which is 99.31% of the worst case, when compared to the BSIM3v3.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129585657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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