Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301761
M. Rebaiaia, J. Jaam, A. Hasnah
Formal verification is the task of proving that a property holds for a model of a design. This paper examines the idea of a Neural Network-based algorithm used to find the set of states that makes a specification valid. The paper addresses a singular approach for those doing theoretical research for the verification of soft programs, and, for hardware designers. The approach of the application of the Artificial Neural Network is not new, but it becomes interesting if one can improve the truth-building efficiency by using some known artifices. Topics described include Integer Linear Programming, Propositional Logic, Model Checking, Satisfiability problems (SAT) and Artificial Neural Networks (ANN).
{"title":"A neural network algorithm for hardware-software verification","authors":"M. Rebaiaia, J. Jaam, A. Hasnah","doi":"10.1109/ICECS.2003.1301761","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301761","url":null,"abstract":"Formal verification is the task of proving that a property holds for a model of a design. This paper examines the idea of a Neural Network-based algorithm used to find the set of states that makes a specification valid. The paper addresses a singular approach for those doing theoretical research for the verification of soft programs, and, for hardware designers. The approach of the application of the Artificial Neural Network is not new, but it becomes interesting if one can improve the truth-building efficiency by using some known artifices. Topics described include Integer Linear Programming, Propositional Logic, Model Checking, Satisfiability problems (SAT) and Artificial Neural Networks (ANN).","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"64 1","pages":"1332-1335 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77933887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301695
Hongwei Zhu, O. Basir
This paper presents a fuzzy and evidential reasoning approach for segmenting main brain tissues: white matter (WM), grey matter (GM), and cerebrospinal fluid (CSF), as well as detecting multiple sclerosis lesions (MS) based on multi-modality MR images. The method performs intensity based tissue segmentation using a fuzzy Dempster-Shafer evidential reasoning data fusion scheme while MS lesions are detected by means of a fuzzy inferencing scheme. The approach is fully automated and unsupervised. Experiments have been carried out for segmenting 15 axial slices of multi-modality MR images obtained from the Simulated Brain Database (SBD). The average overall accuracy is 96.77% for segmenting tissues CSF, GM, and WM. The average sensitivity is 84.34%, and the average similarity index is 81.94% in MS detection in terms of ground truth images.
{"title":"Automated brain tissue segmentation and MS lesion detection using fuzzy and evidential reasoning","authors":"Hongwei Zhu, O. Basir","doi":"10.1109/ICECS.2003.1301695","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301695","url":null,"abstract":"This paper presents a fuzzy and evidential reasoning approach for segmenting main brain tissues: white matter (WM), grey matter (GM), and cerebrospinal fluid (CSF), as well as detecting multiple sclerosis lesions (MS) based on multi-modality MR images. The method performs intensity based tissue segmentation using a fuzzy Dempster-Shafer evidential reasoning data fusion scheme while MS lesions are detected by means of a fuzzy inferencing scheme. The approach is fully automated and unsupervised. Experiments have been carried out for segmenting 15 axial slices of multi-modality MR images obtained from the Simulated Brain Database (SBD). The average overall accuracy is 96.77% for segmenting tissues CSF, GM, and WM. The average sensitivity is 84.34%, and the average similarity index is 81.94% in MS detection in terms of ground truth images.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"85 1","pages":"1070-1073 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78159517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301856
A. El-Maleh
One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequency-directed run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the Geometric-Primitives-Based compression technique.
{"title":"A hybrid test compression technique for efficient testing of systems-on-a-chip","authors":"A. El-Maleh","doi":"10.1109/ICECS.2003.1301856","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301856","url":null,"abstract":"One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequency-directed run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the Geometric-Primitives-Based compression technique.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"21 1","pages":"599-602 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72824879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302031
S. Koziel, S. Szczepański
In the paper, an algebraic model of continuous-time G/sub m/-LC filter is presented. It is shown that any filter of this class (both voltage- and current-mode) is a particular case of the presented general structure. The theoretical considerations and the introduced formalism are accompanied by the application example to synthesis of odd-order low-pass elliptic G/sub m/-LC filter.
{"title":"Algebraic model of continuous-time G/sub m/-LC filters and applications","authors":"S. Koziel, S. Szczepański","doi":"10.1109/ICECS.2003.1302031","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302031","url":null,"abstract":"In the paper, an algebraic model of continuous-time G/sub m/-LC filter is presented. It is shown that any filter of this class (both voltage- and current-mode) is a particular case of the presented general structure. The theoretical considerations and the introduced formalism are accompanied by the application example to synthesis of odd-order low-pass elliptic G/sub m/-LC filter.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"3 1","pages":"280-283 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73362290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301855
L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni
In this paper, a novel scheme for testing LC-tank CMOS Voltage Controlled Oscillators (VCOs) is presented. The proposed test circuit is capable of detecting soft and hard faults in a percentage that can guarantee safe overall fault coverage. It has been realized that the proposed technique is capable of detecting open and short circuits as well as process variations outside the specified limits in the passive components of the VCO in a percentage that exceeds 93%. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit, which additionally presents negligible silicon area requirements in the design process.
{"title":"A novel scheme for testing radio frequency voltage controlled oscillators","authors":"L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni","doi":"10.1109/ICECS.2003.1301855","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301855","url":null,"abstract":"In this paper, a novel scheme for testing LC-tank CMOS Voltage Controlled Oscillators (VCOs) is presented. The proposed test circuit is capable of detecting soft and hard faults in a percentage that can guarantee safe overall fault coverage. It has been realized that the proposed technique is capable of detecting open and short circuits as well as process variations outside the specified limits in the passive components of the VCO in a percentage that exceeds 93%. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit, which additionally presents negligible silicon area requirements in the design process.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"9 1","pages":"595-598 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82277037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302032
I. A. Awad, S. Mahmoud, A. Soliman
A new CMOS buffer is introduced. A compensation circuit is used to cancel the output voltage offset resulting from the body effect. The voltage offset cancellation is achieved over all the input range, hence resulting in a highly linear voltage transfer gain, which is independent of process variation. A class AB output stage is used in order to minimize the power consumption and increase the driving capability of the buffer. PSpice simulations for the proposed buffer are given to confirm the theoretical analysis.
{"title":"Novel compensated CMOS buffer","authors":"I. A. Awad, S. Mahmoud, A. Soliman","doi":"10.1109/ICECS.2003.1302032","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302032","url":null,"abstract":"A new CMOS buffer is introduced. A compensation circuit is used to cancel the output voltage offset resulting from the body effect. The voltage offset cancellation is achieved over all the input range, hence resulting in a highly linear voltage transfer gain, which is independent of process variation. A class AB output stage is used in order to minimize the power consumption and increase the driving capability of the buffer. PSpice simulations for the proposed buffer are given to confirm the theoretical analysis.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"32 1","pages":"284-287 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81683125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302029
S. Koziel, S. Szczepański
In the paper, novel canonic structures of odd-order continuous-time elliptic G/sub m/-C filters are proposed and discussed. The structures are characterized by very small number of components, especially transconductance amplifiers. This makes them suitable for low-power and low-sensitivity applications. A detailed comparison of the novel third order structure and other implementations such as leap-frog with distributed input and leap-frog with floating capacitor is carried out including sensitivity and other properties important for IC implementation.
{"title":"Canonic structures of odd-order elliptic G/sub m/-C filters","authors":"S. Koziel, S. Szczepański","doi":"10.1109/ICECS.2003.1302029","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302029","url":null,"abstract":"In the paper, novel canonic structures of odd-order continuous-time elliptic G/sub m/-C filters are proposed and discussed. The structures are characterized by very small number of components, especially transconductance amplifiers. This makes them suitable for low-power and low-sensitivity applications. A detailed comparison of the novel third order structure and other implementations such as leap-frog with distributed input and leap-frog with floating capacitor is carried out including sensitivity and other properties important for IC implementation.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"87 1","pages":"272-275 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78644282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301702
C. Jou, Kuo-Hua Cheng, H. Hsieh
A low power voltage-controlled oscillator (VCO) for IEEE 802.11b direct conversion receiver is demonstrated. The VCO is fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is -73.62dBc/Hz@600 kHz offset and -82.44dBc/Hz@1MHz offset at 2.4GHz. The circuit draws only 53/spl mu/A current for the VCO core from a 1.5V supply.
{"title":"An ultra low power 2.4GHz CMOS VCO","authors":"C. Jou, Kuo-Hua Cheng, H. Hsieh","doi":"10.1109/ICECS.2003.1301702","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301702","url":null,"abstract":"A low power voltage-controlled oscillator (VCO) for IEEE 802.11b direct conversion receiver is demonstrated. The VCO is fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is -73.62dBc/Hz@600 kHz offset and -82.44dBc/Hz@1MHz offset at 2.4GHz. The circuit draws only 53/spl mu/A current for the VCO core from a 1.5V supply.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"66 1","pages":"1098-1100 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76458734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301912
I. Grech, J. Micallef, G. Azzopardi, C. J. Debono
The G/sub m/-C technique is extensively used for continuous-time filtering applications because it results in tunable, wideband and compact designs. In this paper, an OTA capable of operating at a supply voltage of 0.9 V is proposed using a novel bulk-input differential pair without the use of a tail current source. Good CMRR (63 dB) is still achieved by using the gate terminal to control the total current in the differential pair, via the use of a dummy pair. The OTA also exhibits a wide differential input range of /spl plusmn/ 600 mV and good G/sub m/- tunability. Simulation and test results are also presented with the OTA used in a second order cochlea low-pass filter. For this design, a standard double-poly double-metal CMOS process has been used, having a nominal threshold voltage of around 0.7 V.
{"title":"A 0.9 V wide-input-range bulk-input CMOS OTA for G/sub m/-C filters","authors":"I. Grech, J. Micallef, G. Azzopardi, C. J. Debono","doi":"10.1109/ICECS.2003.1301912","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301912","url":null,"abstract":"The G/sub m/-C technique is extensively used for continuous-time filtering applications because it results in tunable, wideband and compact designs. In this paper, an OTA capable of operating at a supply voltage of 0.9 V is proposed using a novel bulk-input differential pair without the use of a tail current source. Good CMRR (63 dB) is still achieved by using the gate terminal to control the total current in the differential pair, via the use of a dummy pair. The OTA also exhibits a wide differential input range of /spl plusmn/ 600 mV and good G/sub m/- tunability. Simulation and test results are also presented with the OTA used in a second order cochlea low-pass filter. For this design, a standard double-poly double-metal CMOS process has been used, having a nominal threshold voltage of around 0.7 V.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"76 1","pages":"818-821 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86181067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301668
E. N. Aghdam, P. Bénabès
A multibit delta-sigma modulator (DSM) is an attractive way of realizing a high-accuracy, high-speed, and low power data converter. However, the overall resolution of delta-sigma modulators is limited by the internal digital-to-analog converter (DAC) nonlinearity that is normally caused by mismatching errors while realizing. Recently, some dynamic element matching (DEM) methods were proposed for reducing mismatch errors by spectral shaping of its naturally white spectrum, but almost all higher order DEM have serious problems of instability and hardware complexity. This paper presents a new more stable algorithm mixed of third and second order mismatch noise shaping. Simulation results show the considerably improving of inband noise shaping, stability and hardware complexity for a third order 17-level bandpass DSM. The proposed technique can also be used in lowpass DSM and extended number of quantization DAC level.
{"title":"A new mixed stable DEM algorithm for bandpass multibit delta sigma ADC","authors":"E. N. Aghdam, P. Bénabès","doi":"10.1109/ICECS.2003.1301668","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301668","url":null,"abstract":"A multibit delta-sigma modulator (DSM) is an attractive way of realizing a high-accuracy, high-speed, and low power data converter. However, the overall resolution of delta-sigma modulators is limited by the internal digital-to-analog converter (DAC) nonlinearity that is normally caused by mismatching errors while realizing. Recently, some dynamic element matching (DEM) methods were proposed for reducing mismatch errors by spectral shaping of its naturally white spectrum, but almost all higher order DEM have serious problems of instability and hardware complexity. This paper presents a new more stable algorithm mixed of third and second order mismatch noise shaping. Simulation results show the considerably improving of inband noise shaping, stability and hardware complexity for a third order 17-level bandpass DSM. The proposed technique can also be used in lowpass DSM and extended number of quantization DAC level.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"163 1","pages":"962-965 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86465597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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