Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302012
O. Nibouche, M. Nibouche, A. Bouridane
In this paper, new structures that implement RSA cryptographic algorithm are presented. These structures are built using a modified Montgomery modular multiplier, where the operations of multiplication and modular reductions are carried out in parallel rather than interleaved as in the traditional Montgomery multiplier. The global broadcast data lines are avoided by interleaving two operations into the same structure, thus making the implementation systolic. The results of implementation in FPGA have shown that the proposed RSA structures outperformed those structures built around a traditional Montgomery multiplier in terms of speed. In terms of area usage, an area-efficient architecture is shown in this paper that has the merit of having a high speed and a reduced area usage when compared with other architectures.
{"title":"High speed FPGA implementation of RSA encryption algorithm","authors":"O. Nibouche, M. Nibouche, A. Bouridane","doi":"10.1109/ICECS.2003.1302012","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302012","url":null,"abstract":"In this paper, new structures that implement RSA cryptographic algorithm are presented. These structures are built using a modified Montgomery modular multiplier, where the operations of multiplication and modular reductions are carried out in parallel rather than interleaved as in the traditional Montgomery multiplier. The global broadcast data lines are avoided by interleaving two operations into the same structure, thus making the implementation systolic. The results of implementation in FPGA have shown that the proposed RSA structures outperformed those structures built around a traditional Montgomery multiplier in terms of speed. In terms of area usage, an area-efficient architecture is shown in this paper that has the merit of having a high speed and a reduced area usage when compared with other architectures.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"74 1","pages":"204-207 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89003042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301968
P. M. Espiñeira, Heriberto Hernández, M. Domínguez, F. Poza, F. Machado, F. Vázquez
In this paper it is presented the state-of-the-art in fieldbus technology, according with the authors' particular experience, giving diverse points of view about the necessary skills for using development tools and involved electronic devices, currently present in the training market. Given its growing impact all over automotive industry, an introduction about the CAN fieldbus is presented, along with the software and hardware tools that configure training environments for this protocol. Following the two different CAN nodes developed currently by the authors, using the aforementioned tools, are presented. Finally, future developments with great potential in the education of electronic engineers, and fieldbus training applied to automotive industry and others, are also mentioned.
{"title":"Development tools for industrial networks design","authors":"P. M. Espiñeira, Heriberto Hernández, M. Domínguez, F. Poza, F. Machado, F. Vázquez","doi":"10.1109/ICECS.2003.1301968","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301968","url":null,"abstract":"In this paper it is presented the state-of-the-art in fieldbus technology, according with the authors' particular experience, giving diverse points of view about the necessary skills for using development tools and involved electronic devices, currently present in the training market. Given its growing impact all over automotive industry, an introduction about the CAN fieldbus is presented, along with the software and hardware tools that configure training environments for this protocol. Following the two different CAN nodes developed currently by the authors, using the aforementioned tools, are presented. Finally, future developments with great potential in the education of electronic engineers, and fieldbus training applied to automotive industry and others, are also mentioned.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"1 1","pages":"28-31 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90345565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301684
U. Nordqvist, Dake Liu
In the emerging research area of protocol processors (PP) there exist many hardware platform proposals. One example of such a platform solution has been proposed by the author in a series of papers, mainly focusing on datapath organization and optimization. The proposed platform is unique since the fast path process incoming packets before storage in the input buffer. This paper proposes that a FIFO buffer should be added to the input buffer to lower the power; consumption. The optimization process and the optimal input buffer architecture are dependent on a large number of parameters, e.g. network type and traffic, host system and physical implementation process. Simulating energy consumption characteristics, a number of architectural conclusions have been made. Especially an input packet buffer configuration is proposed which can he used in a wide variety of network applications and host systems.
{"title":"Power optimized packet buffering in a protocol processor","authors":"U. Nordqvist, Dake Liu","doi":"10.1109/ICECS.2003.1301684","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301684","url":null,"abstract":"In the emerging research area of protocol processors (PP) there exist many hardware platform proposals. One example of such a platform solution has been proposed by the author in a series of papers, mainly focusing on datapath organization and optimization. The proposed platform is unique since the fast path process incoming packets before storage in the input buffer. This paper proposes that a FIFO buffer should be added to the input buffer to lower the power; consumption. The optimization process and the optimal input buffer architecture are dependent on a large number of parameters, e.g. network type and traffic, host system and physical implementation process. Simulating energy consumption characteristics, a number of architectural conclusions have been made. Especially an input packet buffer configuration is proposed which can he used in a wide variety of network applications and host systems.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"168 1","pages":"1026-1029 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80559629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301726
H. Achi, A. Hellany, Ali Elachi
Switched Virtual Circuits (SVC) have been a known functionality of ATM networks for years. The connection oriented and low latency nature of ATM makes it natural for handling streaming protocols such as video and multimedia. One of the advantages of SVC implementation is to provide bandwidth on demand, and reduce network complexity and costs. This paper explores the implementation of Video broadcasting services using SVC over ATM networks. A Network design based on performance tests has been proposed and Service Level Agreement is recommended.
{"title":"Video broadcasting using switched virtual circuits over ATM network","authors":"H. Achi, A. Hellany, Ali Elachi","doi":"10.1109/ICECS.2003.1301726","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301726","url":null,"abstract":"Switched Virtual Circuits (SVC) have been a known functionality of ATM networks for years. The connection oriented and low latency nature of ATM makes it natural for handling streaming protocols such as video and multimedia. One of the advantages of SVC implementation is to provide bandwidth on demand, and reduce network complexity and costs. This paper explores the implementation of Video broadcasting services using SVC over ATM networks. A Network design based on performance tests has been proposed and Service Level Agreement is recommended.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"52 1","pages":"1192-1195 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83797459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301923
M. Elgamel, M. Bayoumi
With high clock frequencies, faster transistor rise/fall time, long signal wires, the use of wider wires and Cu material interconnects, the decreased spacing between adjacent wires, and the increased aspect ratio, the crosstalk noise is becoming an important design metric in digital circuits. For a risk-free layout solution of a chip, capacitive and inductive noises should be considered at various routing process stages. A formulation and efficient solution for the min-area spacing problem to satisfy maximum reliability in multiple coupled nets is provided. The noise model used can handle different wire widths, different spacing among wires, and different wire lengths. Experimental results show that the proposed framework redistributes the spacing among neighboring wires to achieve maximum reliability through the minimization of the maximum crosstalk noise in nets.
{"title":"An efficient minimum area spacing algorithm for noise reduction","authors":"M. Elgamel, M. Bayoumi","doi":"10.1109/ICECS.2003.1301923","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301923","url":null,"abstract":"With high clock frequencies, faster transistor rise/fall time, long signal wires, the use of wider wires and Cu material interconnects, the decreased spacing between adjacent wires, and the increased aspect ratio, the crosstalk noise is becoming an important design metric in digital circuits. For a risk-free layout solution of a chip, capacitive and inductive noises should be considered at various routing process stages. A formulation and efficient solution for the min-area spacing problem to satisfy maximum reliability in multiple coupled nets is provided. The noise model used can handle different wire widths, different spacing among wires, and different wire lengths. Experimental results show that the proposed framework redistributes the spacing among neighboring wires to achieve maximum reliability through the minimization of the maximum crosstalk noise in nets.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"27 1","pages":"862-865 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79682121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302040
Hung-Ming Chen, Po-Hung Chen, Tai-Jee Pan, F. Lai
For the design of portable systems, power consumption is as important a design criterion as performance. Low power design starts at the system level and a top down approach will yield the greatest results. Previous researches only address on partial stages of platform-based power management. Hence, in this paper, we consider the low power design on the whole system to explore the methodology and implementation from the circuit design stage including selection of key components, analysis of hardware architecture and the platform design to dynamic power management on battery management techniques, operating systems and software design for various Hardware/Software co-design issues. We will take the tablet appliances platform as an example to illustrate how to design the power management system of the handheld device of medium to large sizes, and how to implement the advanced software power management mechanism on embedded OS like Microsoft Windows CE.NET.
对于便携式系统的设计，功耗与性能一样是重要的设计标准。低功耗设计从系统级开始，自上而下的方法将产生最大的结果。以往的研究只涉及基于平台的电源管理的部分阶段。因此，在本文中，我们考虑整个系统的低功耗设计，从电路设计阶段(包括关键组件的选择，硬件架构分析和平台设计)到电池管理技术的动态电源管理，操作系统和软件设计等各个硬件/软件协同设计问题探索方法和实现。我们将以平板电器平台为例，说明如何设计大中型手持设备的电源管理系统，以及如何在Microsoft Windows CE.NET等嵌入式操作系统上实现先进的软件电源管理机制。
{"title":"Designing platform-based system power management on a smart tablet appliance","authors":"Hung-Ming Chen, Po-Hung Chen, Tai-Jee Pan, F. Lai","doi":"10.1109/ICECS.2003.1302040","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302040","url":null,"abstract":"For the design of portable systems, power consumption is as important a design criterion as performance. Low power design starts at the system level and a top down approach will yield the greatest results. Previous researches only address on partial stages of platform-based power management. Hence, in this paper, we consider the low power design on the whole system to explore the methodology and implementation from the circuit design stage including selection of key components, analysis of hardware architecture and the platform design to dynamic power management on battery management techniques, operating systems and software design for various Hardware/Software co-design issues. We will take the tablet appliances platform as an example to illustrate how to design the power management system of the handheld device of medium to large sizes, and how to implement the advanced software power management mechanism on embedded OS like Microsoft Windows CE.NET.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"11 1","pages":"316-319 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81029313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301835
G. Papadimitriou, M. Obaidat, A. Pomportsis, H. S. Laskaridis
Shared-medium ATM switches are favored by the industry among other families of ATM switches. In this paper, four variations of a new distributed scheme are proposed for the arbitration of a shared bus of an ATM switch. The proposed bus arbitration schemes are based on learning automata. Taking advantage of the bursty nature of ATM traffic, the new arbitration scheme shows a superb performance compared to the time division multiple access, TDMA, scheme.
{"title":"Adaptive distributed bus arbitration schemes for shared-medium ATM switches","authors":"G. Papadimitriou, M. Obaidat, A. Pomportsis, H. S. Laskaridis","doi":"10.1109/ICECS.2003.1301835","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301835","url":null,"abstract":"Shared-medium ATM switches are favored by the industry among other families of ATM switches. In this paper, four variations of a new distributed scheme are proposed for the arbitration of a shared bus of an ATM switch. The proposed bus arbitration schemes are based on learning automata. Taking advantage of the bursty nature of ATM traffic, the new arbitration scheme shows a superb performance compared to the time division multiple access, TDMA, scheme.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"497 1","pages":"515-518 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88593112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301745
A. Glass, Mark Amott, Richard W. Harris
A packet/cell reservation protocol is proposed for operation in a GPRS environment. The operation of the protocol exploits the advantages of contending random access protocols for reservation purpose while accommodating a hybrid form of GSM and ATM systems to enable the provision of services to mobile users. The protocol provides reservation priority for voice and inter-active real-time services in a multichannel environment. The protocol also uses a voice activity detector to eliminate unused reserved time slots in any frame payload and then allocate them to other users that have a lower priority. A simulation model has been established to mimic the operation of the protocol for voice and data traffic. The results show better overall channel utilisation together with lower overall time delay for data messages.
{"title":"Packet reservation protocol for personal mobile communications","authors":"A. Glass, Mark Amott, Richard W. Harris","doi":"10.1109/ICECS.2003.1301745","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301745","url":null,"abstract":"A packet/cell reservation protocol is proposed for operation in a GPRS environment. The operation of the protocol exploits the advantages of contending random access protocols for reservation purpose while accommodating a hybrid form of GSM and ATM systems to enable the provision of services to mobile users. The protocol provides reservation priority for voice and inter-active real-time services in a multichannel environment. The protocol also uses a voice activity detector to eliminate unused reserved time slots in any frame payload and then allocate them to other users that have a lower priority. A simulation model has been established to mimic the operation of the protocol for voice and data traffic. The results show better overall channel utilisation together with lower overall time delay for data messages.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"1 1","pages":"1268-1271 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90764640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302056
N. Al-Musabi, Z. Al-Hamouz, H. Al-Duwaish, S. Al-Baiyat
In this paper, selection of the variable structure controller feedback gains by Particle Swarm Optimization (PSO) technique is presented contrary to the trial and error selection of the variable structure feedback gains reported in literature. The proposed design has been applied to the load frequency problem of a single area power system. The system performance against a step load variations has been simulated and compared to some previous methods. Simulation results show that not only dynamic system performance has been improved, but also the control effort is reduced. The results show the reliability of the proposed technique.
{"title":"Variable structure load frequency controller using particle swarm optimization technique","authors":"N. Al-Musabi, Z. Al-Hamouz, H. Al-Duwaish, S. Al-Baiyat","doi":"10.1109/ICECS.2003.1302056","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302056","url":null,"abstract":"In this paper, selection of the variable structure controller feedback gains by Particle Swarm Optimization (PSO) technique is presented contrary to the trial and error selection of the variable structure feedback gains reported in literature. The proposed design has been applied to the load frequency problem of a single area power system. The system performance against a step load variations has been simulated and compared to some previous methods. Simulation results show that not only dynamic system performance has been improved, but also the control effort is reduced. The results show the reliability of the proposed technique.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"62 1","pages":"380-383 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90453207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301706
K. Górecki, J. Zarebski, K. Posobkiewicz
In this paper the problem of modelling selfheating influence on the characteristics of monolithic switch-mode power supplies is considered. The LT1073 integrated circuit (IC) has been chosen for detailed investigations. Its new ElectroThermal Macromodel (ETM) joining the Electrical Model (EM) along with the thermally dependent parameters and the Lumped Thermal Model (LTM) generating the junction (inner) temperature of LT1073 is proposed. The correctness and usefulness of the new model has been revealed by means of comparison of measurements and simulations of BOOST converter including LT1073 device.
{"title":"The electrothermal macromodel of the monolithic voltage regulator LT1073 for SPICE","authors":"K. Górecki, J. Zarebski, K. Posobkiewicz","doi":"10.1109/ICECS.2003.1301706","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301706","url":null,"abstract":"In this paper the problem of modelling selfheating influence on the characteristics of monolithic switch-mode power supplies is considered. The LT1073 integrated circuit (IC) has been chosen for detailed investigations. Its new ElectroThermal Macromodel (ETM) joining the Electrical Model (EM) along with the thermally dependent parameters and the Lumped Thermal Model (LTM) generating the junction (inner) temperature of LT1073 is proposed. The correctness and usefulness of the new model has been revealed by means of comparison of measurements and simulations of BOOST converter including LT1073 device.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"22 1","pages":"1113-1116 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90527855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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