Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302027
A. Harb, M. Sawan
In this paper, we describe a low-voltage CMOS switched-capacitor rectification and bin-integration (RBI) circuit dedicated to sensor electronic interfaces. The applications of these interfaces are among others, biomedical and more particularly the implantable devices. RBI is the most common signal processing function applied to the nerve signals. Since the frequency of these signals is below 10 kHz, a switched-capacitor architecture has been used. The circuit comprises an always-valid sample and hold circuit followed by a full wave rectifier. The bin-integration is then performed with three resettable integration stages. The third stage is reset in such a way to use the maximum range of the ADC. The resulting RBI signal is then converted to digital and transferred to the implant central processor where information about bladder could be extracted. The circuit has been realized in CMOS 0.35 /spl mu/m, 3.3 V technology. The design, simulation and measurement results of the proposed interface are presented. At 1.3 V supply, the measured circuit obtains an RBI error of less than -45 dB for a sinewave input of 7.2 kHz that is the main component of the nerve signal and a dynamic range of /spl plusmn/1.1 V while dissipating 578 /spl mu/W and occupying a chip area of 5.83 mm/sup 2/.
{"title":"A SC rectification and bin-integration circuit for nerve signal processing: experimental results","authors":"A. Harb, M. Sawan","doi":"10.1109/ICECS.2003.1302027","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302027","url":null,"abstract":"In this paper, we describe a low-voltage CMOS switched-capacitor rectification and bin-integration (RBI) circuit dedicated to sensor electronic interfaces. The applications of these interfaces are among others, biomedical and more particularly the implantable devices. RBI is the most common signal processing function applied to the nerve signals. Since the frequency of these signals is below 10 kHz, a switched-capacitor architecture has been used. The circuit comprises an always-valid sample and hold circuit followed by a full wave rectifier. The bin-integration is then performed with three resettable integration stages. The third stage is reset in such a way to use the maximum range of the ADC. The resulting RBI signal is then converted to digital and transferred to the implant central processor where information about bladder could be extracted. The circuit has been realized in CMOS 0.35 /spl mu/m, 3.3 V technology. The design, simulation and measurement results of the proposed interface are presented. At 1.3 V supply, the measured circuit obtains an RBI error of less than -45 dB for a sinewave input of 7.2 kHz that is the main component of the nerve signal and a dynamic range of /spl plusmn/1.1 V while dissipating 578 /spl mu/W and occupying a chip area of 5.83 mm/sup 2/.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"2 1","pages":"264-267 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81080925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301727
A. Bouridane, F. Kurugollu, Russell Beggs, S. Boussakta
Digital image watermarking has become a very active research area. One key requirement in designing a watermarking system is that there should be no perceptible difference between the watermarked and original image, and the watermark should be difficult to remove or alter without damaging the host image. However, these two somewhat different requirements are usually closely related. This paper is concerned with an investigation of different methods to increase imperceptibility and robustness of colour watermarks embedded in colour host images using the Complex Wavelet Transform (CWT). The Complex Wavelet Transform was chosen because experimentation results from have shown the CWT to be more robust than other transforms under compression, additive noise, median and mean filtering attacks. Fusion based watermarking has been chosen since it provides a visual authentication of the watermark.
{"title":"Colour image watermarking in the complex wavelet domain","authors":"A. Bouridane, F. Kurugollu, Russell Beggs, S. Boussakta","doi":"10.1109/ICECS.2003.1301727","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301727","url":null,"abstract":"Digital image watermarking has become a very active research area. One key requirement in designing a watermarking system is that there should be no perceptible difference between the watermarked and original image, and the watermark should be difficult to remove or alter without damaging the host image. However, these two somewhat different requirements are usually closely related. This paper is concerned with an investigation of different methods to increase imperceptibility and robustness of colour watermarks embedded in colour host images using the Complex Wavelet Transform (CWT). The Complex Wavelet Transform was chosen because experimentation results from have shown the CWT to be more robust than other transforms under compression, additive noise, median and mean filtering attacks. Fusion based watermarking has been chosen since it provides a visual authentication of the watermark.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"28 1","pages":"1196-1199 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81121519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301872
R. Amirifar, N. Sadati
This paper develops a stability and performance preserving controller order reduction method for linear time-invariant continuous-time single-input, single-output systems. In this method, the error between the complementary sensitivity functions of the nominal closed-loop system and closed-loop system using the reduced-order controller is converted to a frequency-weighted error between the Youla parameters of the full-order and reduced-order controllers and then the H/sub /spl infin// norm of this error, subject to a set of linear matrix inequality constraints, is minimized. The main ideas of order reduction and stability preservation are contained in the constraints of the optimization problem. However, since this minimization problem is nonconvex, the Youla parameter of the reduced-order controller is obtained by solving a suboptimal linear matrix inequality problem, that is convex and readily solved using existing semi-definite programming solvers. It is shown that the resulting reduced-order controller preserves the stability and performance of the nominal closed-loop system in disturbance rejection and input tracking.
{"title":"Stability and performance preserving controller order reduction via Youla parameterization and LMIS","authors":"R. Amirifar, N. Sadati","doi":"10.1109/ICECS.2003.1301872","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301872","url":null,"abstract":"This paper develops a stability and performance preserving controller order reduction method for linear time-invariant continuous-time single-input, single-output systems. In this method, the error between the complementary sensitivity functions of the nominal closed-loop system and closed-loop system using the reduced-order controller is converted to a frequency-weighted error between the Youla parameters of the full-order and reduced-order controllers and then the H/sub /spl infin// norm of this error, subject to a set of linear matrix inequality constraints, is minimized. The main ideas of order reduction and stability preservation are contained in the constraints of the optimization problem. However, since this minimization problem is nonconvex, the Youla parameter of the reduced-order controller is obtained by solving a suboptimal linear matrix inequality problem, that is convex and readily solved using existing semi-definite programming solvers. It is shown that the resulting reduced-order controller preserves the stability and performance of the nominal closed-loop system in disturbance rejection and input tracking.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"16 1","pages":"663-666 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83538486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301914
Yingyi Yan, T. Szymanski
The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 /spl mu/m CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.
{"title":"Low power high speed I/O interfaces in 0.18 /spl mu/m CMOS","authors":"Yingyi Yan, T. Szymanski","doi":"10.1109/ICECS.2003.1301914","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301914","url":null,"abstract":"The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 /spl mu/m CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"25 1","pages":"826-829 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88262213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301904
S. Saeedi, S. Mehrmanesh, H. A. Aslanzadeh, S. M. Atarodi
A 14-bit 1.5 V CMOS current steering digital to analog converter (DAC) with a new calibration technique is presented. This technique is suitable for low voltage applications and does not require digital computation and correction circuits and additional calibration DAC. The circuit has been designed and simulated in a standard 0.18 /spl mu/m CMOS technology. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are better than 0.35 LSB and 0.15 LSB, respectively. The power consumption of analog circuits is 33 mW, whereas the digital part consumes 48 mW.
介绍了一种采用新型校准技术的14位1.5 V CMOS电流转向数模转换器(DAC)。该技术适用于低电压应用，不需要数字计算和校正电路以及额外的校准DAC。电路在标准的0.18 /spl mu/m CMOS工艺下进行了设计和仿真。所提出的14位规格DAC的积分和微分非线性分别优于0.35 LSB和0.15 LSB。模拟电路的功耗为33兆瓦，而数字部分的功耗为48兆瓦。
{"title":"A 1.5-V 14-bit CMOS DAC with a new self-calibration technique for wireless communication systems","authors":"S. Saeedi, S. Mehrmanesh, H. A. Aslanzadeh, S. M. Atarodi","doi":"10.1109/ICECS.2003.1301904","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301904","url":null,"abstract":"A 14-bit 1.5 V CMOS current steering digital to analog converter (DAC) with a new calibration technique is presented. This technique is suitable for low voltage applications and does not require digital computation and correction circuits and additional calibration DAC. The circuit has been designed and simulated in a standard 0.18 /spl mu/m CMOS technology. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are better than 0.35 LSB and 0.15 LSB, respectively. The power consumption of analog circuits is 33 mW, whereas the digital part consumes 48 mW.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"1 1","pages":"786-789 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77306226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302037
F. Ghanipour, A. Nabavi
In this paper we investigate power dissipation for the Viterbi algorithm. We modified the Viterbi algorithm in a power-aware way and employed several low-power techniques to reduce its power dissipation. The first modification is re-arranging of arithmetic operations to reduce the number and complexity of computational components. Another simplification is made in the survivor memory unit by storing only one bit to identify the previous state in the survivor path, and by assigning each register to the decision vector of each clock cycle. This approach eliminates unnecessary shift operations and enables us to apply a clock-gating technique to disable all of the registers but one. The final modification stems from the property of converging all of the trace-back paths at a same state regardless of their initial state. Thus, there is no need to store a global winner path. The schemes employed in our low-power design are precomputation, clock-gating, toggle filtering, and using double edge-triggered flip-flops. The power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of an original Viterbi decoder design by 88%.
{"title":"Design of a low-power Viterbi decoder for wireless communications","authors":"F. Ghanipour, A. Nabavi","doi":"10.1109/ICECS.2003.1302037","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302037","url":null,"abstract":"In this paper we investigate power dissipation for the Viterbi algorithm. We modified the Viterbi algorithm in a power-aware way and employed several low-power techniques to reduce its power dissipation. The first modification is re-arranging of arithmetic operations to reduce the number and complexity of computational components. Another simplification is made in the survivor memory unit by storing only one bit to identify the previous state in the survivor path, and by assigning each register to the decision vector of each clock cycle. This approach eliminates unnecessary shift operations and enables us to apply a clock-gating technique to disable all of the registers but one. The final modification stems from the property of converging all of the trace-back paths at a same state regardless of their initial state. Thus, there is no need to store a global winner path. The schemes employed in our low-power design are precomputation, clock-gating, toggle filtering, and using double edge-triggered flip-flops. The power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of an original Viterbi decoder design by 88%.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"194 1","pages":"304-307 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77575234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302042
A. Orozco-Lugo, D. McLernon, M. Lara
In this paper, a new method to perform channel estimation is presented. It is shown that accurate estimation can be obtained when a training sequence is actually arithmetically added to the information data as opposed to being placed in a separate empty time slot - hence the words 'hidden' and 'almost blind'. A closed form solution for the channel estimation variance is derived. A procedure is given to obtain training sequences that result in channel estimation independence of both the channel characteristics and modulation format. The problems of blind synchronization and dc offset are solved. Finally, from the simulations performed, the new algorithm is very competitive with those using traditional training, and outperforms all that are totally blind.
{"title":"Almost blind channel estimation using hidden training","authors":"A. Orozco-Lugo, D. McLernon, M. Lara","doi":"10.1109/ICECS.2003.1302042","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302042","url":null,"abstract":"In this paper, a new method to perform channel estimation is presented. It is shown that accurate estimation can be obtained when a training sequence is actually arithmetically added to the information data as opposed to being placed in a separate empty time slot - hence the words 'hidden' and 'almost blind'. A closed form solution for the channel estimation variance is derived. A procedure is given to obtain training sequences that result in channel estimation independence of both the channel characteristics and modulation format. The problems of blind synchronization and dc offset are solved. Finally, from the simulations performed, the new algorithm is very competitive with those using traditional training, and outperforms all that are totally blind.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"30 1","pages":"324-327 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87201989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302055
Y. Abdel-Magid, M. Abido
This paper demonstrates the use of particle swarm optimization for optimizing the parameters of automatic generation control systems (AGC). An integral controller and a proportional-plus-integral controller are considered. A two-area reheat thermal system is considered to exemplify the optimum parameter search. The optimal AGC parameters search is formulated as an optimization problem with a standard infinite time quadratic objective function. A time domain simulation of the system is then used in conjunction with the particle swarm optimizer to determine the controller gains. The integral square of the error and the integral of time-multiplied absolute value of the error performances indices are considered. The results reported in this paper demonstrate the effectiveness of the particle swarm optimizer in the tuning of the AGC parameters. The enhancement in the dynamic response of the power system is verified through simulation results.
{"title":"AGC tuning of interconnected reheat thermal systems with particle swarm optimization","authors":"Y. Abdel-Magid, M. Abido","doi":"10.1109/ICECS.2003.1302055","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302055","url":null,"abstract":"This paper demonstrates the use of particle swarm optimization for optimizing the parameters of automatic generation control systems (AGC). An integral controller and a proportional-plus-integral controller are considered. A two-area reheat thermal system is considered to exemplify the optimum parameter search. The optimal AGC parameters search is formulated as an optimization problem with a standard infinite time quadratic objective function. A time domain simulation of the system is then used in conjunction with the particle swarm optimizer to determine the controller gains. The integral square of the error and the integral of time-multiplied absolute value of the error performances indices are considered. The results reported in this paper demonstrate the effectiveness of the particle swarm optimizer in the tuning of the AGC parameters. The enhancement in the dynamic response of the power system is verified through simulation results.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"64 1","pages":"376-379 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91205174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301863
M. Al-Mualla, C. N. Canagarajah, D. Bull
Warping-based motion estimation has been proposed in the literature to achieve higher video coding efficiency compared to conventional block-based motion estimation. This paper investigates the performance of warping-based methods at very low bit rates typical of mobile video communication applications. Simulation results show that despite their improvements over block-based methods, the use of warping-based methods in such applications may not be justifiable due to the huge increase in computational complexity. In fact, it is shown that similar, if not better, improvements can be obtained, at a fraction of the complexity, by simply augmenting basic block-based methods with techniques like subpel accuracy and overlapped motion compensation.
{"title":"On the performance of warping-based motion estimation","authors":"M. Al-Mualla, C. N. Canagarajah, D. Bull","doi":"10.1109/ICECS.2003.1301863","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301863","url":null,"abstract":"Warping-based motion estimation has been proposed in the literature to achieve higher video coding efficiency compared to conventional block-based motion estimation. This paper investigates the performance of warping-based methods at very low bit rates typical of mobile video communication applications. Simulation results show that despite their improvements over block-based methods, the use of warping-based methods in such applications may not be justifiable due to the huge increase in computational complexity. In fact, it is shown that similar, if not better, improvements can be obtained, at a fraction of the complexity, by simply augmenting basic block-based methods with techniques like subpel accuracy and overlapped motion compensation.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"31 1","pages":"627-630 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73100353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301841
M. Yavari, H. Zare-Hoseini, M. Farazian, O. Shoaei
This paper presents a new compensation method for fully differential two-stage CMOS operational transconductance amplifiers (OTAs). It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for minimum settling time of the proposed compensation technique for a two-stage class A/AB OTA is described. To demonstrate the usefulness of it, three design examples are considered.
{"title":"A new compensation technique for two-stage CMOS operational transconductance amplifiers","authors":"M. Yavari, H. Zare-Hoseini, M. Farazian, O. Shoaei","doi":"10.1109/ICECS.2003.1301841","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301841","url":null,"abstract":"This paper presents a new compensation method for fully differential two-stage CMOS operational transconductance amplifiers (OTAs). It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for minimum settling time of the proposed compensation technique for a two-stage class A/AB OTA is described. To demonstrate the usefulness of it, three design examples are considered.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"9 1","pages":"539-542 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73911907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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