Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302057
Mahdi Jalifi-Khamajoo
The design of new optimal nonlinear voltage regulator for power systems is considered. In the proposed approach, the Hamilton-Jacobi-Belman (HJB), a partial differential equation, is solved using Taylor series expansion of its nonlinear terms. The performance of the proposed controller in a single-machine infinite-bus power system is simulated and the advantages of the nonlinear feedback controllers are investigated. The proposed controller action is simulated in different operation points. Simulation results show that the resulting nonlinear controller has greater domain of validity than that of linearized counterpart.
{"title":"Design of new optimal power system voltage regulators with greater domain of validity","authors":"Mahdi Jalifi-Khamajoo","doi":"10.1109/ICECS.2003.1302057","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302057","url":null,"abstract":"The design of new optimal nonlinear voltage regulator for power systems is considered. In the proposed approach, the Hamilton-Jacobi-Belman (HJB), a partial differential equation, is solved using Taylor series expansion of its nonlinear terms. The performance of the proposed controller in a single-machine infinite-bus power system is simulated and the advantages of the nonlinear feedback controllers are investigated. The proposed controller action is simulated in different operation points. Simulation results show that the resulting nonlinear controller has greater domain of validity than that of linearized counterpart.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"425 1","pages":"384-387 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76663060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301737
V. Carchiolo, A. Longheu, M. Malgeri, G. Mangioni
The E-learning represents the new frontier of education, significantly improving the teaming process. In this paper we propose an e-learning model, providing both teachers and students with an open and modular learning environment. We then focus on courses personalization, both in terms of contents and teaching materials, according to each student's needs and capabilities, also taking teacher guidelines into account.
{"title":"Automatic generation of learning paths","authors":"V. Carchiolo, A. Longheu, M. Malgeri, G. Mangioni","doi":"10.1109/ICECS.2003.1301737","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301737","url":null,"abstract":"The E-learning represents the new frontier of education, significantly improving the teaming process. In this paper we propose an e-learning model, providing both teachers and students with an open and modular learning environment. We then focus on courses personalization, both in terms of contents and teaching materials, according to each student's needs and capabilities, also taking teacher guidelines into account.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"132 1","pages":"1236-1239 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76741200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301981
Jan Schmidt, M. Novotný
A design of a scalable arithmetic unit for operations over elements of GF(2/sup m/) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in one arithmetic unit. We discuss optimum design of the shifter with respect to inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA. We present implementation data for various digit widths which exhibit a time minimum for digit width D=15.
{"title":"Normal basis multiplication and inversion unit for elliptic curve cryptography","authors":"Jan Schmidt, M. Novotný","doi":"10.1109/ICECS.2003.1301981","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301981","url":null,"abstract":"A design of a scalable arithmetic unit for operations over elements of GF(2/sup m/) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in one arithmetic unit. We discuss optimum design of the shifter with respect to inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA. We present implementation data for various digit widths which exhibit a time minimum for digit width D=15.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"27 1","pages":"80-83 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75013813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301675
N. Sklavos, G. Dimitroulakos, O. Koufopavlou
Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. The research community efforts are also centered to the efficient implementation of them, in both software platforms and hardware devices. This work is related to hash functions FPGA implementation. Two different hash functions are studied: RIPEMD-160 and SHA-1. A high speed architecture is proposed for the implementation of both of them in the same hardware module. The proposed system reaches throughput values equal to 1,4 for SHA-1 and 1,6 for RIPEMND-160. The proposed system is compared with other related works in both software and hardware.
{"title":"An ultra high speed architecture for VLSI implementation of hash functions","authors":"N. Sklavos, G. Dimitroulakos, O. Koufopavlou","doi":"10.1109/ICECS.2003.1301675","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301675","url":null,"abstract":"Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. The research community efforts are also centered to the efficient implementation of them, in both software platforms and hardware devices. This work is related to hash functions FPGA implementation. Two different hash functions are studied: RIPEMD-160 and SHA-1. A high speed architecture is proposed for the implementation of both of them in the same hardware module. The proposed system reaches throughput values equal to 1,4 for SHA-1 and 1,6 for RIPEMND-160. The proposed system is compared with other related works in both software and hardware.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"42 1","pages":"990-993 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73241296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301827
I. O’Connor, F. Mieyeville, F. Tissafi-Drissi, G. Tosik, F. Gaffiot
This paper presents a fast and robust design method for systematically maximising the frequency response of basic CMOS transimpedance amplifiers, a class of circuit of fundamental interest to architects of MOEMS/NOEMS. This method is based on a frequential analysis of the structure and a mapping of the component values to coefficients in a filter approximation function of Butterworth type. We use the method to explore the design space and examine how parametric, structural and architectural trade-offs can alleviate stringent design constraints on the internal amplifier.
{"title":"Predictive design space exploration of maximum bandwidth CMOS photoreceiver preamplifiers","authors":"I. O’Connor, F. Mieyeville, F. Tissafi-Drissi, G. Tosik, F. Gaffiot","doi":"10.1109/ICECS.2003.1301827","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301827","url":null,"abstract":"This paper presents a fast and robust design method for systematically maximising the frequency response of basic CMOS transimpedance amplifiers, a class of circuit of fundamental interest to architects of MOEMS/NOEMS. This method is based on a frequential analysis of the structure and a mapping of the component values to coefficients in a filter approximation function of Butterworth type. We use the method to explore the design space and examine how parametric, structural and architectural trade-offs can alleviate stringent design constraints on the internal amplifier.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"19 1","pages":"483-486 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73267539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301813
M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli
In this paper, the sawtooth map in its digital implementation is investigated as a source of pseudorandom binary numbers. Effects of precision in the arithmetic blocks used to implement the map, as well as approximation strategies and value of the map slope are discussed in terms of period and statistical properties of bits generated. Optimum values of design parameters to achieve a good quality of output bit sequences are identified, and an area-efficient implementation on a programmable device is discussed. Comparison to traditional PRNGs based on Linear-Feedback Shift Registers shows that the discretized sawtooth map is a viable solution for implementing integrated PRNG circuits.
{"title":"Analysis and design of digital PRNGS based on the discretized sawtooth map","authors":"M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli","doi":"10.1109/ICECS.2003.1301813","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301813","url":null,"abstract":"In this paper, the sawtooth map in its digital implementation is investigated as a source of pseudorandom binary numbers. Effects of precision in the arithmetic blocks used to implement the map, as well as approximation strategies and value of the map slope are discussed in terms of period and statistical properties of bits generated. Optimum values of design parameters to achieve a good quality of output bit sequences are identified, and an area-efficient implementation on a programmable device is discussed. Comparison to traditional PRNGs based on Linear-Feedback Shift Registers shows that the discretized sawtooth map is a viable solution for implementing integrated PRNG circuits.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"56 1","pages":"427-430 Vol.2"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73324123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301679
M. Tahir, M. A. Roula, A. Bouridane, F. Kurugollu, A. Amira
Gray Level Co-occurrence Matrix (GLCM), one of the best known texture analysis methods, estimates image properties related to second-order statistics. These image properties commonly known as texture features can be used for image classification, image segmentation, and remote sensing applications. In this paper, we present an FPGA based co-processor to accelerate the extraction of texture features from GLCM. Handel-C, a recently developed C-like programming language for hardware design, has been used for the FPGA implementation of GLCM texture features measurement. Results show that the FPGA has better speed performances when compared to a general purpose processor for the extraction of GLCM features.
{"title":"An FPGA based co-processor for GLCM texture features measurement","authors":"M. Tahir, M. A. Roula, A. Bouridane, F. Kurugollu, A. Amira","doi":"10.1109/ICECS.2003.1301679","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301679","url":null,"abstract":"Gray Level Co-occurrence Matrix (GLCM), one of the best known texture analysis methods, estimates image properties related to second-order statistics. These image properties commonly known as texture features can be used for image classification, image segmentation, and remote sensing applications. In this paper, we present an FPGA based co-processor to accelerate the extraction of texture features from GLCM. Handel-C, a recently developed C-like programming language for hardware design, has been used for the FPGA implementation of GLCM texture features measurement. Results show that the FPGA has better speed performances when compared to a general purpose processor for the extraction of GLCM features.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"22 1","pages":"1006-1009 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73363062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301988
A. Masoudnia, H. Sarbazi-Azad, S. Boussakta
In this paper a novel technique using the Block Truncation Coding (BTC) to further improve the compression quality of a 4-tap integer wavelet filter is proposed. Experimental results reveal that noticeable improvements can be achieved using the proposed BTC-based technique.
{"title":"A BTC-based technique for improving image compression","authors":"A. Masoudnia, H. Sarbazi-Azad, S. Boussakta","doi":"10.1109/ICECS.2003.1301988","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301988","url":null,"abstract":"In this paper a novel technique using the Block Truncation Coding (BTC) to further improve the compression quality of a 4-tap integer wavelet filter is proposed. Experimental results reveal that noticeable improvements can be achieved using the proposed BTC-based technique.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"598 ","pages":"108-111 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ICECS.2003.1301988","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72435701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1301677
Abbas Ramazani, F. Monteiro, A. Dandache, B. Lepley
Modems and other network interfaces are critical devices in a network infrastructure. While software modems would be the ideal solution for flexibility and low cost, they miss the speed performance requirement. On the other hand, the usual hardware specific approach is not adapted to the fast evolution of protocols in modern multimedia network applications, in which very high data rates, flexibility, reliability and low cost designs are the target keywords. Designing a new processor architecture based on a pseudosystolic MIMD approach is a promising road to explore in order to find an effective trade-off between all these requirements. The aim of this paper is to present a methodology to design such a complex and specific device and to introduce an useful set of CAD (Computer Aided Design) tools.
{"title":"A methodology to design a multimedia processor core","authors":"Abbas Ramazani, F. Monteiro, A. Dandache, B. Lepley","doi":"10.1109/ICECS.2003.1301677","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1301677","url":null,"abstract":"Modems and other network interfaces are critical devices in a network infrastructure. While software modems would be the ideal solution for flexibility and low cost, they miss the speed performance requirement. On the other hand, the usual hardware specific approach is not adapted to the fast evolution of protocols in modern multimedia network applications, in which very high data rates, flexibility, reliability and low cost designs are the target keywords. Designing a new processor architecture based on a pseudosystolic MIMD approach is a promising road to explore in order to find an effective trade-off between all these requirements. The aim of this paper is to present a methodology to design such a complex and specific device and to introduce an useful set of CAD (Computer Aided Design) tools.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"32 1","pages":"998-1001 Vol.3"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84592438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-14DOI: 10.1109/ICECS.2003.1302046
F. Belhoul, R. Shubair, M. Al-Mualla
This paper presents a simulation tool for direction-of-arrival (DOA) estimation in adaptive signal processing arrays. The tool implements the multiple signal classification (MUSIC) DOA algorithm. A user-friendly graphical user interface (GUI) is also developed. In addition to its usefulness in the design and analysis of adaptive signal processing arrays, the tool can also be used for computer-aided learning of modem communication systems utilizing smart antennas. To demonstrate the versatility and accuracy of the developed tool, it is used to carry out a detailed performance analysis of DOA estimation using MUSIC. This includes investigating the effect of the number of mobile users and their spatial distribution, the number of array elements and their spacing, and the number of signal snapshots.
{"title":"Modelling and performance analysis of DOA estimation in adaptive signal processing arrays","authors":"F. Belhoul, R. Shubair, M. Al-Mualla","doi":"10.1109/ICECS.2003.1302046","DOIUrl":"https://doi.org/10.1109/ICECS.2003.1302046","url":null,"abstract":"This paper presents a simulation tool for direction-of-arrival (DOA) estimation in adaptive signal processing arrays. The tool implements the multiple signal classification (MUSIC) DOA algorithm. A user-friendly graphical user interface (GUI) is also developed. In addition to its usefulness in the design and analysis of adaptive signal processing arrays, the tool can also be used for computer-aided learning of modem communication systems utilizing smart antennas. To demonstrate the versatility and accuracy of the developed tool, it is used to carry out a detailed performance analysis of DOA estimation using MUSIC. This includes investigating the effect of the number of mobile users and their spatial distribution, the number of array elements and their spacing, and the number of signal snapshots.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"16 1","pages":"340-343 Vol.1"},"PeriodicalIF":0.0,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81728388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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