Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362671
F. Grunthaner, J. Maserjian
X-ray photoelectron spectroscopy (XPS) is described in its application as a probe for studying defects such as sodium in SiO2 films. A general description is given of key experimental methods in XPS. New techniques are described for applying and monitoring a fixed bias at the surface of the oxide during the XPS measurement. These methods are shown capable of detecting extremely small Na and Cu concentrations in undoped samples (< 1011 cm¿2). In deliberately Na-doped samples, five spectral peaks are distinctly observed and related to different defect states at the vacuum/SiO2 and SiO2/Si interfaces. By applying a bias-temperature stress during the XPS measurements, these peaks change in relative intensity and can be related to the motion of the Na+ ions between different states occurring at the two interfaces. An attempt is made to correlate the observations with previously reported models.
{"title":"Sodium Ions at Defect Sites at SiO2/Si Interfaces as Determined by X-Ray Photoelectron Spectroscopy","authors":"F. Grunthaner, J. Maserjian","doi":"10.1109/IRPS.1975.362671","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362671","url":null,"abstract":"X-ray photoelectron spectroscopy (XPS) is described in its application as a probe for studying defects such as sodium in SiO2 films. A general description is given of key experimental methods in XPS. New techniques are described for applying and monitoring a fixed bias at the surface of the oxide during the XPS measurement. These methods are shown capable of detecting extremely small Na and Cu concentrations in undoped samples (< 1011 cm¿2). In deliberately Na-doped samples, five spectral peaks are distinctly observed and related to different defect states at the vacuum/SiO2 and SiO2/Si interfaces. By applying a bias-temperature stress during the XPS measurements, these peaks change in relative intensity and can be related to the motion of the Na+ ions between different states occurring at the two interfaces. An attempt is made to correlate the observations with previously reported models.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121523214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362685
R. Berger, A. Gregoritsch
An n-channel FET memory array chip whose quartz passivation layer is purposely disrupted in specific-nonrandom locations is used to study the propensity of these induced defects to fail due to localized inversion of the silicon surface stemming from positive ions contained within the defect which are residual from processing. Two distinct sizes of induced defects are considered; three and seven micron diamters; 800 of the larger size and 100 of the smaller. Vertical structures range from shallow indentations to holes completely-through the passivation layer thus exposing the underlying silicon. Positive ionic contamination is introduced into the defects via an overcoat of photoresist whose positive ionic species and levels are known. Accelerated temperature and voltage life stresses are performed. Temperatures employed are 85 and 150°C, while voltage levels (and E field) across the defect are nominal and twice nominal. Data obtained from these temperature/voltage accelerated stresses is presented which shows time-to-fail is related to the ionic (mostly sodium) levels contained within the defects. Voltage acceleration was found to be a nonlinear function while temperature follows the standard Arrhenius model with an activation energy of 1.1 eV. Hole size was found to be at best a second order effect on time-to-fail. High temperature no bias bake-out at 150°C for 48 hours was performed. Percent inversion is seen to decrease by approximately an order of magnitude in all cases.
{"title":"Induced Passivation Defect Study","authors":"R. Berger, A. Gregoritsch","doi":"10.1109/IRPS.1975.362685","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362685","url":null,"abstract":"An n-channel FET memory array chip whose quartz passivation layer is purposely disrupted in specific-nonrandom locations is used to study the propensity of these induced defects to fail due to localized inversion of the silicon surface stemming from positive ions contained within the defect which are residual from processing. Two distinct sizes of induced defects are considered; three and seven micron diamters; 800 of the larger size and 100 of the smaller. Vertical structures range from shallow indentations to holes completely-through the passivation layer thus exposing the underlying silicon. Positive ionic contamination is introduced into the defects via an overcoat of photoresist whose positive ionic species and levels are known. Accelerated temperature and voltage life stresses are performed. Temperatures employed are 85 and 150°C, while voltage levels (and E field) across the defect are nominal and twice nominal. Data obtained from these temperature/voltage accelerated stresses is presented which shows time-to-fail is related to the ionic (mostly sodium) levels contained within the defects. Voltage acceleration was found to be a nonlinear function while temperature follows the standard Arrhenius model with an activation energy of 1.1 eV. Hole size was found to be at best a second order effect on time-to-fail. High temperature no bias bake-out at 150°C for 48 hours was performed. Percent inversion is seen to decrease by approximately an order of magnitude in all cases.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128993670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362686
J. J. Bart
This paper reviews the results of deposited glass layer analysis carried out during device failure analysis and characterization studies performed at the Rome Air Development Center. The Scanning Electron Microscope (SEM) was used as the principal analysis technique for this study. The variables under consideration were glass deposition method, device interconnect metallurgy, package type and device stress conditions. The effects of glass layer defects on device reliability are discussed along with qualification and screen tests aimed at eliminating batch-related problems.
{"title":"Analysis of Deposited Glass Layer Defects","authors":"J. J. Bart","doi":"10.1109/IRPS.1975.362686","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362686","url":null,"abstract":"This paper reviews the results of deposited glass layer analysis carried out during device failure analysis and characterization studies performed at the Rome Air Development Center. The Scanning Electron Microscope (SEM) was used as the principal analysis technique for this study. The variables under consideration were glass deposition method, device interconnect metallurgy, package type and device stress conditions. The effects of glass layer defects on device reliability are discussed along with qualification and screen tests aimed at eliminating batch-related problems.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362670
D. Yang, W. C. Johnson, M. Lampert
The dielectric breakdown of SiO2 films thermally grown on (100) silicon substrates was studied by the self-quenching technique, using thin aluminum field plates. The breakdown regions show distinct differences among the four possible combinations of substrate type and polarity of applied voltage. With p-type substrate and positive field-plate polarity, an anisotropy is observed which reflects the crystallo-graphic structure of the substrate. A pre-breakdown instability, which is enhanced at lowered temperatures, is ascribed to hole-electron pair production in the oxide followed by hole trapping at or near the negative electrode.
{"title":"A Study of the Dielectric Breakdown of Thermally Grown SiO2 by the Self-Quenching Technique","authors":"D. Yang, W. C. Johnson, M. Lampert","doi":"10.1109/IRPS.1975.362670","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362670","url":null,"abstract":"The dielectric breakdown of SiO2 films thermally grown on (100) silicon substrates was studied by the self-quenching technique, using thin aluminum field plates. The breakdown regions show distinct differences among the four possible combinations of substrate type and polarity of applied voltage. With p-type substrate and positive field-plate polarity, an anisotropy is observed which reflects the crystallo-graphic structure of the substrate. A pre-breakdown instability, which is enhanced at lowered temperatures, is ascribed to hole-electron pair production in the oxide followed by hole trapping at or near the negative electrode.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129530233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362684
A. Macpherson, W. Weisenberger, H. Day, A. Christou
Microwave power transistors in a radar-system may undergo ~ 1011 fast heating and cooling cycles during lifetime. Controlled temperature cycling tests have been carried out on Al, passivated Al, and gold metallization systems using both a special test pattern and commercially available transistors. Significant visible and electrical changes were observed for Al, glassed Al and a laboratory Ta-Pt-Ta-Au system, but not for a commercial gold transistor.
{"title":"Effects of Fast Temperature Cycling on Aluminum and Gold Metal Systems","authors":"A. Macpherson, W. Weisenberger, H. Day, A. Christou","doi":"10.1109/IRPS.1975.362684","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362684","url":null,"abstract":"Microwave power transistors in a radar-system may undergo ~ 1011 fast heating and cooling cycles during lifetime. Controlled temperature cycling tests have been carried out on Al, passivated Al, and gold metallization systems using both a special test pattern and commercially available transistors. Significant visible and electrical changes were observed for Al, glassed Al and a laboratory Ta-Pt-Ta-Au system, but not for a commercial gold transistor.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124794873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362707
N. W. VanVonno
Accelerated testing was utilized as a means of rapidly determining the reliability, under usage conditions, of a two-level aluminum metallization -Si02 structure with level-to-level via contacts. A specially designed test vehicle containing 0.25-mil square and 0.50-mil square via contact structures was used. Electromigration was identified as the failure mechanism by SE4 analysis. Calculation of the activation energy was in agreement with an electromigration mechanism. In using the described evaluation technique, only a small quantity of units was required to arrive quickly at valid results.
{"title":"Determination of Useful Life of Two-Layer Metallization Systems Via Accelerated Stressing","authors":"N. W. VanVonno","doi":"10.1109/IRPS.1975.362707","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362707","url":null,"abstract":"Accelerated testing was utilized as a means of rapidly determining the reliability, under usage conditions, of a two-level aluminum metallization -Si02 structure with level-to-level via contacts. A specially designed test vehicle containing 0.25-mil square and 0.50-mil square via contact structures was used. Electromigration was identified as the failure mechanism by SE4 analysis. Calculation of the activation energy was in agreement with an electromigration mechanism. In using the described evaluation technique, only a small quantity of units was required to arrive quickly at valid results.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121235796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362688
D. Blackburn
A technique is described which uses straightforward electrical measurement procedures to determine the peak junction temperature of power transistors. To determine the peak temperature, standard electrical measurement techniques are altered to account for the difference between the distributions of the calibration and measurement currents in the active area of the device. For relatively uniform temperature distributions, the electrically determined peak junction temperature is only about 6% or less below the infrared measured peak temperature whereas the standard electrically measured temperature is about 10 to 25% below the infrared measured peak temperature. For severely non-uniform temperature distributions, when only about 20% of the total active area of the device is dissipating power at steady state, the electrically determined peak temperature is within 11% of the infrared measured peak temperature while the standard electrically measured temperature is more than 40% below the infrared measured peak temperature. Device operating conditions for which the junction temperature as determined by standard electrical methods, infrared techniques, and the electrical peak temperature technique equals the manufacturer's specified maximum safe operating temperature are compared with one another and with the manufacturer's specified safe operating limits. It is suggested that the electrical peak temperature technique can be used to generate more realistic safe operating area limits and to determine the validity of specified safe operating limits of power transistors.
{"title":"An Electrical Technique for the Measurement of the Peak Junction Temperature of Power Transistors","authors":"D. Blackburn","doi":"10.1109/IRPS.1975.362688","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362688","url":null,"abstract":"A technique is described which uses straightforward electrical measurement procedures to determine the peak junction temperature of power transistors. To determine the peak temperature, standard electrical measurement techniques are altered to account for the difference between the distributions of the calibration and measurement currents in the active area of the device. For relatively uniform temperature distributions, the electrically determined peak junction temperature is only about 6% or less below the infrared measured peak temperature whereas the standard electrically measured temperature is about 10 to 25% below the infrared measured peak temperature. For severely non-uniform temperature distributions, when only about 20% of the total active area of the device is dissipating power at steady state, the electrically determined peak temperature is within 11% of the infrared measured peak temperature while the standard electrically measured temperature is more than 40% below the infrared measured peak temperature. Device operating conditions for which the junction temperature as determined by standard electrical methods, infrared techniques, and the electrical peak temperature technique equals the manufacturer's specified maximum safe operating temperature are compared with one another and with the manufacturer's specified safe operating limits. It is suggested that the electrical peak temperature technique can be used to generate more realistic safe operating area limits and to determine the validity of specified safe operating limits of power transistors.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362694
S. Bellier, R. Haythornthwaite, J. L. May, P. J. Woods
It has been demonstrated that failures of gallium arsenide field effect transistors often occur at the sites of minor manufacturing defects. SEN and optical examination can be used to reject devices with such defects. Failure may often be traced to energy pulses which cause expulsion of material from localized areas. Failures caused by positive and negative pulses have distinctive characteristics: positive pulses on the gates tend to cause failures close to the gate bonding pads, or at regions of high gate resistance; negative pulses tend to cause failures at manufacturing defects. The damage may not cause the devices to go out of electrical specification but will seriously reduce their expected life.
{"title":"Reliability of Microwave Gallium Arsenide Field Effect Transistors","authors":"S. Bellier, R. Haythornthwaite, J. L. May, P. J. Woods","doi":"10.1109/IRPS.1975.362694","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362694","url":null,"abstract":"It has been demonstrated that failures of gallium arsenide field effect transistors often occur at the sites of minor manufacturing defects. SEN and optical examination can be used to reject devices with such defects. Failure may often be traced to energy pulses which cause expulsion of material from localized areas. Failures caused by positive and negative pulses have distinctive characteristics: positive pulses on the gates tend to cause failures close to the gate bonding pads, or at regions of high gate resistance; negative pulses tend to cause failures at manufacturing defects. The damage may not cause the devices to go out of electrical specification but will seriously reduce their expected life.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132412256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362696
R. Hamaker, J. Laskowski, R. J. Segalla, J. Franco
Prior to the onset of long-term degradation, noticeable increases in the external quantum efficiency of zinc-diffused GaAs electroluminescent diodes have been observed and characterized. Such appreciation behavior may exist for several thousand hours of device operation and is dependent on both the relative strength of the stress condition as well as the initial emitted light intensity of the particular device. This anomalous behavior has been determined to be caused by increases in the intrinsic quantum efficiency within the P region of the device. Both pulsed and direct current stress conditions have been examined to characterize this behavior.
{"title":"Early Appreciation in Zinc-Diffused GaAs Electroluminescent Infrared Diodes","authors":"R. Hamaker, J. Laskowski, R. J. Segalla, J. Franco","doi":"10.1109/IRPS.1975.362696","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362696","url":null,"abstract":"Prior to the onset of long-term degradation, noticeable increases in the external quantum efficiency of zinc-diffused GaAs electroluminescent diodes have been observed and characterized. Such appreciation behavior may exist for several thousand hours of device operation and is dependent on both the relative strength of the stress condition as well as the initial emitted light intensity of the particular device. This anomalous behavior has been determined to be caused by increases in the intrinsic quantum efficiency within the P region of the device. Both pulsed and direct current stress conditions have been examined to characterize this behavior.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115452759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362692
R. Soukup, L. Collingwood
Reliability life tests of rf power transistors during pre-production evaluation of advanced design avionics distance measuring equipment (DME) have revealed two primary failure mechanisms affecting the transistors used in this 1 GHz pulse power application. The mechanisms are: 1. dissolution of silicon in aluminum, with subsequent hillock formation in the emitter metallization, and 2. aluminum grain swelling, both mechanisms resulting in base-emitter degradation. These results have been verified by SEN and electrical tests based on rf pulse power life tests on the DME equipment and from failures in field test environments. Several corrective measures have been implemented by semiconductor manufacturers as a consequence of aluminum electromigration failures in preliminary carrier wave (CW) life tests. Additional corrective measures on these devices were necessary to eliminate the failure mechanisms seen in the 1 GHz pulse power environment to which these transistors were subjected. A recent 5000 hour pulse power life test substantiates that degradation has not occurred in transistors incorporating the design corrections.
{"title":"Failure Mechanisms in Pulsed RF Power Transistors","authors":"R. Soukup, L. Collingwood","doi":"10.1109/IRPS.1975.362692","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362692","url":null,"abstract":"Reliability life tests of rf power transistors during pre-production evaluation of advanced design avionics distance measuring equipment (DME) have revealed two primary failure mechanisms affecting the transistors used in this 1 GHz pulse power application. The mechanisms are: 1. dissolution of silicon in aluminum, with subsequent hillock formation in the emitter metallization, and 2. aluminum grain swelling, both mechanisms resulting in base-emitter degradation. These results have been verified by SEN and electrical tests based on rf pulse power life tests on the DME equipment and from failures in field test environments. Several corrective measures have been implemented by semiconductor manufacturers as a consequence of aluminum electromigration failures in preliminary carrier wave (CW) life tests. Additional corrective measures on these devices were necessary to eliminate the failure mechanisms seen in the 1 GHz pulse power environment to which these transistors were subjected. A recent 5000 hour pulse power life test substantiates that degradation has not occurred in transistors incorporating the design corrections.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124966598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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