Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362676
L. Hanley, Jacob Martin
Parylene has been suggested for use and, in some cases, is used as a protective system for electronic components and assemblies, such as microcircuits. unfortunately, the amount of environmental test data for such parylene-protected components is quite limited and, to the authors' knowledge, almost no long-term test data exists. The principal objective of the test program reported in this paper was to determine whether it is at all reasonable to use parylene as a protective system for microcircuits in place of a hermetic seal in high-reliability equipment. A radiation-hardened circuit containing nichrome resistors was selected as a test specimen because of its considerable sensitivity to humidity-induced failure. The ceramic encased circuits were mounted on carrier cards, delidded, and coated with parylene C at three different facilities (Vendors A, B, and C). The cleaning cycle, the adhesion promotor, and the thickness of the parylene coating appifed differed from vendor to vendor, depending on the practices considered appropriate by the particular coating facili-ty at the time. The circuits were operated in a ring-counter configuration during humidity tests. Nonparylened units both with and without lids were also tested as controls, and other parylene-coated control units were kept in a dessicator. Units which had been coated by Vendor C had a hifgher failure rate than even the unprotected units. This is attributed to the adhesion promoter used. The failure modes exhibited by Vendor-C parts were: (1) Nichrome voiding at the nichrome/aluminum interface. (2) Nichrome voiding in the bulk of the nichrome resistors.
{"title":"A Test of Parylene as a Protective System for Microcircuitry","authors":"L. Hanley, Jacob Martin","doi":"10.1109/IRPS.1975.362676","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362676","url":null,"abstract":"Parylene has been suggested for use and, in some cases, is used as a protective system for electronic components and assemblies, such as microcircuits. unfortunately, the amount of environmental test data for such parylene-protected components is quite limited and, to the authors' knowledge, almost no long-term test data exists. The principal objective of the test program reported in this paper was to determine whether it is at all reasonable to use parylene as a protective system for microcircuits in place of a hermetic seal in high-reliability equipment. A radiation-hardened circuit containing nichrome resistors was selected as a test specimen because of its considerable sensitivity to humidity-induced failure. The ceramic encased circuits were mounted on carrier cards, delidded, and coated with parylene C at three different facilities (Vendors A, B, and C). The cleaning cycle, the adhesion promotor, and the thickness of the parylene coating appifed differed from vendor to vendor, depending on the practices considered appropriate by the particular coating facili-ty at the time. The circuits were operated in a ring-counter configuration during humidity tests. Nonparylened units both with and without lids were also tested as controls, and other parylene-coated control units were kept in a dessicator. Units which had been coated by Vendor C had a hifgher failure rate than even the unprotected units. This is attributed to the adhesion promoter used. The failure modes exhibited by Vendor-C parts were: (1) Nichrome voiding at the nichrome/aluminum interface. (2) Nichrome voiding in the bulk of the nichrome resistors.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125036693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362674
C. Libove
Formulas are presented for the maximum tensile stresses in the lid seal and the maximum lid deflections of a rectangular flat-pack under external pressure. These formulas can facilitate (a) the proper design of the package so that it will retain its hermeticity under a given screening pressure and (b) the selection of a proper pressure to use in the hermeticity screening of an already designed package. Information is also given on the approximate equivalence of external pressure and centrifuge acceleration in regard to the seal stresses and lid deflections of a rectangular flat-pack.
{"title":"Rectangular Flat-Pack Lids Under External Pressure: Formulas for Screening and Design","authors":"C. Libove","doi":"10.1109/IRPS.1975.362674","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362674","url":null,"abstract":"Formulas are presented for the maximum tensile stresses in the lid seal and the maximum lid deflections of a rectangular flat-pack under external pressure. These formulas can facilitate (a) the proper design of the package so that it will retain its hermeticity under a given screening pressure and (b) the selection of a proper pressure to use in the hermeticity screening of an already designed package. Information is also given on the approximate equivalence of external pressure and centrifuge acceleration in regard to the seal stresses and lid deflections of a rectangular flat-pack.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129987386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362701
A. Bertin, T. Terwilliger
The anticipated performance of manufactured devices is at present based on long-term use history of similar items. The hybrid microelectronic circuit is of recent vintage and its history is relatively short. To counter this short history, predictions have been cautious and in-process environmental screening and testing have been used to achieve performance. It has been proposed that the reliability performance of a hybrid circuit can be achieved, or enhanced, when no repairs are made to the device during assembly and subsequent testing. To investigate the validity of this theory, the proper combination of factors must be made available detailed knowledge of the circuit history during assembly, screening, and testing history of the performance in the system level effort and finally, but most important, the complete history of the device's use by the ultimate customer in his environment. These factors were available for a large group of circuits, of five different designs. The conclusions reached are significant in that they show that repairs can be made without affecting the hybrid circuit performance or reliability.
{"title":"Repairs to Complex Hybrid Circuits - Their Effect on Reliability","authors":"A. Bertin, T. Terwilliger","doi":"10.1109/IRPS.1975.362701","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362701","url":null,"abstract":"The anticipated performance of manufactured devices is at present based on long-term use history of similar items. The hybrid microelectronic circuit is of recent vintage and its history is relatively short. To counter this short history, predictions have been cautious and in-process environmental screening and testing have been used to achieve performance. It has been proposed that the reliability performance of a hybrid circuit can be achieved, or enhanced, when no repairs are made to the device during assembly and subsequent testing. To investigate the validity of this theory, the proper combination of factors must be made available detailed knowledge of the circuit history during assembly, screening, and testing history of the performance in the system level effort and finally, but most important, the complete history of the device's use by the ultimate customer in his environment. These factors were available for a large group of circuits, of five different designs. The conclusions reached are significant in that they show that repairs can be made without affecting the hybrid circuit performance or reliability.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134535081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362680
H. Khajezadeh, A. S. Rose
Previous studies of the basic failure mechanisms of conventional plastic-encapsulated integrated circuits have led to improvements in materials and processes which have yielded two orders of magnitude improvement in reliability. Additionally, it has been demonstrated that, where severe environmental conditions are encountered, enhanced reliability is provided by device surfaces passivated with a silicon nitride dielectric and metallized with a titanium, platinum, gold interconnecting system. Failures associated witlh gold electro-plating under severe humidity-bias conditions are avoided by the deposition of a dielectric layer over tlle metallizationi pattern. Subsequent thermal, electrical, and moisture stress testinig his confirmed earlier indications that predicted lifetimes greater than 107 hours can be anticipated for these types of initegrated circuits when they are operated at a maximuim rated temperature of 125°C. An automated duial-in-linle-package assembly system has been evaluated that provides plastic packages in which the convenitional wire bonds have been eliminated and replaced with thermocom-pression bonds of metal beams to both the device and the lead-frame bond sites. The advantages gained from this type of assembly system are discussed.
{"title":"Reliability Evaluation of Hermetic Integrated Circuit Chips in Plastic Packages","authors":"H. Khajezadeh, A. S. Rose","doi":"10.1109/IRPS.1975.362680","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362680","url":null,"abstract":"Previous studies of the basic failure mechanisms of conventional plastic-encapsulated integrated circuits have led to improvements in materials and processes which have yielded two orders of magnitude improvement in reliability. Additionally, it has been demonstrated that, where severe environmental conditions are encountered, enhanced reliability is provided by device surfaces passivated with a silicon nitride dielectric and metallized with a titanium, platinum, gold interconnecting system. Failures associated witlh gold electro-plating under severe humidity-bias conditions are avoided by the deposition of a dielectric layer over tlle metallizationi pattern. Subsequent thermal, electrical, and moisture stress testinig his confirmed earlier indications that predicted lifetimes greater than 107 hours can be anticipated for these types of initegrated circuits when they are operated at a maximuim rated temperature of 125°C. An automated duial-in-linle-package assembly system has been evaluated that provides plastic packages in which the convenitional wire bonds have been eliminated and replaced with thermocom-pression bonds of metal beams to both the device and the lead-frame bond sites. The advantages gained from this type of assembly system are discussed.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116415542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362687
A. Mohsen, T. F. Retajczyk, S. Haszko
The metal-polysilicon-doped silicon butting contact is presently widely used in MOS silicon gate integrated circuits because it occupies minimum area on the chip and does not require additional photolithography. A possible failure mechanism of this contact with self-aligned, ion-implanted sources and drains has been observed. Recent data obtained on processes used to fabricate two-phase, two-level polysilicon CCDs are presented. Results show that oxide etching under the edges of the polysilicon gate during contact window definition can lead to excessive leakage due to metal-to-substrate shorts at the metal-polysilicon-doped silicon butting contact.
{"title":"Failure Mechanism of Metal-Polysilicon-Doped Silicon Butting Contacts","authors":"A. Mohsen, T. F. Retajczyk, S. Haszko","doi":"10.1109/IRPS.1975.362687","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362687","url":null,"abstract":"The metal-polysilicon-doped silicon butting contact is presently widely used in MOS silicon gate integrated circuits because it occupies minimum area on the chip and does not require additional photolithography. A possible failure mechanism of this contact with self-aligned, ion-implanted sources and drains has been observed. Recent data obtained on processes used to fabricate two-phase, two-level polysilicon CCDs are presented. Results show that oxide etching under the edges of the polysilicon gate during contact window definition can lead to excessive leakage due to metal-to-substrate shorts at the metal-polysilicon-doped silicon butting contact.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122324366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362678
J. Jellison
Analysis of broken ultrasonic Al-Ag bonds involving SEM electron microprobe, ion microprobe, and Auger electron spectroscopy indicated that failure was due to corrosion. Subsequent environmental tests demonstrated that Al-Ag bonds are highly susceptible to corrosion, but Al-Au and Au-Al bonds are less so. No evidence of corrosion of Au-Ag bonds was found.
{"title":"Susceptibility of Microweids in Hybrid Microcincuits to Corrosion Degradation","authors":"J. Jellison","doi":"10.1109/IRPS.1975.362678","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362678","url":null,"abstract":"Analysis of broken ultrasonic Al-Ag bonds involving SEM electron microprobe, ion microprobe, and Auger electron spectroscopy indicated that failure was due to corrosion. Subsequent environmental tests demonstrated that Al-Ag bonds are highly susceptible to corrosion, but Al-Au and Au-Al bonds are less so. No evidence of corrosion of Au-Ag bonds was found.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362683
B. Agarwala
Experiments are carried out to understand the electromigration-induced failure mechanism in thin-film Au conductors. The activation energy for the atom transport and the magnitude of the current exponent In the failure equation are obtained. The role of surface coverage on the reliability of AU stripes is studied. The underlying mode of atom transport and the possible sources of flux divergences are discussed in terms of these results.
{"title":"Electromigration Failure in Au Thin-Film Conductors","authors":"B. Agarwala","doi":"10.1109/IRPS.1975.362683","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362683","url":null,"abstract":"Experiments are carried out to understand the electromigration-induced failure mechanism in thin-film Au conductors. The activation energy for the atom transport and the magnitude of the current exponent In the failure equation are obtained. The role of surface coverage on the reliability of AU stripes is studied. The underlying mode of atom transport and the possible sources of flux divergences are discussed in terms of these results.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362675
D. E. Meyer
{"title":"Miniature Moisture Sensors for In-Package Use by the Microelectronics Industry","authors":"D. E. Meyer","doi":"10.1109/IRPS.1975.362675","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362675","url":null,"abstract":"","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126566679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362690
J. Philbrick, T. Distefano
A scanned surface photovoltage (SSP) method is capable of detecting a wide variety of defects in a silicon surface. This method can be used to scan a large area of the silicon surface, which is coupled by a surface channel to a small remote electrode. The resolution obtained, about 2 ¿m, is explained theoretically in this paper for the case of a differentiated photovoltage signal and a small (0.8 ¿m diameter) light beam from an optimized optical system. SSP images of a variety of defects, both naturally occurring and induced, were obtained along with images produced by other methods for comparison.
{"title":"Scanned Surface Photovoltage Detection of Defects in Silicon Wafers","authors":"J. Philbrick, T. Distefano","doi":"10.1109/IRPS.1975.362690","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362690","url":null,"abstract":"A scanned surface photovoltage (SSP) method is capable of detecting a wide variety of defects in a silicon surface. This method can be used to scan a large area of the silicon surface, which is coupled by a surface channel to a small remote electrode. The resolution obtained, about 2 ¿m, is explained theoretically in this paper for the case of a differentiated photovoltage signal and a small (0.8 ¿m diameter) light beam from an optimized optical system. SSP images of a variety of defects, both naturally occurring and induced, were obtained along with images produced by other methods for comparison.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130483069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1975-04-01DOI: 10.1109/IRPS.1975.362693
R. N. Clarke, B. Stallard
Four types of microwave transistors were tested for D. C. electromigration under accelerated to typical use conditions. A lower activation energy was obtained along with a larger preexponential constant and smaller exponent for current density for the typical electromigration equation. Three of the transistor types were also run in an operational life test at 2.0GHz. After 5,000 hours of testing, the beginnings of a correlation between the D.C. and R.F. testing have appeared. Also oscillators have failed; while amplifiers have not. Power cycling of gold lead wires has shown no fatigue deterioration of the wires or bonds. Temperature step stress showed a semiconductor device cannot be used above its eutectic temperature. A computer model is used to calculate operating temperature at high case temperature and power loading, where actual measurements are difficult to make and intrepret.
{"title":"Reliability Study of Microwave Transistors","authors":"R. N. Clarke, B. Stallard","doi":"10.1109/IRPS.1975.362693","DOIUrl":"https://doi.org/10.1109/IRPS.1975.362693","url":null,"abstract":"Four types of microwave transistors were tested for D. C. electromigration under accelerated to typical use conditions. A lower activation energy was obtained along with a larger preexponential constant and smaller exponent for current density for the typical electromigration equation. Three of the transistor types were also run in an operational life test at 2.0GHz. After 5,000 hours of testing, the beginnings of a correlation between the D.C. and R.F. testing have appeared. Also oscillators have failed; while amplifiers have not. Power cycling of gold lead wires has shown no fatigue deterioration of the wires or bonds. Temperature step stress showed a semiconductor device cannot be used above its eutectic temperature. A computer model is used to calculate operating temperature at high case temperature and power loading, where actual measurements are difficult to make and intrepret.","PeriodicalId":369161,"journal":{"name":"13th International Reliability Physics Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133464924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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