Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226937
E. Efremova, N. Maksimov, A. Panas
In this report the problem of forming chaotic signals with prescribed spectrum is discussed. Possibilities of chaotic spectrum control in band-limited chaotic oscillator are demonstrated. Dependence of the form and ruggedness of chaotic spectrum on system parameters is shown.
{"title":"Control of power spectrum envelope in single-transistor chaotic oscillator","authors":"E. Efremova, N. Maksimov, A. Panas","doi":"10.1109/SCS.2003.1226937","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226937","url":null,"abstract":"In this report the problem of forming chaotic signals with prescribed spectrum is discussed. Possibilities of chaotic spectrum control in band-limited chaotic oscillator are demonstrated. Dependence of the form and ruggedness of chaotic spectrum on system parameters is shown.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126581640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227090
B. Dumitrescu
We describe a convex domain around a given stable 2-D polynomial, in the form of a linear matrix inequality. Such a domain is useful in the design of 2-D IIR filters with non-separable denominator.
{"title":"2-D convex stability domain","authors":"B. Dumitrescu","doi":"10.1109/SCS.2003.1227090","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227090","url":null,"abstract":"We describe a convex domain around a given stable 2-D polynomial, in the form of a linear matrix inequality. Such a domain is useful in the design of 2-D IIR filters with non-separable denominator.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130391226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226975
M. Costin, A. Grichnik, M. Zbancioc
This study reveals more interesting aspects on speaker and speech recognition as: 1. different importance of certain spectral frequency bands on the process of speaker and speech recognition; 2. signal phase has a significant importance; and 3. vowel recognition is preponderant in the decision weighting. To resolve the paradox described in A.J. Grichnik (2000), autoregressive (AR) coefficients were used to compute feature vectors in order to teach neural networks (NN). Tests made by using a two layer perceptron (MLP) were compared to a radial basis function (RBF) network in order to obtain the best recognition results.
{"title":"Tips on speaker recognition by autoregressive parameters and connectionist methods","authors":"M. Costin, A. Grichnik, M. Zbancioc","doi":"10.1109/SCS.2003.1226975","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226975","url":null,"abstract":"This study reveals more interesting aspects on speaker and speech recognition as: 1. different importance of certain spectral frequency bands on the process of speaker and speech recognition; 2. signal phase has a significant importance; and 3. vowel recognition is preponderant in the decision weighting. To resolve the paradox described in A.J. Grichnik (2000), autoregressive (AR) coefficients were used to compute feature vectors in order to teach neural networks (NN). Tests made by using a two layer perceptron (MLP) were compared to a radial basis function (RBF) network in order to obtain the best recognition results.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227011
C. Comsa, I. Bogdan
Multicarrier or Orthogonal Frequency Division Multiplexing (OFDM) has gain recently an increased interest with the development of faster signal processing components and technologies. OFDM has been shown to be a very efficient scheme for mitigating the adverse effects of inter-symbol interference, squeezing multiple modulated carriers tightly together but keeping the modulated signals orthogonal so they do not interfere with each other's. This paper describes the system level model of the OFDM baseband and uses it to evaluate the BER performance.
{"title":"System level design of baseband OFDM for wireless LAN","authors":"C. Comsa, I. Bogdan","doi":"10.1109/SCS.2003.1227011","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227011","url":null,"abstract":"Multicarrier or Orthogonal Frequency Division Multiplexing (OFDM) has gain recently an increased interest with the development of faster signal processing components and technologies. OFDM has been shown to be a very efficient scheme for mitigating the adverse effects of inter-symbol interference, squeezing multiple modulated carriers tightly together but keeping the modulated signals orthogonal so they do not interfere with each other's. This paper describes the system level model of the OFDM baseband and uses it to evaluate the BER performance.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131575002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226964
S. Di Pascoli, L. Fanucci, F. Giusti, B. Neri, D. Zito
A fully integrated RF single-conversion heterodyne receiver front-end for ISM band (2.44 GHz) wireless applications is presented. The circuit realizes a high image rejection by exploiting a band pass low noise amplifier and an image-reject mixer according to the Hartley architecture. The front-end has been designed on a 50 GHz cut-off frequency bipolar process. The main characteristics of this design are an overall image-rejection greater than 57 dB at 110 MHz of intermediate frequency, a transducer power gain of 32 dB, a bandwidth of 80 MHz, an input linearity range up to -20 dBm, a power consumption of 96 mW, and finally, it does not require external components.
{"title":"Fully integrated heterodyne RF receiver for ISM band applications","authors":"S. Di Pascoli, L. Fanucci, F. Giusti, B. Neri, D. Zito","doi":"10.1109/SCS.2003.1226964","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226964","url":null,"abstract":"A fully integrated RF single-conversion heterodyne receiver front-end for ISM band (2.44 GHz) wireless applications is presented. The circuit realizes a high image rejection by exploiting a band pass low noise amplifier and an image-reject mixer according to the Hartley architecture. The front-end has been designed on a 50 GHz cut-off frequency bipolar process. The main characteristics of this design are an overall image-rejection greater than 57 dB at 110 MHz of intermediate frequency, a transducer power gain of 32 dB, a bandwidth of 80 MHz, an input linearity range up to -20 dBm, a power consumption of 96 mW, and finally, it does not require external components.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227123
D. Burdia, G. Grigore, C. Ionascu
In this paper, analytical expressions characterizing the output voltage, propagation delay and short-circuit energy dissipation of a CMOS inverter driving resistive interconnects are presented. The α-power law MOSFET model is used. A detailed analysis of the inverter operation is provided, which results in accurate expressions of the output response to an input ramp. The propagation delay is analytically calculated taking into account the coupling capacitance between input and output and the effect of the short-circuit current. In addition, the short-circuit energy dissipation is accurately estimated. Experimental results showed that our analytical expressions for propagation delay and short-circuit energy are in very good agreement with SPICE simulations.
{"title":"Delay and short-circuit power expressions characterizing a CMOS inverter driving resistive interconnect","authors":"D. Burdia, G. Grigore, C. Ionascu","doi":"10.1109/SCS.2003.1227123","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227123","url":null,"abstract":"In this paper, analytical expressions characterizing the output voltage, propagation delay and short-circuit energy dissipation of a CMOS inverter driving resistive interconnects are presented. The α-power law MOSFET model is used. A detailed analysis of the inverter operation is provided, which results in accurate expressions of the output response to an input ramp. The propagation delay is analytically calculated taking into account the coupling capacitance between input and output and the effect of the short-circuit current. In addition, the short-circuit energy dissipation is accurately estimated. Experimental results showed that our analytical expressions for propagation delay and short-circuit energy are in very good agreement with SPICE simulations.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226987
D. Neacşu
This paper introduces a new direct topology for AC/AC conversion with reduced passive components and extended output voltage range. Comparisons with usual solutions for three-phase to three-phase conversion are detailed. This converter topology is easy to be controlled with conventionally DSP systems.
{"title":"IGBT-based \"cycloconverters\" built of conventional current source inverter modules","authors":"D. Neacşu","doi":"10.1109/SCS.2003.1226987","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226987","url":null,"abstract":"This paper introduces a new direct topology for AC/AC conversion with reduced passive components and extended output voltage range. Comparisons with usual solutions for three-phase to three-phase conversion are detailed. This converter topology is easy to be controlled with conventionally DSP systems.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131207445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227010
D. Truscan, S. Virtanen, J. Lilius
In this paper, we present our use of SystemC to simulate IPv6 router architecture on our TTA based protocol processor. Our approach makes it easy to verify the correct functionality and to identify performances bottlenecks in the architecture within a short time frame. All this is done prior to proceeding to synthesize the processor into hardware.
{"title":"SystemC simulation framework of protocol processing architectures for IPv6 routing","authors":"D. Truscan, S. Virtanen, J. Lilius","doi":"10.1109/SCS.2003.1227010","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227010","url":null,"abstract":"In this paper, we present our use of SystemC to simulate IPv6 router architecture on our TTA based protocol processor. Our approach makes it easy to verify the correct functionality and to identify performances bottlenecks in the architecture within a short time frame. All this is done prior to proceeding to synthesize the processor into hardware.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132338190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226997
J. Plosila, P. Liljeberg, J. Isoaho
This paper describes an on-chip bus architecture targeted for the globally asynchronous locally synchronous system-on-chip design strategy. The proposed pipelined bus structure is composed of asynchronously interacting segments which can operate in parallel. The bus is segmented using transfer stages which partition bus into a set of point-to-point interconnects. Self-timed arbitration and control is distributed among the pipelined stages to enable parallel operation of distinct segments, to prevent problems present in a globally clocked system, and to increase design modularity. In a 0.18 μm technology, each bus segment is capable of transferring data at a maximum throughput of 1.2 giga data items per second concurrently in both directions.
{"title":"Pipelined on-chip bus architecture with distributed self-timed control","authors":"J. Plosila, P. Liljeberg, J. Isoaho","doi":"10.1109/SCS.2003.1226997","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226997","url":null,"abstract":"This paper describes an on-chip bus architecture targeted for the globally asynchronous locally synchronous system-on-chip design strategy. The proposed pipelined bus structure is composed of asynchronously interacting segments which can operate in parallel. The bus is segmented using transfer stages which partition bus into a set of point-to-point interconnects. Self-timed arbitration and control is distributed among the pipelined stages to enable parallel operation of distinct segments, to prevent problems present in a globally clocked system, and to increase design modularity. In a 0.18 μm technology, each bus segment is capable of transferring data at a maximum throughput of 1.2 giga data items per second concurrently in both directions.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117080145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227114
B. Metin, E. Arslan, O. Cicekoglu
Current conveyor was developed by Sedra at almost the same time with the commercial IC opamp in 1968. Although it is one of the oldest active components and has a better frequency response than opamp, there are not as many applications presented in the literature as with the opamp that is used in a wide variety of applications in electronic circuits. This paper aims to use this old however beneficial element in the analogue filter area by giving several new all-pass filter applications. All circuits given employ a single capacitor and are therefore canonic in the number of capacitors.
{"title":"All-pass sections realized with single first generation current conveyor","authors":"B. Metin, E. Arslan, O. Cicekoglu","doi":"10.1109/SCS.2003.1227114","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227114","url":null,"abstract":"Current conveyor was developed by Sedra at almost the same time with the commercial IC opamp in 1968. Although it is one of the oldest active components and has a better frequency response than opamp, there are not as many applications presented in the literature as with the opamp that is used in a wide variety of applications in electronic circuits. This paper aims to use this old however beneficial element in the analogue filter area by giving several new all-pass filter applications. All circuits given employ a single capacitor and are therefore canonic in the number of capacitors.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122320173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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