Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.363002
C. Canali, F. Fantini, G. Queirolo, E. Zanoni
Metallurgical and electrical failure mechanisms of the PtSi- Ti/W-Al metal system were investigated in commercial bipolar logic devices and in "to the purpose" prepared samples. SEM, microprobe, AES and X-ray diffraction were used to study interdiffusion phenomena and intermetallic compound formation which were correlated to Schottky diode barrier height changes induced by thermal annealing. A few monolayers of oxygen at the Al-Ti/W interface will strongly reduce the degradation phenomena.
{"title":"\"Reliability of PtSi-Ti/W-Al Metallization System used in Bipolar Logics\"","authors":"C. Canali, F. Fantini, G. Queirolo, E. Zanoni","doi":"10.1109/IRPS.1981.363002","DOIUrl":"https://doi.org/10.1109/IRPS.1981.363002","url":null,"abstract":"Metallurgical and electrical failure mechanisms of the PtSi- Ti/W-Al metal system were investigated in commercial bipolar logic devices and in \"to the purpose\" prepared samples. SEM, microprobe, AES and X-ray diffraction were used to study interdiffusion phenomena and intermetallic compound formation which were correlated to Schottky diode barrier height changes induced by thermal annealing. A few monolayers of oxygen at the Al-Ti/W interface will strongly reduce the degradation phenomena.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130383440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.363001
L. Dechiaro
Electro-thermomigration (ETM) of aluminum metallization through contact windows into the substrate accounts for many of the burh-in failures for certain NMOS LSI devices. The developmental history of this failure mode was studied by an analysis of the failed devices and by controlled ESD stressing. The failure mode tends to preferentially occur at parasitic bipolar transistor sites which exhibit minimum BVCEO and which contain an aluminum contact window located close to the collector-base junction. By applying the mathematical model of Raburn and Causey1, the BVCEO values for two important parasitics are calculated as a function of layout and processing parameters. In combination with the ETM studies of Christou2, these results are used to generate layout recommendations which yield an improved resistance to the ETM failure mode.
{"title":"Electro-Thermomigration in NMOS LSI Devices","authors":"L. Dechiaro","doi":"10.1109/IRPS.1981.363001","DOIUrl":"https://doi.org/10.1109/IRPS.1981.363001","url":null,"abstract":"Electro-thermomigration (ETM) of aluminum metallization through contact windows into the substrate accounts for many of the burh-in failures for certain NMOS LSI devices. The developmental history of this failure mode was studied by an analysis of the failed devices and by controlled ESD stressing. The failure mode tends to preferentially occur at parasitic bipolar transistor sites which exhibit minimum BVCEO and which contain an aluminum contact window located close to the collector-base junction. By applying the mathematical model of Raburn and Causey1, the BVCEO values for two important parasitics are calculated as a function of layout and processing parameters. In combination with the ETM studies of Christou2, these results are used to generate layout recommendations which yield an improved resistance to the ETM failure mode.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127644558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-07DOI: 10.1109/IRPS.1981.362968
O. Hallberg
Statistics on voltage-accelerated failures of 4K NMOS RAM's have been compared with accelerated life test data and with real field use data. It is concluded that it is possible to get long-term reliability information from fast overvoltage step stress tests such as 40 ms and 1.2 s dwell time per step. The correlation between step stress data and life-test failures representing the main population is good. It is possible to use this quick test for lot acceptance and to design a proper voltage screening for the particular batch under test. The need for conventional burn-in testing would thus be reduced.
{"title":"NMOS Voltage Breakdown Characteristics Compared with Accelerated Life Tests and Field use Data","authors":"O. Hallberg","doi":"10.1109/IRPS.1981.362968","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362968","url":null,"abstract":"Statistics on voltage-accelerated failures of 4K NMOS RAM's have been compared with accelerated life test data and with real field use data. It is concluded that it is possible to get long-term reliability information from fast overvoltage step stress tests such as 40 ms and 1.2 s dwell time per step. The correlation between step stress data and life-test failures representing the main population is good. It is possible to use this quick test for lot acceptance and to design a proper voltage screening for the particular batch under test. The need for conventional burn-in testing would thus be reduced.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115816010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-01DOI: 10.1109/IRPS.1981.362988
R. Lowry, R. Masters
Surfaces of a wide variety of IC materials, from raw silicon wafers to package piece parts, must be ultra-clean prior to key manufacturing steps to assure reliable performance of the finished devices. Knowledge of surface cleanliness is essential for optimum process design. Secondary ion mass spectroscopy (SIMS) is utilized to define levels of impurities on critical surfaces at various stages of device manufacture.
{"title":"Evaluation of Critical Surface Cleanliness by Secondary Ion Mass Spectroscopy","authors":"R. Lowry, R. Masters","doi":"10.1109/IRPS.1981.362988","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362988","url":null,"abstract":"Surfaces of a wide variety of IC materials, from raw silicon wafers to package piece parts, must be ultra-clean prior to key manufacturing steps to assure reliable performance of the finished devices. Knowledge of surface cleanliness is essential for optimum process design. Secondary ion mass spectroscopy (SIMS) is utilized to define levels of impurities on critical surfaces at various stages of device manufacture.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115609438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-01DOI: 10.1109/IRPS.1981.362973
Masaaki Isagawa, Hideo Oniyama, Hideo Azegami
The memory retention life and its repeatability was examined under conditions of high temperature storage, temperature cycling, bias operating, and high humidity, and after write/erase cycles for MNMoOS EAROMs having short memory retention life. It is shown that the high temperature storage and humidity tests are representative of all these tests, retention life during humidity tests for PED's is generally shorter than the unrecoverable failure life, and SiN overcoating extends retention life remarkably.
{"title":"Memory Retention Life at Various Environmental and Life Tests","authors":"Masaaki Isagawa, Hideo Oniyama, Hideo Azegami","doi":"10.1109/IRPS.1981.362973","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362973","url":null,"abstract":"The memory retention life and its repeatability was examined under conditions of high temperature storage, temperature cycling, bias operating, and high humidity, and after write/erase cycles for MNMoOS EAROMs having short memory retention life. It is shown that the high temperature storage and humidity tests are representative of all these tests, retention life during humidity tests for PED's is generally shorter than the unrecoverable failure life, and SiN overcoating extends retention life remarkably.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127482865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-01DOI: 10.1109/IRPS.1981.362977
James L. Spencer, Walter Ff. Schroen, G. Bednarz, John A. Bryan, Terry D. Metzgar, Robert D. Cleveland, D. Edwards
New strain gauge test bars have been designed forming individual and bridge structures for silicon integrated circuits. They are used to quantitatively measure internal stress introduced in IC bars during packaging. The results show that unexpectedly high levels of stress are introduced as a function of plastic material selection as well as mold and cure temperatures of the materials. The stress can be reduced, and process control can be tightened by appropriate choice of packaging conditions. The importance for IC reliability and electrical performance is discussed.
{"title":"New Quantitative Measurements of IC Stress Introduced by Plastic Packages","authors":"James L. Spencer, Walter Ff. Schroen, G. Bednarz, John A. Bryan, Terry D. Metzgar, Robert D. Cleveland, D. Edwards","doi":"10.1109/IRPS.1981.362977","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362977","url":null,"abstract":"New strain gauge test bars have been designed forming individual and bridge structures for silicon integrated circuits. They are used to quantitatively measure internal stress introduced in IC bars during packaging. The results show that unexpectedly high levels of stress are introduced as a function of plastic material selection as well as mold and cure temperatures of the materials. The stress can be reduced, and process control can be tightened by appropriate choice of packaging conditions. The importance for IC reliability and electrical performance is discussed.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"13 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116750594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-01DOI: 10.1109/IRPS.1981.362969
J. L. Boyle, R. Mcintyre, R. E. Youtz, J. T. Nelson
A failure mechanism in NMOS VLSI devices has been traced to radiation damage due to residual radioactive gas found in their hermetically sealed packages. The entrapped gas is a result of hermeticity testing. This report describes the characteristic failure mode of NMOS memories and the changes in transistor characteristics that result from radiation damage. Criteria for the implementation of radioactive tracer leak testing are proposed to prevent failures.
{"title":"Latent B-Radiation Damage in Hermetically Sealed NMOS Devices","authors":"J. L. Boyle, R. Mcintyre, R. E. Youtz, J. T. Nelson","doi":"10.1109/IRPS.1981.362969","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362969","url":null,"abstract":"A failure mechanism in NMOS VLSI devices has been traced to radiation damage due to residual radioactive gas found in their hermetically sealed packages. The entrapped gas is a result of hermeticity testing. This report describes the characteristic failure mode of NMOS memories and the changes in transistor characteristics that result from radiation damage. Criteria for the implementation of radioactive tracer leak testing are proposed to prevent failures.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124625566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-01DOI: 10.1109/IRPS.1981.362993
A. Christou, E. Cohen, A. Macpherson
Failure modes have been identified for two commercially available microwave power GaAs FETs constructed with aluminum gates. MTTF data for Al gate power FETs and Al gate in combination with refractory link power FETs-indicates the presence of a failure mode with a well defined activation energy. The first set of power FETs (Set A) use AuGe/Au source and drain contacts and Al gates. The second set use an Al-TiPt gate with AuGe-TiPt-Au source, drain contacts. The devices from set A were tested at 200°C under rf drive. An MTTF of 2200 hrs was achieved and source-drain electromigration was identified as the primary failure mode. This newly identified failure mode for ohmic contacts has been confirmed by Auger electron spectroscopy, and the SEM. Gallium has been shown to outdiffuse in the contact system with subsequent Ga whisker growth and gate void formation caused by the AuAl couple at the gate. Sputter AES profiles indicated that interdiffusion in the source and drain contacts extends into the active channel region under the bias-stress tests. The analyzed devices from the second set of power FETs (Al-TiPt gate with AuGe-TiPt-Au ohmic contacts) can be separated into four types: A, B, C, D. Type A failed catastrophically, type B failed non-catastrophically type C was annealed in nitrogen at 200-210°C for 150 hours and type D were untested devices which exhibited a high forward gate resistance.
已经确定了两种商用铝栅极微波功率GaAs场效应管的失效模式。Al栅极功率场效应管和Al栅极结合耐火链功率场效应管的MTTF数据表明存在具有明确活化能的失效模式。第一组功率场效应管(A组)使用AuGe/Au源极和漏极触点和Al栅极。第二组使用Al-TiPt栅极与AuGe-TiPt-Au源、漏接点。组A中的器件在200°C射频驱动下进行测试。MTTF达到2200小时，并确定源漏电迁移为主要失效模式。这种新发现的欧姆接触失效模式已被俄歇电子能谱和扫描电镜证实。镓在接触体系中向外扩散，随后镓晶须生长，栅极上的al偶对导致栅极空穴形成。溅射能谱表明，在偏应力测试下，源漏接触的互扩散扩展到有源通道区域。第二组功率场效应管(带有auge - tip - au欧姆触点的Al-TiPt栅极)所分析的器件可分为A、B、C、D四种类型。A型是灾难性失效，B型是非灾难性失效，C型是在200-210°C氮气中退火150小时，D型是未测试的器件，具有较高的正向栅极电阻。
{"title":"Failure Modes in GaAs Power FETs: Ohmic Contact Electromigration and Formation of Refractory Oxides","authors":"A. Christou, E. Cohen, A. Macpherson","doi":"10.1109/IRPS.1981.362993","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362993","url":null,"abstract":"Failure modes have been identified for two commercially available microwave power GaAs FETs constructed with aluminum gates. MTTF data for Al gate power FETs and Al gate in combination with refractory link power FETs-indicates the presence of a failure mode with a well defined activation energy. The first set of power FETs (Set A) use AuGe/Au source and drain contacts and Al gates. The second set use an Al-TiPt gate with AuGe-TiPt-Au source, drain contacts. The devices from set A were tested at 200°C under rf drive. An MTTF of 2200 hrs was achieved and source-drain electromigration was identified as the primary failure mode. This newly identified failure mode for ohmic contacts has been confirmed by Auger electron spectroscopy, and the SEM. Gallium has been shown to outdiffuse in the contact system with subsequent Ga whisker growth and gate void formation caused by the AuAl couple at the gate. Sputter AES profiles indicated that interdiffusion in the source and drain contacts extends into the active channel region under the bias-stress tests. The analyzed devices from the second set of power FETs (Al-TiPt gate with AuGe-TiPt-Au ohmic contacts) can be separated into four types: A, B, C, D. Type A failed catastrophically, type B failed non-catastrophically type C was annealed in nitrogen at 200-210°C for 150 hours and type D were untested devices which exhibited a high forward gate resistance.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132324313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-01DOI: 10.1109/IRPS.1981.362995
B. A. Unger
ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exceed the limits of the protection networks. Damage from ESDs can cause either complete device failure by parametric shifts, or device weakness by flocally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. 1. A charged person touches a device and discharges the stored charge to or through the device to ground. 2. The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. 3. An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: 1.
{"title":"Electrostatic Discharge Failures of Semiconductor Devices","authors":"B. A. Unger","doi":"10.1109/IRPS.1981.362995","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362995","url":null,"abstract":"ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exceed the limits of the protection networks. Damage from ESDs can cause either complete device failure by parametric shifts, or device weakness by flocally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. 1. A charged person touches a device and discharges the stored charge to or through the device to ground. 2. The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. 3. An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: 1.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133632935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-04-01DOI: 10.1109/IRPS.1981.362974
James Calderbank, P. Holloway
This paper reviews the analysis of exterior leakage paths causing failures of common 2N2222A transistors. The failure mechanism, exterior leakage paths activated in high humidity conditions on the surface of glass seals, is identified. The glass constituents which are responsible for this intermittent, sometime self-correcting failure mechanism are discussed and the method of conduction analyzed.
{"title":"Humidity Activated Surface Leakage Paths on T.O. Case Style Glass Headers","authors":"James Calderbank, P. Holloway","doi":"10.1109/IRPS.1981.362974","DOIUrl":"https://doi.org/10.1109/IRPS.1981.362974","url":null,"abstract":"This paper reviews the analysis of exterior leakage paths causing failures of common 2N2222A transistors. The failure mechanism, exterior leakage paths activated in high humidity conditions on the surface of glass seals, is identified. The glass constituents which are responsible for this intermittent, sometime self-correcting failure mechanism are discussed and the method of conduction analyzed.","PeriodicalId":376954,"journal":{"name":"19th International Reliability Physics Symposium","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124684141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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