Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679284
H. M. H. Babu, Tsutomu Sasao
This paper presents a design method for multiple-output networks using time domain multiplexing (TDM) and shared multi-terminal multiple-valued decision diagrams (SMTMDDs). SMTMDDs represent multiple-valued multiple-output functions, while TDM systems transmit several signals on a single line. This method reduces: 1) hardware; 2) logic levels; and 3) pins. In the logic design, we use two types of decision diagrams (DDs): shared binary decision diagrams (SBDDs) and SMTMDDs. We propose heuristic algorithms to derive shared multiterminal binary decision diagrams (SMTBDDs) from SBDDs, and SMTMDDs from SMTBDDs. Experimental results show the compactness of SMTMDDs over SBDDs in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the network, each non-terminal node of an SBDD and an SMTMDD is realized by a multiplexer (MUX). We also present upper bounds on the number of nonterminal nodes to realize an n-input m-output function by an SBDD and an SMTMDD. In addition, we compare the proposed TDM realization with the conventional one.
{"title":"Design of multiple-output networks using time domain multiplexing and shared multi-terminal multiple-valued decision diagrams","authors":"H. M. H. Babu, Tsutomu Sasao","doi":"10.1109/ISMVL.1998.679284","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679284","url":null,"abstract":"This paper presents a design method for multiple-output networks using time domain multiplexing (TDM) and shared multi-terminal multiple-valued decision diagrams (SMTMDDs). SMTMDDs represent multiple-valued multiple-output functions, while TDM systems transmit several signals on a single line. This method reduces: 1) hardware; 2) logic levels; and 3) pins. In the logic design, we use two types of decision diagrams (DDs): shared binary decision diagrams (SBDDs) and SMTMDDs. We propose heuristic algorithms to derive shared multiterminal binary decision diagrams (SMTBDDs) from SBDDs, and SMTMDDs from SMTBDDs. Experimental results show the compactness of SMTMDDs over SBDDs in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the network, each non-terminal node of an SBDD and an SMTMDD is realized by a multiplexer (MUX). We also present upper bounds on the number of nonterminal nodes to realize an n-input m-output function by an SBDD and an SMTMDD. In addition, we compare the proposed TDM realization with the conventional one.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129243046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679324
T. Aoki, T. Higuchi
This paper presents the concept of "set-valued logic" as a foundation for next-generation integrated systems free from interconnection problems. The set-valued logic system employs multiplexable information carriers to achieve highly parallel processing with reduced interconnections. This paper also proposes a new approach to the construction of set-valued logic VLSIs employing pseudo-random sequences as information carriers.
{"title":"Set-valued logic circuits for next generation VLSI architectures","authors":"T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.1998.679324","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679324","url":null,"abstract":"This paper presents the concept of \"set-valued logic\" as a foundation for next-generation integrated systems free from interconnection problems. The set-valued logic system employs multiplexable information carriers to achieve highly parallel processing with reduced interconnections. This paper also proposes a new approach to the construction of set-valued logic VLSIs employing pseudo-random sequences as information carriers.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132629094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679315
M. Baaz, R. Zach
Entailment in propositional Godel logics can be defined in a natural way. While all infinite sets of truth values yield the same sets of tautologies, the entailment relations differ. It is shown that there is a rich structure of infinite-valued Godel logics, only one of which is compact. It is also shown that the compact infinite-valued Godel logic is the only one which interpolates, and the only one with an r.e. entailment relation.
{"title":"Compact propositional Godel logics","authors":"M. Baaz, R. Zach","doi":"10.1109/ISMVL.1998.679315","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679315","url":null,"abstract":"Entailment in propositional Godel logics can be defined in a natural way. While all infinite sets of truth values yield the same sets of tautologies, the entailment relations differ. It is shown that there is a rich structure of infinite-valued Godel logics, only one of which is compact. It is also shown that the compact infinite-valued Godel logic is the only one which interpolates, and the only one with an r.e. entailment relation.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128824270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679340
R. Stankovic, D. Jankovic, C. Moraga
In this paper, we introduce Reed-Muller-Fourier representations of four-valued functions over the ring of integers modulo 4 and compare them with the Galois field representations over GF(4). It is reported that on the average Reed-Muller-Fourier representations exhibit a lower complexity than those based on Galois field polynomials.
{"title":"Reed-Muller-Fourier versus Galois field representations of four-valued logic functions","authors":"R. Stankovic, D. Jankovic, C. Moraga","doi":"10.1109/ISMVL.1998.679340","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679340","url":null,"abstract":"In this paper, we introduce Reed-Muller-Fourier representations of four-valued functions over the ring of integers modulo 4 and compare them with the Galois field representations over GF(4). It is reported that on the average Reed-Muller-Fourier representations exhibit a lower complexity than those based on Galois field polynomials.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"18 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679470
Shugang Wei, K. Shimizu
Multiple-valued residue arithmetic circuits using integers 4/sup p/ and 4/sup p//spl plusmn/1 as moduli of residue number system (RNS) are presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a radix-4 signed-digit (SD) number system is introduced, and the compact SD adder based on the multiple-valued current-mode circuits is applied for the implementation of high-speed and compact residue arithmetic circuits. The modulo m addition, m=4/sup p/ or m=4/sup p//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time was independent of the word length of operands. Modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and the modulo m multiplication can be performed in a time proportional to log/sub 2/p.
{"title":"Residue arithmetic circuits based on the signed-digit multiple-valued arithmetic circuits","authors":"Shugang Wei, K. Shimizu","doi":"10.1109/ISMVL.1998.679470","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679470","url":null,"abstract":"Multiple-valued residue arithmetic circuits using integers 4/sup p/ and 4/sup p//spl plusmn/1 as moduli of residue number system (RNS) are presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a radix-4 signed-digit (SD) number system is introduced, and the compact SD adder based on the multiple-valued current-mode circuits is applied for the implementation of high-speed and compact residue arithmetic circuits. The modulo m addition, m=4/sup p/ or m=4/sup p//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time was independent of the word length of operands. Modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and the modulo m multiplication can be performed in a time proportional to log/sub 2/p.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"472 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116581303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679266
T. Okuda
A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each level corresponding to the two-bit-data storage of a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier that uses charge coupling and charge sharing was developed for the four level sensing and restoring operations. A 4-Gb DRAM was fabricated using 0.15-/spl mu/m CMOS technology, that measures 986 mm/sup 2/ in area. The area of the memory cell is 0.23 /spl mu/m/sup 2/. Its capacitance of 60 fF is achieved by use of a high-dielectric-constant material (Ba,Sr)TiO/sub 3/.
{"title":"Advanced circuit technology to realize post giga-bit DRAM","authors":"T. Okuda","doi":"10.1109/ISMVL.1998.679266","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679266","url":null,"abstract":"A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each level corresponding to the two-bit-data storage of a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier that uses charge coupling and charge sharing was developed for the four level sensing and restoring operations. A 4-Gb DRAM was fabricated using 0.15-/spl mu/m CMOS technology, that measures 986 mm/sup 2/ in area. The area of the memory cell is 0.23 /spl mu/m/sup 2/. Its capacitance of 60 fF is achieved by use of a high-dielectric-constant material (Ba,Sr)TiO/sub 3/.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121908277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679476
T. Shibata
Implementing intelligent systems directly on integrated circuits hardware is presented. The key concept of the approach is the enhancement in the basic functionality of a transistor and the binary-multivalued-analog merged computation using the functional device. Intelligent LSI systems based on the psychological model of a brain are proposed. The system stores the past experience in non-volatile vast analog memories and recall the maximum-likelihood event to a current input using the association processor working in the analog/digital-merged decision making principle.
{"title":"Functional-device-based VLSI for intelligent electronic systems","authors":"T. Shibata","doi":"10.1109/ISMVL.1998.679476","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679476","url":null,"abstract":"Implementing intelligent systems directly on integrated circuits hardware is presented. The key concept of the approach is the enhancement in the basic functionality of a transistor and the binary-multivalued-analog merged computation using the functional device. Intelligent LSI systems based on the psychological model of a brain are proposed. The system stores the past experience in non-volatile vast analog memories and recall the maximum-likelihood event to a current input using the association processor working in the analog/digital-merged decision making principle.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128033646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679517
Hajime Machida
The lattice L/sub k/ of all clones over the set {0, 1,/spl middot//spl middot//spl middot/, k-1} is known to be a metric space. In this paper, we define some maps induced by the lattice operators and note that those induced by the meet operator are continuous maps from L/sub k/ to L/sub k/. Secondly, we use the meet operator to construct two continuous maps from L/sub 3/ to L/sub 2/. These maps are shown to be order-preserving and surjective. Finally, the images of all the maximal clones in L/sub 3/ and those of Yanov-Muchnik clones in L/sub 3/ under these maps are studied.
{"title":"Some continuous maps on the space of clones in multiple-valued logic","authors":"Hajime Machida","doi":"10.1109/ISMVL.1998.679517","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679517","url":null,"abstract":"The lattice L/sub k/ of all clones over the set {0, 1,/spl middot//spl middot//spl middot/, k-1} is known to be a metric space. In this paper, we define some maps induced by the lattice operators and note that those induced by the meet operator are continuous maps from L/sub k/ to L/sub k/. Secondly, we use the meet operator to construct two continuous maps from L/sub 3/ to L/sub 2/. These maps are shown to be order-preserving and surjective. Finally, the images of all the maximal clones in L/sub 3/ and those of Yanov-Muchnik clones in L/sub 3/ under these maps are studied.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128148663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：