Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679512
F. Wakui, Masato Hirano
This paper shows a proposal and this application of a new membership function based on a career-mode. The career-mode corresponds to a transition direction of non-fuzzy input and outputs as selecting it from among the grade that an ambiguity define by means of two degrees. Here against a hardware development we improve the crossover distortion of the threshold control of multi-valued multi-threshold circuit and show a configuration principle moreover. By these, this paper develops a career-mode fuzzy controller to control the rotation speed of DC motor and it also shows that the career-mode fuzzy control can improve the control characteristics.
{"title":"A proposal and an application of a career-mode membership function","authors":"F. Wakui, Masato Hirano","doi":"10.1109/ISMVL.1998.679512","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679512","url":null,"abstract":"This paper shows a proposal and this application of a new membership function based on a career-mode. The career-mode corresponds to a transition direction of non-fuzzy input and outputs as selecting it from among the grade that an ambiguity define by means of two degrees. Here against a hardware development we improve the crossover distortion of the threshold control of multi-valued multi-threshold circuit and show a configuration principle moreover. By these, this paper develops a career-mode fuzzy controller to control the rotation speed of DC motor and it also shows that the career-mode fuzzy control can improve the control characteristics.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126724587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679296
Liu Ren-ren
In multiple-valued logic theories, the characterization of Sheffer (1913) functions is an important problem, it includes the decision and construction for Sheffer functions in P/sub k/ and P/sub k/*. The solution of these problems depends on the solution of the decision problem of completeness in P/sub k/ and P/sub k/*, and reduced to determining the minimal coverings of precomplete classes in P/sub k/ and P/sub k/* respectively. In this paper, some full symmetric function sets are proved to be the component part of the minimal covering of precomplete classes in P/sub k/*.
{"title":"Some results on the decision for Sheffer functions in partial K-valued logic. II","authors":"Liu Ren-ren","doi":"10.1109/ISMVL.1998.679296","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679296","url":null,"abstract":"In multiple-valued logic theories, the characterization of Sheffer (1913) functions is an important problem, it includes the decision and construction for Sheffer functions in P/sub k/ and P/sub k/*. The solution of these problems depends on the solution of the decision problem of completeness in P/sub k/ and P/sub k/*, and reduced to determining the minimal coverings of precomplete classes in P/sub k/ and P/sub k/* respectively. In this paper, some full symmetric function sets are proved to be the component part of the minimal covering of precomplete classes in P/sub k/*.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128749551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679318
Z. Vranesic
Examines some key issues in the development of field-programmable gate arrays (FPGAs). Design factors that determine the performance and effectiveness of these devices are discussed. The main emphasis is on the structure of logic blocks and interconnection resources. Potential areas for application of multiple-valued logic techniques are considered.
{"title":"The FPGA challenge","authors":"Z. Vranesic","doi":"10.1109/ISMVL.1998.679318","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679318","url":null,"abstract":"Examines some key issues in the development of field-programmable gate arrays (FPGAs). Design factors that determine the performance and effectiveness of these devices are discussed. The main emphasis is on the structure of logic blocks and interconnection resources. Potential areas for application of multiple-valued logic techniques are considered.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131972426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679447
P. Gulak
This paper provides a brief overview of semiconductor memory design from the perspective of the impact multiple-valued circuit techniques are making on modern day implementations. The focus is primarily on CMOS-related technologies.
{"title":"A review of multiple-valued memory technology","authors":"P. Gulak","doi":"10.1109/ISMVL.1998.679447","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679447","url":null,"abstract":"This paper provides a brief overview of semiconductor memory design from the perspective of the impact multiple-valued circuit techniques are making on modern day implementations. The focus is primarily on CMOS-related technologies.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"200 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134324657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679291
H. M. Chung, S. Pi, S. Rey
Generally, multiple valued logic algebra is based on the number system of modulo-M. In this paper, characters a, b, c,... each of which represents the independent state, are regarded as the elements of the symbolic multiple valued logic. By using set theory, the symbolic multiple valued logic and their functions are defined. Variations of the symbolic logic function due to the variation of a variable and their properties are suggested and analyzed. With these variations, the MacLaurin's and Taylor's series expansions of the symbolic multiple valued logic functions are proposed and proved. The theory and properties may be available in the design and modeling of the hardware or intelligent system.
{"title":"The MacLaurin's and Taylor's series expansions of the symbolic multiple valued logic functions","authors":"H. M. Chung, S. Pi, S. Rey","doi":"10.1109/ISMVL.1998.679291","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679291","url":null,"abstract":"Generally, multiple valued logic algebra is based on the number system of modulo-M. In this paper, characters a, b, c,... each of which represents the independent state, are regarded as the elements of the symbolic multiple valued logic. By using set theory, the symbolic multiple valued logic and their functions are defined. Variations of the symbolic logic function due to the variation of a variable and their properties are suggested and analyzed. With these variations, the MacLaurin's and Taylor's series expansions of the symbolic multiple valued logic functions are proposed and proved. The theory and properties may be available in the design and modeling of the hardware or intelligent system.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133824518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679270
M. Morisue, J. Endo, T. Morooka, N. Shimizu, M. Sakamoto
A novel ternary logic memory circuit using Josephson junctions is described. The principle of the ternary memory circuit proposed here is based on the persistent circulating current in the superconducting loop in the clockwise and the counter clockwise directions. As the gate for writing and reading operation of the memory, the three-junction SQUID and the JCTL which is constructed by combination of two two-junction SQUIDs are used. In order to develop the memory circuit, we have made the simulations to determine the most suitable circuit parameters to the memory cell and then fabricated the circuit based on 2 /spl mu/m minimum line width technology. The simulation results show satisfactory operations of the memory circuit, which agree well with the experiment results. The advantages of the proposed memory circuit are capability of high speed computation, low power consumption and very simple construction with less number of elements due to the ternary operation.
{"title":"A Josephson ternary memory circuit","authors":"M. Morisue, J. Endo, T. Morooka, N. Shimizu, M. Sakamoto","doi":"10.1109/ISMVL.1998.679270","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679270","url":null,"abstract":"A novel ternary logic memory circuit using Josephson junctions is described. The principle of the ternary memory circuit proposed here is based on the persistent circulating current in the superconducting loop in the clockwise and the counter clockwise directions. As the gate for writing and reading operation of the memory, the three-junction SQUID and the JCTL which is constructed by combination of two two-junction SQUIDs are used. In order to develop the memory circuit, we have made the simulations to determine the most suitable circuit parameters to the memory cell and then fabricated the circuit based on 2 /spl mu/m minimum line width technology. The simulation results show satisfactory operations of the memory circuit, which agree well with the experiment results. The advantages of the proposed memory circuit are capability of high speed computation, low power consumption and very simple construction with less number of elements due to the ternary operation.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121171941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679287
D. M. Miller, R. Drechsler
Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider issues regarding the efficient implementation of a package for the creation and manipulation of multiple-valued decision diagrams (MDDs). In particular we identify issues that differ from binary decision diagram packages. We describe a matrix method for level interchange in MDDs that is essential for implementing variable reordering strategies. In addition, it is the basis for a novel approach to performing logic operations on MDDs, which we also present. Experimental results demonstrate the efficiency of this approach.
{"title":"Implementing a multiple-valued decision diagram package","authors":"D. M. Miller, R. Drechsler","doi":"10.1109/ISMVL.1998.679287","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679287","url":null,"abstract":"Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider issues regarding the efficient implementation of a package for the creation and manipulation of multiple-valued decision diagrams (MDDs). In particular we identify issues that differ from binary decision diagram packages. We describe a matrix method for level interchange in MDDs that is essential for implementing variable reordering strategies. In addition, it is the basis for a novel approach to performing logic operations on MDDs, which we also present. Experimental results demonstrate the efficiency of this approach.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116026993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679350
Yoshinori Yamamoto
In a series of papers, the author proposed an approximate reasoning method which expresses reasoning rules with one newly-defined infinitely-valued threshold function to use it as a reasoning engine, and discussed the advantages and limitations to the fuzzy reasoning. The subject of this paper is the remained problem: how to express the complicated reasoning rules containing non-linearity, non-unateness, etc. The problem is related to the multi-stage synthesis of multiple-valued threshold functions. A synthesis method using the genetic algorithm is devised here with some promising results of realization of arbitrary multiple-valued logic function by threshold functions.
{"title":"A synthesis method of the approximate reasoning engine by means of genetic algorithm-neural net realization of any multiple-valued logic function using GA","authors":"Yoshinori Yamamoto","doi":"10.1109/ISMVL.1998.679350","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679350","url":null,"abstract":"In a series of papers, the author proposed an approximate reasoning method which expresses reasoning rules with one newly-defined infinitely-valued threshold function to use it as a reasoning engine, and discussed the advantages and limitations to the fuzzy reasoning. The subject of this paper is the remained problem: how to express the complicated reasoning rules containing non-linearity, non-unateness, etc. The problem is related to the multi-stage synthesis of multiple-valued threshold functions. A synthesis method using the genetic algorithm is devised here with some promising results of realization of arbitrary multiple-valued logic function by threshold functions.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124340667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679323
T. Hanyu, T. Saito, M. Kameyama
This paper presents a new asynchronous data-transfer in a multi-valued current-mode VLSI circuit based on dual-rail differential logic. In the proposed 2-phase multiple-valued asynchronous communication scheme, R-valued dual-rail complementary signals are used to represent a "data value" while the "spacer" is represented as (0, 0). The sum of R-valued dual-rail complementary values is a constant (R-1) which makes it easy to distinguish a data-arrival state from a data-transition state. This scheme can be extended to any multiple-valued data representation in asynchronous communication. New basic components, a signal-state detector to detect a data-arrival state, and a current-controlled threshold detector to produce dual-rail spacer signals (0,0) are also proposed to realize a compact asynchronous control circuit. It is demonstrated that the overhead for the proposed asynchronous circuit is very small compared with the conventional synchronous multiple-valued current-mode logic approach.
{"title":"Asynchronous multiple-valued VLSI system based on dual-rail current-mode differential logic","authors":"T. Hanyu, T. Saito, M. Kameyama","doi":"10.1109/ISMVL.1998.679323","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679323","url":null,"abstract":"This paper presents a new asynchronous data-transfer in a multi-valued current-mode VLSI circuit based on dual-rail differential logic. In the proposed 2-phase multiple-valued asynchronous communication scheme, R-valued dual-rail complementary signals are used to represent a \"data value\" while the \"spacer\" is represented as (0, 0). The sum of R-valued dual-rail complementary values is a constant (R-1) which makes it easy to distinguish a data-arrival state from a data-transition state. This scheme can be extended to any multiple-valued data representation in asynchronous communication. New basic components, a signal-state detector to detect a data-arrival state, and a current-controlled threshold detector to produce dual-rail spacer signals (0,0) are also proposed to realize a compact asynchronous control circuit. It is demonstrated that the overhead for the proposed asynchronous circuit is very small compared with the conventional synchronous multiple-valued current-mode logic approach.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131340413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679469
T. Hanyu, K. Teranishi, M. Kameyama
A new logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. Since, multiple-valued pass-transistor network is realized by multiple-valued threshold-literal and pass-switch functions, it can be designed compactly by using floating-gate MOS transistors. As an example of typical logic-in memory VLSI systems, a fully parallel magnitude comparator is also presented. The performance of the proposed multiple-valued logic-in-memory VLSI is about 26 times higher than that of the corresponding implementation based on a binary content-addressable memory under a 0.8 /spl mu/m flash EEPROM technology. Moreover, its effective chip area and power dissipation are reduced to about 42 and 20 percents, respectively, in comparison with those of binary implementation.
{"title":"Multiple-valued floating-gate-MOS pass logic and its application to logic-in-memory VLSI","authors":"T. Hanyu, K. Teranishi, M. Kameyama","doi":"10.1109/ISMVL.1998.679469","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679469","url":null,"abstract":"A new logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. Since, multiple-valued pass-transistor network is realized by multiple-valued threshold-literal and pass-switch functions, it can be designed compactly by using floating-gate MOS transistors. As an example of typical logic-in memory VLSI systems, a fully parallel magnitude comparator is also presented. The performance of the proposed multiple-valued logic-in-memory VLSI is about 26 times higher than that of the corresponding implementation based on a binary content-addressable memory under a 0.8 /spl mu/m flash EEPROM technology. Moreover, its effective chip area and power dissipation are reduced to about 42 and 20 percents, respectively, in comparison with those of binary implementation.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131264223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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