Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682949
Seungwhun Paik, Youngsoo Shin
The use of the slow and power-consuming flip-flops is one of the factors that cause a large gap between custom and ASIC designs. A pulsed-latch, which is a latch driven by a brief pulse clock, inherits the advantage of latch while allowing us to use a simple timing model similar to that of flip-flop. As a result, it offers the opportunity of higher performance and lower power consumption within the conventional ASIC design environment. We address challenges and problems specific to pulsed-latch ASIC, and review potential solutions. Some quantitative results are provided to assess the effectiveness of pulsed-latch circuits.
{"title":"Pulsed-latch circuits to push the envelope of ASIC design","authors":"Seungwhun Paik, Youngsoo Shin","doi":"10.1109/SOCDC.2010.5682949","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682949","url":null,"abstract":"The use of the slow and power-consuming flip-flops is one of the factors that cause a large gap between custom and ASIC designs. A pulsed-latch, which is a latch driven by a brief pulse clock, inherits the advantage of latch while allowing us to use a simple timing model similar to that of flip-flop. As a result, it offers the opportunity of higher performance and lower power consumption within the conventional ASIC design environment. We address challenges and problems specific to pulsed-latch ASIC, and review potential solutions. Some quantitative results are provided to assess the effectiveness of pulsed-latch circuits.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116659366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682958
S. Sriram, Haiqing Nan, K. Choi
As technology is scaling down, circuit reliability issues are major concerns because digital circuits are more susceptible to external noise sources. Soft Error is one such source which changes the voltage of internal nodes of the circuit. Hence it is necessary to design soft error (SE) immune digital circuits. In this paper, we proposed a novel SE immune latch circuit which operates at 0.5V using 32nm technology node. Compared to previous hardened latches up to date, the proposed latch circuit completely immunes to SE on any node of the circuit with 26% total delay reduction.
{"title":"Dual loop hardened latch circuit for low power application","authors":"S. Sriram, Haiqing Nan, K. Choi","doi":"10.1109/SOCDC.2010.5682958","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682958","url":null,"abstract":"As technology is scaling down, circuit reliability issues are major concerns because digital circuits are more susceptible to external noise sources. Soft Error is one such source which changes the voltage of internal nodes of the circuit. Hence it is necessary to design soft error (SE) immune digital circuits. In this paper, we proposed a novel SE immune latch circuit which operates at 0.5V using 32nm technology node. Compared to previous hardened latches up to date, the proposed latch circuit completely immunes to SE on any node of the circuit with 26% total delay reduction.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122426976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682930
Bongki Lee, Jaehwan Kim, Yeuncheul Jeung, J. Chong
In this paper, we propose the task scheduling for preventing the occurrence of peak power in the multi-core systems considering data dependence. In the mobile system, the peak power reduces the battery lifetime and makes the system unstable. Among the power consumption of system, the proportion of power consumption of core is very large. If cores execute multiple tasks simultaneously, this gives rise to the peak power. Therefore, algorithm to minimize the occurrence of peak power is needed. When multiple tasks are allocated to the multi-core systems, data dependence relations of all tasks should be considered to avoid data interferences. The proposed algorithm to reduce the peak power schedules the tasks with the data dependence information after data dependence analysis. The proposed algorithm is composed of task partitioning step, data dependence analysis step and priority scheduling step. The simulation results show that the proposed algorithm reduce the occurrence of peak power by up to around 11% compared to the existing algorithms.
{"title":"Peak power reduction methodology for multi-core systems","authors":"Bongki Lee, Jaehwan Kim, Yeuncheul Jeung, J. Chong","doi":"10.1109/SOCDC.2010.5682930","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682930","url":null,"abstract":"In this paper, we propose the task scheduling for preventing the occurrence of peak power in the multi-core systems considering data dependence. In the mobile system, the peak power reduces the battery lifetime and makes the system unstable. Among the power consumption of system, the proportion of power consumption of core is very large. If cores execute multiple tasks simultaneously, this gives rise to the peak power. Therefore, algorithm to minimize the occurrence of peak power is needed. When multiple tasks are allocated to the multi-core systems, data dependence relations of all tasks should be considered to avoid data interferences. The proposed algorithm to reduce the peak power schedules the tasks with the data dependence information after data dependence analysis. The proposed algorithm is composed of task partitioning step, data dependence analysis step and priority scheduling step. The simulation results show that the proposed algorithm reduce the occurrence of peak power by up to around 11% compared to the existing algorithms.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129009617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682901
Jung-hyen Lee, B. Michael, Hojin Park, Byeong-ha Park
A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm2 active area.
{"title":"A 7b 1GS/s 60mW folding ADC in 65nm CMOS","authors":"Jung-hyen Lee, B. Michael, Hojin Park, Byeong-ha Park","doi":"10.1109/SOCDC.2010.5682901","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682901","url":null,"abstract":"A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm2 active area.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682967
S. Shibata, S. Honda, H. Tomiyama, H. Takada
This paper presents our integrated system-level design tool set, named Advanced SystemBuilder. Advanced SystemBuilder supports overall methodology for system design and design space exploration, and provides programming model of systems, automatic synthesis capabilities for FPGA-based prototyping, cosimulation and execution profiling. A case study of MPEG4 decoder design shows the effectiveness of the design space exploration methodology with Advanced SystemBuilder.
{"title":"Advanced SystemBuilder: A tool set for multiprocessor design space exploration","authors":"S. Shibata, S. Honda, H. Tomiyama, H. Takada","doi":"10.1109/SOCDC.2010.5682967","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682967","url":null,"abstract":"This paper presents our integrated system-level design tool set, named Advanced SystemBuilder. Advanced SystemBuilder supports overall methodology for system design and design space exploration, and provides programming model of systems, automatic synthesis capabilities for FPGA-based prototyping, cosimulation and execution profiling. A case study of MPEG4 decoder design shows the effectiveness of the design space exploration methodology with Advanced SystemBuilder.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127558607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682988
Hailong Jiao, V. Kursun
A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by up to 3.84× and the read static noise margin is increased by up to 4.79× with the new memory power gating technique as compared to a previously published power gated 6T SRAM circuit in a UMC 80nm CMOS technology.
{"title":"Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode","authors":"Hailong Jiao, V. Kursun","doi":"10.1109/SOCDC.2010.5682988","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682988","url":null,"abstract":"A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by up to 3.84× and the read static noise margin is increased by up to 4.79× with the new memory power gating technique as compared to a previously published power gated 6T SRAM circuit in a UMC 80nm CMOS technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114468459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682932
Wooheon Kang, Hyungjun Cho, Sungho Kang
With the growth of memory capacity and density, test cost and yield improvement are becoming more important. To increase yield of memory, redundancy analysis (RA) which analyzes the faults in memory is essential. However, the time for finding solutions to repair memories with faulty cells is very huge because most RA algorithms for automatic test equipment (ATE) are based on a tree structure. To reduce the time of memory test & repair is important to increase the memory yield using ATE. In order to reduce the time of memory test & repair, an RA algorithm with an early termination condition is proposed and it builds a geometric faults based search tree. To build the proposed algorithm, the faults in a memory are classified into geometric faults according to their characteristic. The experimental results show the effectiveness of the proposed algorithm.
{"title":"Enhenced redundancy analysis for memories using geometric faults based search tree","authors":"Wooheon Kang, Hyungjun Cho, Sungho Kang","doi":"10.1109/SOCDC.2010.5682932","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682932","url":null,"abstract":"With the growth of memory capacity and density, test cost and yield improvement are becoming more important. To increase yield of memory, redundancy analysis (RA) which analyzes the faults in memory is essential. However, the time for finding solutions to repair memories with faulty cells is very huge because most RA algorithms for automatic test equipment (ATE) are based on a tree structure. To reduce the time of memory test & repair is important to increase the memory yield using ATE. In order to reduce the time of memory test & repair, an RA algorithm with an early termination condition is proposed and it builds a geometric faults based search tree. To build the proposed algorithm, the faults in a memory are classified into geometric faults according to their characteristic. The experimental results show the effectiveness of the proposed algorithm.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121974194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682963
Teng-Yuan Cheng, Tsung-Huang Chen, C. Jason, Shao-Yi Chien
The coarse-grained reconfigurable image stream processor (CRISP) architecture is introduced for the image processing demands of high-definition (HD) cameras and camcorders. With several architectural concepts of the reconfigurable architecture, the CRISP architecture is proposed to meet the performance and flexibility requirements of the HD cameras. A multi-frame processing system with CRISP is implemented to achieve the real-time HD video recording and 11M-pixel image processing capability. Compared with the performance of the high-dynamic-range image fusion algorithm implemented with a general-purpose processor, 106 times speed-up is achieved by the proposed processor with high image quality of 42.5dB in PSNR.
{"title":"Coarse-grained reconfigurable image stream processor architecture for high-definition cameras and camcorders","authors":"Teng-Yuan Cheng, Tsung-Huang Chen, C. Jason, Shao-Yi Chien","doi":"10.1109/SOCDC.2010.5682963","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682963","url":null,"abstract":"The coarse-grained reconfigurable image stream processor (CRISP) architecture is introduced for the image processing demands of high-definition (HD) cameras and camcorders. With several architectural concepts of the reconfigurable architecture, the CRISP architecture is proposed to meet the performance and flexibility requirements of the HD cameras. A multi-frame processing system with CRISP is implemented to achieve the real-time HD video recording and 11M-pixel image processing capability. Compared with the performance of the high-dynamic-range image fusion algorithm implemented with a general-purpose processor, 106 times speed-up is achieved by the proposed processor with high image quality of 42.5dB in PSNR.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114067959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682896
Hae-Kang Jung, Soo-Min Lee, J. Sim, Hong-June Park
By using the data timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver (RX) at the same time. This transmitter is implemented by using the delay block with low jitter and a 3:1Mux to select one CLKT of the generated three different sampling CLKD, in advance. The TX is implemented by using a 0.18 μm CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps.
{"title":"A transmitter with different output timing to compensate for the crosstalk-induced jitter of coupled microstrip lines","authors":"Hae-Kang Jung, Soo-Min Lee, J. Sim, Hong-June Park","doi":"10.1109/SOCDC.2010.5682896","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682896","url":null,"abstract":"By using the data timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver (RX) at the same time. This transmitter is implemented by using the delay block with low jitter and a 3:1Mux to select one CLKT of the generated three different sampling CLKD, in advance. The TX is implemented by using a 0.18 μm CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124049963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682924
B. S. Angada, M. Baghini, K. Dinesh, V. Rao
This paper focuses on the alternate strategies to enable scaling of Multi-Gate FETs into sub-22 nm nodes. Scaling is not only limited by device level challenges like increasing parasitic resistances and capacitances, but also circuit level challenges like increasing interconnect parasitics, variability etc. The alternate scaling strategies consider both device level and circuit level challenges to obtain overall benefits with scaling.
{"title":"Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications","authors":"B. S. Angada, M. Baghini, K. Dinesh, V. Rao","doi":"10.1109/SOCDC.2010.5682924","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682924","url":null,"abstract":"This paper focuses on the alternate strategies to enable scaling of Multi-Gate FETs into sub-22 nm nodes. Scaling is not only limited by device level challenges like increasing parasitic resistances and capacitances, but also circuit level challenges like increasing interconnect parasitics, variability etc. The alternate scaling strategies consider both device level and circuit level challenges to obtain overall benefits with scaling.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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