Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682938
C. Lin, M. Syrzycki
This paper presents a modified Delay Locked Loop (DLL) based Time Difference Amplifier (TDA) that utilizes a Dynamic-Logic Phase Frequency Detector (PFD). The zero dead-zone characteristic of the Dynamic-Logic PFD allows the DLL to eliminate phase error and maintain a stable gain for single picoseconds input time intervals. The TDA has been designed in 0.13μm CMOS technology. The simulation result demonstrates a linear transfer characteristic for an input time interval range from 0 to 90 ps and a gain shift less than 4.2% under ±10% supply voltage variation and temperature range from −40 D to 80D.
{"title":"Pico-second time interval amplification","authors":"C. Lin, M. Syrzycki","doi":"10.1109/SOCDC.2010.5682938","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682938","url":null,"abstract":"This paper presents a modified Delay Locked Loop (DLL) based Time Difference Amplifier (TDA) that utilizes a Dynamic-Logic Phase Frequency Detector (PFD). The zero dead-zone characteristic of the Dynamic-Logic PFD allows the DLL to eliminate phase error and maintain a stable gain for single picoseconds input time intervals. The TDA has been designed in 0.13μm CMOS technology. The simulation result demonstrates a linear transfer characteristic for an input time interval range from 0 to 90 ps and a gain shift less than 4.2% under ±10% supply voltage variation and temperature range from −40 D to 80D.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126470507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682877
Chanho Lee, Seohoon Yang
H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. We propose variable pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. A smart bus arbiter is introduced to adjust the priority adaptively so that the access to a reference memory does not degrade the performance of the decoding pipeline. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.
{"title":"Design of an H.264 decoder with variable pipeline and smart bus arbiter","authors":"Chanho Lee, Seohoon Yang","doi":"10.1109/SOCDC.2010.5682877","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682877","url":null,"abstract":"H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. We propose variable pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. A smart bus arbiter is introduced to adjust the priority adaptively so that the access to a reference memory does not degrade the performance of the decoding pipeline. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682931
Dongchul Kim, Hyewon Kim, Y. Eo
A new efficient and accurate eye-diagram determination technique for differential signaling is presented. An efficient eye-diagram for the differential transmission lines is determined by decoupling the coupled lines into effective single lines. Introducing the simplest input bit pattern to determine the worst case inter-symbol interference (ISI), the output response for a single line can be readily determined by using Fast Fourier transform technique (FFT). The proposed technique is compared with SPICE W-model-based simulation that employs pseudorandom bit sequence (PRBS) input signals.
{"title":"Efficient eye diagram determination of strongly coupled lines for differential signals","authors":"Dongchul Kim, Hyewon Kim, Y. Eo","doi":"10.1109/SOCDC.2010.5682931","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682931","url":null,"abstract":"A new efficient and accurate eye-diagram determination technique for differential signaling is presented. An efficient eye-diagram for the differential transmission lines is determined by decoupling the coupled lines into effective single lines. Introducing the simplest input bit pattern to determine the worst case inter-symbol interference (ISI), the output response for a single line can be readily determined by using Fast Fourier transform technique (FFT). The proposed technique is compared with SPICE W-model-based simulation that employs pseudorandom bit sequence (PRBS) input signals.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115961688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682934
Keun-Soo Lee, Hyuntae Park, HyeonUk Son, Sungho Kang
As the design for testability (DFT) is essential in the semiconductor manufacturing, the scan-based architecture is widely used to decrease the test complexity of a chip. However, the scan-based architecture requires high test cost such as the test data volume and the test time. In order to alleviate the test cost problem of the scan-based architecture, a lot of test data compression schemes using the scan slice encoding have been presented. In this paper, we propose a new scan slice encoding scheme with flexible code for test data compression. The proposed scheme fully utilizes the flexible code as the control code or the data code. The flexible code provides supplementary encoding mode without additional control code. As a result, the test cost is significantly reduced by the various encoding mode with low test equipment pin overhead. The experiment results based on ISCAS'89 benchmark circuits show that the test data volume and the test time is reduced up to 82% compared with the original data.
{"title":"A new scan slice encoding scheme with flexible code for test data compression","authors":"Keun-Soo Lee, Hyuntae Park, HyeonUk Son, Sungho Kang","doi":"10.1109/SOCDC.2010.5682934","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682934","url":null,"abstract":"As the design for testability (DFT) is essential in the semiconductor manufacturing, the scan-based architecture is widely used to decrease the test complexity of a chip. However, the scan-based architecture requires high test cost such as the test data volume and the test time. In order to alleviate the test cost problem of the scan-based architecture, a lot of test data compression schemes using the scan slice encoding have been presented. In this paper, we propose a new scan slice encoding scheme with flexible code for test data compression. The proposed scheme fully utilizes the flexible code as the control code or the data code. The flexible code provides supplementary encoding mode without additional control code. As a result, the test cost is significantly reduced by the various encoding mode with low test equipment pin overhead. The experiment results based on ISCAS'89 benchmark circuits show that the test data volume and the test time is reduced up to 82% compared with the original data.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121765659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682895
Jong‐Wook Lee, Jia-fu Lin
This paper presents two high power K-band CMOS amplifiers operating at high voltages. The amplifiers employed series-bias technique to increase the operating voltage and achieved a high output power level. The technique also allowed the power amplifiers to operate at a low DC current and thus high efficiency was obtained. The series-bias technique allowed overcoming the low voltage constraint of scaled-down CMOS technology, providing practical solution for realizing high power CMOS amplifier. A two-stage amplifier employing the series-bias technique of four cascode power cells showed a maximum small-signal gain of 25.6 dB, an output power of 20 dBm, and a PAE of 12.5 % at 21 GHz. This is the first CMOS power amplifier delivering 100mW output power above 20 GHz. A three-stage series-bias amplifier having common-source transistor showed a small-signal gain of 17.3 dB, an output power of 17.5 dBm, and a PAE of 8.8% at 23.5 GHz. These amplifiers employing the series-bias technique are shown to have a highly favorable figure-of-merit compared to the results obtained from conventional amplifiers.
{"title":"Series-biased CMOS power amplifiers operating at high voltage for 24 GHz radar applications","authors":"Jong‐Wook Lee, Jia-fu Lin","doi":"10.1109/SOCDC.2010.5682895","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682895","url":null,"abstract":"This paper presents two high power K-band CMOS amplifiers operating at high voltages. The amplifiers employed series-bias technique to increase the operating voltage and achieved a high output power level. The technique also allowed the power amplifiers to operate at a low DC current and thus high efficiency was obtained. The series-bias technique allowed overcoming the low voltage constraint of scaled-down CMOS technology, providing practical solution for realizing high power CMOS amplifier. A two-stage amplifier employing the series-bias technique of four cascode power cells showed a maximum small-signal gain of 25.6 dB, an output power of 20 dBm, and a PAE of 12.5 % at 21 GHz. This is the first CMOS power amplifier delivering 100mW output power above 20 GHz. A three-stage series-bias amplifier having common-source transistor showed a small-signal gain of 17.3 dB, an output power of 17.5 dBm, and a PAE of 8.8% at 23.5 GHz. These amplifiers employing the series-bias technique are shown to have a highly favorable figure-of-merit compared to the results obtained from conventional amplifiers.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132649497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682887
M. Shen, Yi-Shuan Wu, Guan-Hung Ke, Po-Chiun Huang
This paper presents a two-stage pseudo-differential amplifier. Rail-to-rail operations are achieved by using bulk terminals as the inputs. The positive feedback technique is used to enhance the transconductance with negative conductance. The bulk terminals of all transistors are carefully biased to lower their threshold voltages (Vth) and maximize signal swing. Using a standard 0.18-μm CMOS technology, measurement results demonstrate that gain-bandwidth product is 0.97MHz. The settling time for a 0.7-Vpp step is 2.1/μS. The input referred noise is 0.14mV at 1MHz. All the circuits dissipate 0.107μW under a single 0.7-V power supply.
{"title":"A 0.7-V CMOS operational transconductance amplifier with bulk-driven technique","authors":"M. Shen, Yi-Shuan Wu, Guan-Hung Ke, Po-Chiun Huang","doi":"10.1109/SOCDC.2010.5682887","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682887","url":null,"abstract":"This paper presents a two-stage pseudo-differential amplifier. Rail-to-rail operations are achieved by using bulk terminals as the inputs. The positive feedback technique is used to enhance the transconductance with negative conductance. The bulk terminals of all transistors are carefully biased to lower their threshold voltages (Vth) and maximize signal swing. Using a standard 0.18-μm CMOS technology, measurement results demonstrate that gain-bandwidth product is 0.97MHz. The settling time for a 0.7-Vpp step is 2.1/μS. The input referred noise is 0.14mV at 1MHz. All the circuits dissipate 0.107μW under a single 0.7-V power supply.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125553901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682961
Chien-Hung Chen, Jiun-Cheng Ju, Ing-Jer Huang
System-on-a-Chip (SoC) design has become more and more complexly. Because difference functions components or IPs (Intellectual Property) will be integrated within a chip. The challenge of integration is “how to verify on-chip communication properties”. Although traditional simulation-based on-chip bus protocol checking bus signals to obey bus transaction behavior or not, however, they are still lack of a chip-level dynamic verification to assist hardware debugging. We proposed a rule-based synthesizable AMBA AXI protocol checker. The AXI protocol checker contains 44 rules to check on-chip communication properties accuracy. In the verification strategy, we use the Synopsys VIP (Verification IP) to verify AXI protocol checker. In the experimental results, the chip cost of AXI protocol checker is 70.7K gate counts and critical path is 4.13 ns (about 242 MHz) under TSMC 0.18um CMOS 1P6M Technology.
{"title":"A synthesizable AXI protocol checker for SoC integration","authors":"Chien-Hung Chen, Jiun-Cheng Ju, Ing-Jer Huang","doi":"10.1109/SOCDC.2010.5682961","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682961","url":null,"abstract":"System-on-a-Chip (SoC) design has become more and more complexly. Because difference functions components or IPs (Intellectual Property) will be integrated within a chip. The challenge of integration is “how to verify on-chip communication properties”. Although traditional simulation-based on-chip bus protocol checking bus signals to obey bus transaction behavior or not, however, they are still lack of a chip-level dynamic verification to assist hardware debugging. We proposed a rule-based synthesizable AMBA AXI protocol checker. The AXI protocol checker contains 44 rules to check on-chip communication properties accuracy. In the verification strategy, we use the Synopsys VIP (Verification IP) to verify AXI protocol checker. In the experimental results, the chip cost of AXI protocol checker is 70.7K gate counts and critical path is 4.13 ns (about 242 MHz) under TSMC 0.18um CMOS 1P6M Technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134537376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682911
Tae-ho Shin, Hyunok Oh, S. Ha
This paper determines a static scheduling and the minimal size of arc buffers for a given synchronous dataflow (SDF) graph, satisfying a throughput constraint. Unlike the previous work, we assume that the target architecture and the mapping information are given. In addition we consider the unfolding of the SDF graph to improve the throughput. To solve this problem, we adopt answer set programming (ASP) with constraint programming (CP) technique which always finds optimal solutions. The proposed ASP+CP formulation is compact enough to list the scheduling rules in 27 lines and could be applied to a small-but-practical size of coarse-grain SDF graphs successfully.
{"title":"Buffer optimal static scheduling with a throughput constraint for synchronous dataflow applications on multiprocessors","authors":"Tae-ho Shin, Hyunok Oh, S. Ha","doi":"10.1109/SOCDC.2010.5682911","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682911","url":null,"abstract":"This paper determines a static scheduling and the minimal size of arc buffers for a given synchronous dataflow (SDF) graph, satisfying a throughput constraint. Unlike the previous work, we assume that the target architecture and the mapping information are given. In addition we consider the unfolding of the SDF graph to improve the throughput. To solve this problem, we adopt answer set programming (ASP) with constraint programming (CP) technique which always finds optimal solutions. The proposed ASP+CP formulation is compact enough to list the scheduling rules in 27 lines and could be applied to a small-but-practical size of coarse-grain SDF graphs successfully.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132049214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682975
K. Kang, Jongpil Jung, C. Kyung
3D integration increases chip integration density, reduces wire length, wire delay and power consumption on wires. However, increased power density causes increase of temperature, which results in the increase of leakage power consumption and performance degradation. In this paper, we propose a solution to compromise these issues on stacking cache memory on a processor core. Experimental results have shown that the proposed method yields, on the average, 16% performance improvement in terms of instructions per second compared to conventional method. The proposed method also reduces energy consumption by 20% on average, in terms of energy per instruction.
{"title":"Performance maximization of 3D-stacked cache memory on DVFS-enabled processor","authors":"K. Kang, Jongpil Jung, C. Kyung","doi":"10.1109/SOCDC.2010.5682975","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682975","url":null,"abstract":"3D integration increases chip integration density, reduces wire length, wire delay and power consumption on wires. However, increased power density causes increase of temperature, which results in the increase of leakage power consumption and performance degradation. In this paper, we propose a solution to compromise these issues on stacking cache memory on a processor core. Experimental results have shown that the proposed method yields, on the average, 16% performance improvement in terms of instructions per second compared to conventional method. The proposed method also reduces energy consumption by 20% on average, in terms of energy per instruction.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132862804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682921
Yanan Sun, V. Kursun
Carbon nanotube MOSFET (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16nm P-type CN-MOSFETs are explored in this paper. The optimum P-type CN-MOSFET device profiles with different number of tubes are identified with a low substrate bias voltage for high-speed operation. Technology development guidelines are provided for achieving high-speed, area efficient, and manufacturable integrated circuits with carbon nanotube transistors.
{"title":"16nm P-type carbon nanotube MOSFET device profile optimization for high-speed","authors":"Yanan Sun, V. Kursun","doi":"10.1109/SOCDC.2010.5682921","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682921","url":null,"abstract":"Carbon nanotube MOSFET (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16nm P-type CN-MOSFETs are explored in this paper. The optimum P-type CN-MOSFET device profiles with different number of tubes are identified with a low substrate bias voltage for high-speed operation. Technology development guidelines are provided for achieving high-speed, area efficient, and manufacturable integrated circuits with carbon nanotube transistors.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：