Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754761
Tarang Agarwal, Shivank Verma, Ashutosh Gaurh
Wind energy is a clean and renewable source of energy which can be utilized in meeting the increasing demand for electrical energy. International Energy Agency (IEA) has identified it as key element to reduce fossil fuel dependency and helpful tool to combat global warming. The principle of harnessing this energy is by capturing the kinetic energy of wind using wind turbine and further converting it into electrical energy using a generator. Although it seems simple but there are many challenges associated in harnessing this type of energy. This paper highlights the importance of wind energy and also examines the key regulatory challenges & issues that are faced in promoting wind energy power plants including social, environmental and techno-economic impacts. There are many possible solutions for these issues which have been successfully implemented worldwide. However, these solutions will involve high costs making it financially non-viable. Hence, government policies must be explicitly designed to promote wind energy.
{"title":"Issues and challenges of wind energy","authors":"Tarang Agarwal, Shivank Verma, Ashutosh Gaurh","doi":"10.1109/ICEEOT.2016.7754761","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754761","url":null,"abstract":"Wind energy is a clean and renewable source of energy which can be utilized in meeting the increasing demand for electrical energy. International Energy Agency (IEA) has identified it as key element to reduce fossil fuel dependency and helpful tool to combat global warming. The principle of harnessing this energy is by capturing the kinetic energy of wind using wind turbine and further converting it into electrical energy using a generator. Although it seems simple but there are many challenges associated in harnessing this type of energy. This paper highlights the importance of wind energy and also examines the key regulatory challenges & issues that are faced in promoting wind energy power plants including social, environmental and techno-economic impacts. There are many possible solutions for these issues which have been successfully implemented worldwide. However, these solutions will involve high costs making it financially non-viable. Hence, government policies must be explicitly designed to promote wind energy.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127448264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754830
Chakor Atmaram Munjaji, A. V. Tamhane
This paper represents the new topology and hardware modeling of Embedded-Z (EZ) source feed industrial drives and comparative analysis of Z source and EZ-source inverter. In industrial application conventionally there are two converters used for ASD systems i.e. Voltage Source Inverter (VSI) and Current Source Inverter (CSI), but they have a limited output voltage range. Conventional VSI and CSI support only either buck or boost DC-AC power conversion and need a relatively complex modulator. The problems in traditional source converters can be overcome by Z source inverter. In this LC impedance are employed for fast power conversion. Due to requirement of additional LC filter the cost of operation also increases. Therefore, instead of using an external LC filter in Z-source inverters, this paper gives an alternative family of Z-source inverters i.e. EZ-source inverter. In which input DC source has embedding between LC impedance, which perform the current and voltage filtering operation in current type and voltage type EZ source inverter. This paper illustrate the hardware design of EZ source inverter fed induction motor which overcome problems of conventional VSI and CSI inverters. And it gives the smooth speed control of induction motor.
{"title":"An embedded-Z (EZ) source inverter feed based industrial adjustable speed drive system","authors":"Chakor Atmaram Munjaji, A. V. Tamhane","doi":"10.1109/ICEEOT.2016.7754830","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754830","url":null,"abstract":"This paper represents the new topology and hardware modeling of Embedded-Z (EZ) source feed industrial drives and comparative analysis of Z source and EZ-source inverter. In industrial application conventionally there are two converters used for ASD systems i.e. Voltage Source Inverter (VSI) and Current Source Inverter (CSI), but they have a limited output voltage range. Conventional VSI and CSI support only either buck or boost DC-AC power conversion and need a relatively complex modulator. The problems in traditional source converters can be overcome by Z source inverter. In this LC impedance are employed for fast power conversion. Due to requirement of additional LC filter the cost of operation also increases. Therefore, instead of using an external LC filter in Z-source inverters, this paper gives an alternative family of Z-source inverters i.e. EZ-source inverter. In which input DC source has embedding between LC impedance, which perform the current and voltage filtering operation in current type and voltage type EZ source inverter. This paper illustrate the hardware design of EZ source inverter fed induction motor which overcome problems of conventional VSI and CSI inverters. And it gives the smooth speed control of induction motor.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132670522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7755515
Md. Sarwar Kamal, S. Nimmy, Muhammad Iqbal Hossain, N. Dey, A. Ashour, V. Santhi
Exons and Introns are complimentary parts of DNA and RNA. Due to excessive data set in biological science, it is sometimes very expensive and costly to extract meaningful information from such data set. To accelerate efficient and faster exons separation an automated system designed under Neural Skyline Filter(NeuralSF) and Bloom filter. This development allows the comparative analysis on performances among NeuralSF, Bloom Filter and processing without filter. The outcome of the experiments and simulations shows that NeuralSF outperforms other processes in both the cases as number of exons finding and timing. This system may help to reduce the redundant data set from large number of collections. Apart from that it will enable to handle big biological data.
{"title":"ExSep: An exon separation process using Neural Skyline Filter","authors":"Md. Sarwar Kamal, S. Nimmy, Muhammad Iqbal Hossain, N. Dey, A. Ashour, V. Santhi","doi":"10.1109/ICEEOT.2016.7755515","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7755515","url":null,"abstract":"Exons and Introns are complimentary parts of DNA and RNA. Due to excessive data set in biological science, it is sometimes very expensive and costly to extract meaningful information from such data set. To accelerate efficient and faster exons separation an automated system designed under Neural Skyline Filter(NeuralSF) and Bloom filter. This development allows the comparative analysis on performances among NeuralSF, Bloom Filter and processing without filter. The outcome of the experiments and simulations shows that NeuralSF outperforms other processes in both the cases as number of exons finding and timing. This system may help to reduce the redundant data set from large number of collections. Apart from that it will enable to handle big biological data.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116557628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754958
P. M. Drusya, Dr.Vinodkumar Jacob
Addition is the most frequently used operation in many algorithms and applications. The limited precision in the floating point representation requires rounding and basically makes the FP addition sensitive to the operand order. When adding multiple FP operands using a network of 2-input floating point adders, the error in the final result can be significant. Besides, the use of several two input floating point adders on a circuit may result in long delays that could be avoided with an integrated solution. The fused three-term floating-point adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders. Floating-point operations require complex processes such as alignment, normalization and rounding, which increases the area, power consumption and latency. In order to further improve the performance of the three-term adder, several optimization techniques are applied including a new exponent compare and significand alignment, dual-reduction, early normalization, three-input leading zero anticipation, compound addition/rounding and pipelining. The proposed design is implemented for single precision. This paper is trying to demonstrate a novel design for fused floating point three term adder.
{"title":"Area efficient fused floating point three term adder","authors":"P. M. Drusya, Dr.Vinodkumar Jacob","doi":"10.1109/ICEEOT.2016.7754958","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754958","url":null,"abstract":"Addition is the most frequently used operation in many algorithms and applications. The limited precision in the floating point representation requires rounding and basically makes the FP addition sensitive to the operand order. When adding multiple FP operands using a network of 2-input floating point adders, the error in the final result can be significant. Besides, the use of several two input floating point adders on a circuit may result in long delays that could be avoided with an integrated solution. The fused three-term floating-point adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders. Floating-point operations require complex processes such as alignment, normalization and rounding, which increases the area, power consumption and latency. In order to further improve the performance of the three-term adder, several optimization techniques are applied including a new exponent compare and significand alignment, dual-reduction, early normalization, three-input leading zero anticipation, compound addition/rounding and pipelining. The proposed design is implemented for single precision. This paper is trying to demonstrate a novel design for fused floating point three term adder.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116860760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754762
Pappu P. Potdukhe, Vishal D. Jaiswal
In this paper, Carry Select Adder (CSA) architecture are proposed using parallel prefix adder. Instead of using 4-bit Ripple Carry Adder (RCA), parallel prefix adder i.e., 4-bit Brent Kung (BK) adder is used to design CSA. Adders are key element in digital design, performing not only addition operation, but also many other function such as subtraction, multiplication and division. Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time. The time critical application use Brent Kung parallel prefix adder to drive fast results but they lead to increase in area. Carry Select Adder understands between RCA and BK in term of area and delay. Delay of RCA is larger therefore we have replaced it with Brent Kung parallel prefix adder which gives fast result. Power and delay of 4-bit RCA and 4-bit BK adder architecture are calculated at different input voltage. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adder designed using TANNER EDA tool.
本文提出了一种采用并行前缀加法器的进位选择加法器(CSA)结构。采用并行前缀加法器即4位Brent Kung (BK)加法器来设计CSA，而不是使用4位纹波进位加法器(RCA)。加法器是数字设计中的关键元件，它不仅执行加法运算，而且还执行减法、乘法、除法等许多其他功能。纹波进位加法器(RCA)设计最复杂，计算时间较长。时间关键型应用使用Brent Kung并行前缀加法器来驱动快速结果，但导致面积增加。进位选择加法器理解RCA和BK之间的面积和延迟。RCA的延迟较大，因此我们用Brent Kung并行前缀加法器代替它，结果更快。计算了4位RCA和4位BK加法器结构在不同输入电压下的功率和时延。本文介绍了利用TANNER EDA工具设计的4位RCA和4位BK并行前缀加法器的性能比较。
{"title":"Design of high speed carry select adder using brent kung adder","authors":"Pappu P. Potdukhe, Vishal D. Jaiswal","doi":"10.1109/ICEEOT.2016.7754762","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754762","url":null,"abstract":"In this paper, Carry Select Adder (CSA) architecture are proposed using parallel prefix adder. Instead of using 4-bit Ripple Carry Adder (RCA), parallel prefix adder i.e., 4-bit Brent Kung (BK) adder is used to design CSA. Adders are key element in digital design, performing not only addition operation, but also many other function such as subtraction, multiplication and division. Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time. The time critical application use Brent Kung parallel prefix adder to drive fast results but they lead to increase in area. Carry Select Adder understands between RCA and BK in term of area and delay. Delay of RCA is larger therefore we have replaced it with Brent Kung parallel prefix adder which gives fast result. Power and delay of 4-bit RCA and 4-bit BK adder architecture are calculated at different input voltage. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adder designed using TANNER EDA tool.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134335669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754780
Y. Abdalla
This work introduces a new general architecture for an analog to digital converter (ADC) cell. Each ADC cell generates one digital output bit when an analog voltage is applied at its input and produces an analog voltage. This analog voltage is suitable to be used as an input for another ADC cell in order to produce another digital output bit. This new ADC cell architecture is used as a building block to construct n-bit ADC. This n-bit ADC architecture is realized using cascaded n ADC cells and generates parallel digital output. A sample circuit realization is presented for the n-bit ADC and supported by simulation results. The ADC produces clean digital output when simulated at 50 Msample/sec.
{"title":"Building n-bit ADC using n 1-bit new general ADC cell architecture","authors":"Y. Abdalla","doi":"10.1109/ICEEOT.2016.7754780","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754780","url":null,"abstract":"This work introduces a new general architecture for an analog to digital converter (ADC) cell. Each ADC cell generates one digital output bit when an analog voltage is applied at its input and produces an analog voltage. This analog voltage is suitable to be used as an input for another ADC cell in order to produce another digital output bit. This new ADC cell architecture is used as a building block to construct n-bit ADC. This n-bit ADC architecture is realized using cascaded n ADC cells and generates parallel digital output. A sample circuit realization is presented for the n-bit ADC and supported by simulation results. The ADC produces clean digital output when simulated at 50 Msample/sec.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"37 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133345184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754828
R. Sundarrajan, V. Vasudevan, S. Mithya
Cloud computing is the new generation of networks that uses remote servers hosted on the Internet for various uses such as data storage, data management, software usage etc. There are huge amount of resources provided and users can make use of the resources in any way they want to. Today, researchers attempt to find newer ways for Workflow scheduling which could work well in the cloud environment. Workflow scheduling is the most important task in cloud computing field and users have to pay for resources that were used based in a pay-per-usage scheme. Hence Workflow scheduling plays a vital role in getting maximum benefit from the resources that are provided. Another important element to be considered about cloud computing is Load balancing. This controlling of fill assures that every exclusive machine does the very same amount of labour at any immediate of time. To make sure this, we want to recommend on using the idea of fill controlling. Here in this document, we recommend heuristic criteria known as Firefly criteria for effective fill controlling in reasoning processing. This criterion is based on the travel behaviour of the fireflies which go looking for the closest possible maximum alternatives. We employ Firefly algorithm to schedule the jobs and thereby evenly distribute the load and in turn reduce the overall completion time (makespan).
{"title":"Workflow scheduling in cloud computing environment using firefly algorithm","authors":"R. Sundarrajan, V. Vasudevan, S. Mithya","doi":"10.1109/ICEEOT.2016.7754828","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754828","url":null,"abstract":"Cloud computing is the new generation of networks that uses remote servers hosted on the Internet for various uses such as data storage, data management, software usage etc. There are huge amount of resources provided and users can make use of the resources in any way they want to. Today, researchers attempt to find newer ways for Workflow scheduling which could work well in the cloud environment. Workflow scheduling is the most important task in cloud computing field and users have to pay for resources that were used based in a pay-per-usage scheme. Hence Workflow scheduling plays a vital role in getting maximum benefit from the resources that are provided. Another important element to be considered about cloud computing is Load balancing. This controlling of fill assures that every exclusive machine does the very same amount of labour at any immediate of time. To make sure this, we want to recommend on using the idea of fill controlling. Here in this document, we recommend heuristic criteria known as Firefly criteria for effective fill controlling in reasoning processing. This criterion is based on the travel behaviour of the fireflies which go looking for the closest possible maximum alternatives. We employ Firefly algorithm to schedule the jobs and thereby evenly distribute the load and in turn reduce the overall completion time (makespan).","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133775932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754746
V. B. Jagtap, Amol B. Jagdale, P. Kadu
Robots are controlling today's tech-machines scenario and world is ready to accept the new trends the for useful operations. In some industries, a part of work which signify threat and consequently, very strict security rules e.g. some of the work in nuclear plant, where human can't go or its should be avoided as well as such condition such as underwater exploration even on terrain surface too where human can't go on defined destination or somehow it's difficult to reach on defined destination even in surface such as rock, mud, natural water flow, sometimes it's impossible to move for any human Here we come up with the solution for this type of problem to develop a Spider robot i.e. hexapod, so that it will overcome not only above examples but it will be a spider robot base system which will be used anywhere in the similar type of situations. Gravitational Search Algorithm would be utilized for gravity search and to run the same system like insects. We would explore the parameters from Gravity algorithm for stabilization of body of the Spider system We will implement artificial intelligence part into the same system as well as GSA algorithm so that spider's locomotion will be like insects and dew to AI, avoidance of obstacle is possible. The physical spider robot system controlled by arduino technology and motors with fabricated body. For development of spider robot we are in planning to use Insects as source of inspiration because the characteristics from the insects such as gaits based on traveling high speed, avoiding obstacles very fast, ability to easily navigate on uneven terrain surface.
{"title":"Hexapod: A spider for terrain and obstacle shunning by arduino","authors":"V. B. Jagtap, Amol B. Jagdale, P. Kadu","doi":"10.1109/ICEEOT.2016.7754746","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754746","url":null,"abstract":"Robots are controlling today's tech-machines scenario and world is ready to accept the new trends the for useful operations. In some industries, a part of work which signify threat and consequently, very strict security rules e.g. some of the work in nuclear plant, where human can't go or its should be avoided as well as such condition such as underwater exploration even on terrain surface too where human can't go on defined destination or somehow it's difficult to reach on defined destination even in surface such as rock, mud, natural water flow, sometimes it's impossible to move for any human Here we come up with the solution for this type of problem to develop a Spider robot i.e. hexapod, so that it will overcome not only above examples but it will be a spider robot base system which will be used anywhere in the similar type of situations. Gravitational Search Algorithm would be utilized for gravity search and to run the same system like insects. We would explore the parameters from Gravity algorithm for stabilization of body of the Spider system We will implement artificial intelligence part into the same system as well as GSA algorithm so that spider's locomotion will be like insects and dew to AI, avoidance of obstacle is possible. The physical spider robot system controlled by arduino technology and motors with fabricated body. For development of spider robot we are in planning to use Insects as source of inspiration because the characteristics from the insects such as gaits based on traveling high speed, avoiding obstacles very fast, ability to easily navigate on uneven terrain surface.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127764383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7754891
M. Alam, M. R. Khan, R. Arora
Performance of any electrical machine during dynamic and steady state condition is assessed by stability analysis of the machine. Three phase induction motors are widely used for a number of applications in industries because of their reliability and low cost. In close loop control system complex circuits are there so the problem of stability is always arises. In this paper a dynamic model of voltage flux linkage relationship. A linearized model is used to evaluate the control characteristics of the five phase induction motor drive which is based on the Conventional methods such as Root Locus technique, Bode plot, Nyquist plot etc. are used for stability analysis of high phase induction machine. Small perturbations are applied with the model to evaluate the control performance. Voltage current relationship is developed to study the behavior of the machine. In this paper voltage-current model is utilized to determine the stability of the motor under different load conditions. MATLAB codes have been developed to carry out this study.
{"title":"Stability analysis of five phase induction motor drive using conventional methods","authors":"M. Alam, M. R. Khan, R. Arora","doi":"10.1109/ICEEOT.2016.7754891","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7754891","url":null,"abstract":"Performance of any electrical machine during dynamic and steady state condition is assessed by stability analysis of the machine. Three phase induction motors are widely used for a number of applications in industries because of their reliability and low cost. In close loop control system complex circuits are there so the problem of stability is always arises. In this paper a dynamic model of voltage flux linkage relationship. A linearized model is used to evaluate the control characteristics of the five phase induction motor drive which is based on the Conventional methods such as Root Locus technique, Bode plot, Nyquist plot etc. are used for stability analysis of high phase induction machine. Small perturbations are applied with the model to evaluate the control performance. Voltage current relationship is developed to study the behavior of the machine. In this paper voltage-current model is utilized to determine the stability of the motor under different load conditions. MATLAB codes have been developed to carry out this study.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121165085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-03DOI: 10.1109/ICEEOT.2016.7755391
Reetesh V. Golhar, Prasann A. Vyawahare, Pavan H. Borghare, Ashwini Manusmare
In the today's advancing world of technology, Mobile Applications are rapidly growing segment of global mobile market. Mobile applications are developing at a meteor space to give user a rich and fast user experience. This paper involves an application for the android base operating system for an institute which will provide the detail and accurate information about an institute. This application is simple yet powerful which integrated platform that connects all the various departments of an institute like Administration, Account, Students section, student and many more modules. We have seen over the years that the process of notice board, important notification about academics has been carried out manually, this process is not only time consuming but also inefficient. In this app we can get the notification given by the institute via emails.
{"title":"Design and implementation of android base mobile app for an institute","authors":"Reetesh V. Golhar, Prasann A. Vyawahare, Pavan H. Borghare, Ashwini Manusmare","doi":"10.1109/ICEEOT.2016.7755391","DOIUrl":"https://doi.org/10.1109/ICEEOT.2016.7755391","url":null,"abstract":"In the today's advancing world of technology, Mobile Applications are rapidly growing segment of global mobile market. Mobile applications are developing at a meteor space to give user a rich and fast user experience. This paper involves an application for the android base operating system for an institute which will provide the detail and accurate information about an institute. This application is simple yet powerful which integrated platform that connects all the various departments of an institute like Administration, Account, Students section, student and many more modules. We have seen over the years that the process of notice board, important notification about academics has been carried out manually, this process is not only time consuming but also inefficient. In this app we can get the notification given by the institute via emails.","PeriodicalId":383674,"journal":{"name":"2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128621362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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