Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543134
Feng Li, K. Hu, Xu Wang, Houbing Lu, Tianru Geng, Xinxin Wang, Hang Yang, Shengquan Liu, L. Han, G. Jin
We will present the strip readout prototype for ATLAS small-strip Thin Gap Chamber(sTGC) Phase-I Muon trigger upgrade, which named strip Front End Board(sFEB). The prototype includes 8 VMM2 ASICs for strip signal conditioning, a Xilinx Kintex-7 FPGA for VMM2 configuration and events readout, a commercial ethernet chip working at the physical layer. The sFEB prototype is described in details.
{"title":"The study of strip readout prototype for ATLAS Phase-I Muon trigger upgrade","authors":"Feng Li, K. Hu, Xu Wang, Houbing Lu, Tianru Geng, Xinxin Wang, Hang Yang, Shengquan Liu, L. Han, G. Jin","doi":"10.1109/RTC.2016.7543134","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543134","url":null,"abstract":"We will present the strip readout prototype for ATLAS small-strip Thin Gap Chamber(sTGC) Phase-I Muon trigger upgrade, which named strip Front End Board(sFEB). The prototype includes 8 VMM2 ASICs for strip signal conditioning, a Xilinx Kintex-7 FPGA for VMM2 configuration and events readout, a commercial ethernet chip working at the physical layer. The sFEB prototype is described in details.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115054088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543094
Xiaoguang Zhang, You-Qi Nie, H. Liang, Jun Zhang
Random numbers are widely used in many fields. However, most existing random number generators cannot directly generate ideal random bits without post-processing. With the development of generation techniques, the generation rate of raw random data has reached Gbps magnitude and the speed of existing post-processing cannot satisfy the growth of demand. To solve this issue, we propose a concurrent pipeline algorithm based on Toeplitz matrix hashing and implement it in a resource limited field-programmable gate array (FPGA). By taking advantage of the concurrent computation features of FPGA instead of common computer serial computation, the post-processing speed is improved by three orders of magnitudes to above 3.36 Gbps, which is suited for Gbps real time post-processing of raw random numbers. After post-processing, the final extracted random bits can well pass the standard randomness tests. To implement the scheme, a printed circuit board (PCB) is designed for raw data acquisition, real time post-processing and final extracted random data transmission. On the PCB, the random signal is sampled and digitalized as raw random data and then the data are fed into a FPGA for real time post-processing. At the same time, three different transmission interfaces including a small form-factor pluggable (SFP) fiber transceiver, a universal serial bus (USB) 2.0 port and a Gigabit Ethernet port are designed for different scenarios. An optional DDR3 memory module is also provided for testing purpose.
{"title":"FPGA implementation of Toeplitz hashing extractor for real time post-processing of raw random numbers","authors":"Xiaoguang Zhang, You-Qi Nie, H. Liang, Jun Zhang","doi":"10.1109/RTC.2016.7543094","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543094","url":null,"abstract":"Random numbers are widely used in many fields. However, most existing random number generators cannot directly generate ideal random bits without post-processing. With the development of generation techniques, the generation rate of raw random data has reached Gbps magnitude and the speed of existing post-processing cannot satisfy the growth of demand. To solve this issue, we propose a concurrent pipeline algorithm based on Toeplitz matrix hashing and implement it in a resource limited field-programmable gate array (FPGA). By taking advantage of the concurrent computation features of FPGA instead of common computer serial computation, the post-processing speed is improved by three orders of magnitudes to above 3.36 Gbps, which is suited for Gbps real time post-processing of raw random numbers. After post-processing, the final extracted random bits can well pass the standard randomness tests. To implement the scheme, a printed circuit board (PCB) is designed for raw data acquisition, real time post-processing and final extracted random data transmission. On the PCB, the random signal is sampled and digitalized as raw random data and then the data are fed into a FPGA for real time post-processing. At the same time, three different transmission interfaces including a small form-factor pluggable (SFP) fiber transceiver, a universal serial bus (USB) 2.0 port and a Gigabit Ethernet port are designed for different scenarios. An optional DDR3 memory module is also provided for testing purpose.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127038135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543118
P. Wustner, D. Grzonka, Q. Hu, J. Ritman, H. Xu, S. van Waasen
For the KOALA detector a small data acquisition system mainly consisting of VME modules was designed and installed at COSY in Jülich. Main focus was the test of the detector and the DAQ system itself. This paper will show the chosen DAQ concept and describe some difficulties we had to deal with.
{"title":"A small data acquisition system for the KOALA experiment in Jülich","authors":"P. Wustner, D. Grzonka, Q. Hu, J. Ritman, H. Xu, S. van Waasen","doi":"10.1109/RTC.2016.7543118","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543118","url":null,"abstract":"For the KOALA detector a small data acquisition system mainly consisting of VME modules was designed and installed at COSY in Jülich. Main focus was the test of the detector and the DAQ system itself. This paper will show the chosen DAQ concept and describe some difficulties we had to deal with.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127431832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543172
D. Freese, D. Hsu, D. Innes, C. Levin
Positron Emission Tomography (PET) imaging of the breast has the potential to play a role in the detection, diagnosis, staging, guiding surgical resection, and monitoring of therapy for breast cancer. Of these potential roles, producing images at near or real-time is especially important to guide surgical resection and biopsy. This task becomes more difficult in systems with large numbers of detectors and channels. We are constructing a two-panel clinical PET system dedicated to imaging the breast that has 294,912 LYSO crystals read out by 4608 Position-Sensitive Avalanche Photodiodes (PSAPD). The system will read out data using UDP over six gigabit ethernet ports with a maximum predicted data rate of 456MBps for clinical settings. We discuss software considerations for receiving data since UDP does not guarantee transmission. We implement a dual-threaded design for receiving then processing raw data from the system. This model shows 0.037 ± 0.004 % data loss at 240MBps. This rate is the maximum for the current two gigabit ethernet cable setup. We extend and test data loss of the dual-threaded model by adding additional processing of raw data in the second thread. The processing of raw data produces calibrated data with an accurate timestamp, energy, and position in real-time. We show negligible (<; 0.0001 %) loss at or below 60MBps. There, however, is a steady increase in loss with increasing data rate up to 45.9 ± 0.6 % loss at 240MBps. We conclude, that barring upgrades to our current data acquisition computer, we need to produce calibrated data from saved raw data after the scan, which can be done quickly without the constraint of minimizing data loss.
{"title":"Feasibility of software-based real-time calibration of multi-gigabit PET data","authors":"D. Freese, D. Hsu, D. Innes, C. Levin","doi":"10.1109/RTC.2016.7543172","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543172","url":null,"abstract":"Positron Emission Tomography (PET) imaging of the breast has the potential to play a role in the detection, diagnosis, staging, guiding surgical resection, and monitoring of therapy for breast cancer. Of these potential roles, producing images at near or real-time is especially important to guide surgical resection and biopsy. This task becomes more difficult in systems with large numbers of detectors and channels. We are constructing a two-panel clinical PET system dedicated to imaging the breast that has 294,912 LYSO crystals read out by 4608 Position-Sensitive Avalanche Photodiodes (PSAPD). The system will read out data using UDP over six gigabit ethernet ports with a maximum predicted data rate of 456MBps for clinical settings. We discuss software considerations for receiving data since UDP does not guarantee transmission. We implement a dual-threaded design for receiving then processing raw data from the system. This model shows 0.037 ± 0.004 % data loss at 240MBps. This rate is the maximum for the current two gigabit ethernet cable setup. We extend and test data loss of the dual-threaded model by adding additional processing of raw data in the second thread. The processing of raw data produces calibrated data with an accurate timestamp, energy, and position in real-time. We show negligible (<; 0.0001 %) loss at or below 60MBps. There, however, is a steady increase in loss with increasing data rate up to 45.9 ± 0.6 % loss at 240MBps. We conclude, that barring upgrades to our current data acquisition computer, we need to produce calibrated data from saved raw data after the scan, which can be done quickly without the constraint of minimizing data loss.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121970746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543161
J. Collado, J. Blasco, N. Dosme, V. González, X. Grave, N. Karkour, X. Lafay, E. Legay, D. Linget, E. Sanchis
The electronics of AGATA HPGe segmented gamma ray detector faces a new challenge in the search of a bigger integration and cost reduction for the phase 2 of the experiment going beyond 45 crystals. This opportunity can be used to introduce a new architecture based on commercial standards while keeping backward compatibility with current electronics. In this sense, new FPGA devices and fast Ethernet links can be used to ease the preprocessing and control task and allowing for processor farms to distribute the processing load. At the same time, modularity should be a key feature of the design in the aim to make it upgradable in time and technology. This paper presents the design of a new preprocessing and control board that could fulfill with the experiment requirements having in mind that it should not be only a new system but also should serve as replacement of the current electronics. The design is intended to process the data coming from 3 crystals (114 channels) in the same board, with a total aggregate bandwidth of 216 Gpbs using 2 Gbps input optical fiber links in SNAP12 format and with a data readout done through Ethernet fiber optics. It is expected that, with this new system, the level of integration will raise up to 3 times while cost will scale down a 30% with respect to the current electronics.
{"title":"A new preprocessing and control board for the phase 2 electronics of AGATA experiment","authors":"J. Collado, J. Blasco, N. Dosme, V. González, X. Grave, N. Karkour, X. Lafay, E. Legay, D. Linget, E. Sanchis","doi":"10.1109/RTC.2016.7543161","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543161","url":null,"abstract":"The electronics of AGATA HPGe segmented gamma ray detector faces a new challenge in the search of a bigger integration and cost reduction for the phase 2 of the experiment going beyond 45 crystals. This opportunity can be used to introduce a new architecture based on commercial standards while keeping backward compatibility with current electronics. In this sense, new FPGA devices and fast Ethernet links can be used to ease the preprocessing and control task and allowing for processor farms to distribute the processing load. At the same time, modularity should be a key feature of the design in the aim to make it upgradable in time and technology. This paper presents the design of a new preprocessing and control board that could fulfill with the experiment requirements having in mind that it should not be only a new system but also should serve as replacement of the current electronics. The design is intended to process the data coming from 3 crystals (114 channels) in the same board, with a total aggregate bandwidth of 216 Gpbs using 2 Gbps input optical fiber links in SNAP12 format and with a data readout done through Ethernet fiber optics. It is expected that, with this new system, the level of integration will raise up to 3 times while cost will scale down a 30% with respect to the current electronics.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123745439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543175
A. Mielczarek, D. Makowski, P. Perek, A. Napieralski, Przemyslaw Sztoch
The paper presents a versatile solution facilitating calibration of stereoscopic camera rigs for 3D cinematography. Manual calibration of the rig can easily take several hours. The proposed device eases this process by providing the operator with several predefined layouts of the images from the cameras. The Image Analyzer is a compact stand-alone device, designed for the portable 19" racks. Almost all of the video processing is performed on a modern Xilinx FPGA. It is supported by ARM computer to provide control and video streaming over the Ethernet. The article presents its hardware design, as well as FPGA firmware and software architectures.
{"title":"FPGA-based image analyzer for calibration of stereo vision rigs","authors":"A. Mielczarek, D. Makowski, P. Perek, A. Napieralski, Przemyslaw Sztoch","doi":"10.1109/RTC.2016.7543175","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543175","url":null,"abstract":"The paper presents a versatile solution facilitating calibration of stereoscopic camera rigs for 3D cinematography. Manual calibration of the rig can easily take several hours. The proposed device eases this process by providing the operator with several predefined layouts of the images from the cameras. The Image Analyzer is a compact stand-alone device, designed for the portable 19\" racks. Almost all of the video processing is performed on a modern Xilinx FPGA. It is supported by ARM computer to provide control and video streaming over the Ethernet. The article presents its hardware design, as well as FPGA firmware and software architectures.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131219975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543151
D. Li, B. Xiao, J. Xia, Y. Huang, S. L. Chen, K. Wang
The Experimental Advanced Superconductive Tokamak (EAST) Device began operation in 2006. EAST's inner structure is very complicated and contains a lot of subsystems which have a variety of different functions. In order to facilitate the understanding of the device and experimental information and promote the development of the experiment, the virtual EAST system has established an EAST virtual reality scene in which the user can roam and access to information by interacting with the system. However, experiment-related parameter information, diagnostic information and magnetic measurement information are displayed in the form of charts, figures, tables and two dimensional graphics. In order to express the experimental results directly, three-dimensional data visualization results are created using computer graphics technology. Data visualization is the process of visualizing data based on the characteristics of the data, the selection of the appropriate data structure and the proper sequence of visual pipeline. We use the visualization toolkit (VTK) to realize the data visualization in VEAST system and give the detailed steps of data visualization of plasma column, electron cyclotron emission diagnostic and plasma magnetic field. Besides, the general format is defined for the users to organize their data so that they can visualize their data in our system.
{"title":"Design and implementation of EAST data visualization in VEAST system","authors":"D. Li, B. Xiao, J. Xia, Y. Huang, S. L. Chen, K. Wang","doi":"10.1109/RTC.2016.7543151","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543151","url":null,"abstract":"The Experimental Advanced Superconductive Tokamak (EAST) Device began operation in 2006. EAST's inner structure is very complicated and contains a lot of subsystems which have a variety of different functions. In order to facilitate the understanding of the device and experimental information and promote the development of the experiment, the virtual EAST system has established an EAST virtual reality scene in which the user can roam and access to information by interacting with the system. However, experiment-related parameter information, diagnostic information and magnetic measurement information are displayed in the form of charts, figures, tables and two dimensional graphics. In order to express the experimental results directly, three-dimensional data visualization results are created using computer graphics technology. Data visualization is the process of visualizing data based on the characteristics of the data, the selection of the appropriate data structure and the proper sequence of visual pipeline. We use the visualization toolkit (VTK) to realize the data visualization in VEAST system and give the detailed steps of data visualization of plasma column, electron cyclotron emission diagnostic and plasma magnetic field. Besides, the general format is defined for the users to organize their data so that they can visualize their data in our system.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132872649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543148
Y. Mei, Z. Han
The Jiangmen Underground Neutrino Observatory (JUNO) is the second phase of the reactor neutrino experiment. The detector of the experiment was designed as a 20k ton LS with a Inner diameter of 34.5 meters casting material acrylic ball shape. Due to the gigantic shape of the detector there are approximate 10k monitoring point of temperature and humidity. There are about 20k channels of high voltage of array PMT, electric crates as well as the power monitoring points. Since most of the first phase software of the DCS was developed on the framework based on windows, which is limited by operation system upgrade and commercial software, the framework migration and upgrade are necessary for DCS of JUNO. The paper will introduce the upgrade framework of the DCS based on EPICS (Experimental Physics and Industrial Control System) running Linux OS. The implementation of the IOCs of the high-voltage crate and modules, stream device drivers, and the embedded temperature firmware will be presented. The software realization and the remote control method will be presented as well as the development of the GUIs by CSS (Control System Studio). The upgrade framework can be widely used in the project with the similar hardware and software interfaces.
江门地下中微子观测站(JUNO)是反应堆中微子实验的第二阶段。实验的探测器设计为20k吨LS，内径34.5米，铸造材料为丙烯酸球状。由于探测器外形巨大，有大约10k的温度和湿度监测点。阵列PMT、电箱、电力监测点等高压通道约2万余条。由于DCS的第一阶段软件大部分是在基于windows的框架上开发的，受到操作系统升级和商用软件的限制，因此JUNO的DCS需要进行框架的迁移和升级。本文将介绍基于EPICS(实验物理与工业控制系统)在Linux操作系统下的DCS升级框架。介绍了高压板条箱和模块、流设备驱动程序和嵌入式温度固件的IOCs的实现。介绍了该系统的软件实现和远程控制方法，并利用CSS (control System Studio)开发了图形用户界面。该升级框架可广泛应用于软硬件接口相似的项目中。
{"title":"Framework upgrade of the detector control system for JUNO","authors":"Y. Mei, Z. Han","doi":"10.1109/RTC.2016.7543148","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543148","url":null,"abstract":"The Jiangmen Underground Neutrino Observatory (JUNO) is the second phase of the reactor neutrino experiment. The detector of the experiment was designed as a 20k ton LS with a Inner diameter of 34.5 meters casting material acrylic ball shape. Due to the gigantic shape of the detector there are approximate 10k monitoring point of temperature and humidity. There are about 20k channels of high voltage of array PMT, electric crates as well as the power monitoring points. Since most of the first phase software of the DCS was developed on the framework based on windows, which is limited by operation system upgrade and commercial software, the framework migration and upgrade are necessary for DCS of JUNO. The paper will introduce the upgrade framework of the DCS based on EPICS (Experimental Physics and Industrial Control System) running Linux OS. The implementation of the IOCs of the high-voltage crate and modules, stream device drivers, and the embedded temperature firmware will be presented. The software realization and the remote control method will be presented as well as the development of the GUIs by CSS (Control System Studio). The upgrade framework can be widely used in the project with the similar hardware and software interfaces.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134645114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543173
J. Zhao, Z. Liu, W. Gong, F. Deng, L. Cheng, Z. Wu, K. Wang, J. Huang
In the ETOF(End-cap TOF) upgrade of BESIII, MRPC(Multi-gap Resistive Plate Chamber) detectors are used. ETOF is designed with 72 MRPCs. 24 channels signal are read out from each MRPC, in which 6 neighbouring channels OR together in Front-End Electronic(FEE) side. So 288 channel hit signals are sent to ETOF trigger system for trigger logic. The MPRC hit signal is about 30 ns width after FEE. Hit signals are stretched and trigger data are stored by TDPP (Trigger Data Pre-Processor) and then sent to ETOFT (End-cap TOF Trigger) through 10 high speed optical fiber links. Trigger data are aligned and stored in FIFO in ETOFT. Trigger logic in the center FPGA counts hit signals and finds Back to Back (BtB) events and give out three ETOF trigger conditions: NETOF.GE.1, NETOF.GE.2 and ETOF.BB. ETOF trigger conditions are integrated with other detector trigger signals by SIF2(Signal Integrate and Fan-out Version2) to Global Trigger to generate L1. ETOF trigger system was installed on BESIII in Sept.2015 and has run stable for half year.
在BESIII的ETOF(End-cap TOF)升级中，使用了MRPC(Multi-gap resistance Plate Chamber)探测器。ETOF由72个mrpc组成。从每个MRPC读出24通道信号，其中6个相邻通道在前端电子(FEE)侧或在一起。因此288通道命中信号被发送到ETOF触发系统进行触发逻辑。MPRC撞击信号在FEE后约30 ns宽。命中信号被拉伸，触发数据被TDPP(触发数据预处理器)存储，然后通过10条高速光纤链路发送到ETOFT (End-cap TOF trigger)。触发数据被对齐并存储在ETOFT的FIFO中。中央FPGA的触发逻辑对命中信号进行计数并查找Back to Back (BtB)事件，并给出三个ETOF触发条件:NETOF.GE。1, NETOF.GE。2和etf . bb。ETOF触发条件通过SIF2(Signal integration and Fan-out Version2)与其他探测器触发信号集成到Global trigger生成L1。ETOF触发系统于2015年9月安装在BESIII上，并稳定运行了半年。
{"title":"Upgrade of End-cap TOF trigger system on BESIII","authors":"J. Zhao, Z. Liu, W. Gong, F. Deng, L. Cheng, Z. Wu, K. Wang, J. Huang","doi":"10.1109/RTC.2016.7543173","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543173","url":null,"abstract":"In the ETOF(End-cap TOF) upgrade of BESIII, MRPC(Multi-gap Resistive Plate Chamber) detectors are used. ETOF is designed with 72 MRPCs. 24 channels signal are read out from each MRPC, in which 6 neighbouring channels OR together in Front-End Electronic(FEE) side. So 288 channel hit signals are sent to ETOF trigger system for trigger logic. The MPRC hit signal is about 30 ns width after FEE. Hit signals are stretched and trigger data are stored by TDPP (Trigger Data Pre-Processor) and then sent to ETOFT (End-cap TOF Trigger) through 10 high speed optical fiber links. Trigger data are aligned and stored in FIFO in ETOFT. Trigger logic in the center FPGA counts hit signals and finds Back to Back (BtB) events and give out three ETOF trigger conditions: NETOF.GE.1, NETOF.GE.2 and ETOF.BB. ETOF trigger conditions are integrated with other detector trigger signals by SIF2(Signal Integrate and Fan-out Version2) to Global Trigger to generate L1. ETOF trigger system was installed on BESIII in Sept.2015 and has run stable for half year.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-01DOI: 10.1109/RTC.2016.7543157
L. Rota, M. Balzer, M. Caselle, S. Kudella, M. Weber, A. Mozzanica, N. Hiller, M. Nasse, G. Niehues, P. Schönfeldt, C. Gerth, Bernd Steffen, S. Walther, D. Makowski, A. Mielczarek
We developed a fast linear array detector to improve the acquisition rate and the resolution of Electro-Optical Spectral Decoding (EOSD) experimental setups currently installed at several light sources. The system consists of a detector board, an FPGA readout board and a high-throughput data link. InGaAs or Si sensors are used to detect near-infrared (NIR) or visible light. The data acquisition, the operation of the detector board and its synchronization with synchrotron machines are handled by the FPGA. The readout architecture is based on a high-throughput PCI-Express data link. In this paper we describe the system and we present preliminary measurements taken at the ANKA storage ring. A line-rate of 2.7 Mlps (lines per second) has been demonstrated.
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