Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543082
Xinzhe Wang, Futian Liang, P. Miao, Yi Qian, G. Jin
Random number generators are wildly used in many applications in a diverse set of areas ranging from statistics to cryptography. Pseudo random number generators (PRNGs) are quite satisfactory for most applications. However, for cryptography and security applications, true random number generators (TRNGs) are required for the unpredictability. High density and high data output rate are as important as the quality of the TRNG in the nowadays true random number required devices and instruments. We present the design and the primary test results of our 10-Gbps TRNG, which is named TRNG2015, in the paper. The entropy source of the TRNG2015 is the jitter of ring oscillators. The TRNG2015 is fabricated in a 130nm CMOS process and assembled in a 6mm × 6 mm QFN48 package. It has one LVDS clock input and ten LVDS random data outputs. The output data rate depends on the input clock which is up to 1 GHz, and the output data rate is up to 1 Gbps per channel and up to 10 Gbps in total.
{"title":"10-Gbps true random number generator accomplished in ASIC","authors":"Xinzhe Wang, Futian Liang, P. Miao, Yi Qian, G. Jin","doi":"10.1109/RTC.2016.7543082","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543082","url":null,"abstract":"Random number generators are wildly used in many applications in a diverse set of areas ranging from statistics to cryptography. Pseudo random number generators (PRNGs) are quite satisfactory for most applications. However, for cryptography and security applications, true random number generators (TRNGs) are required for the unpredictability. High density and high data output rate are as important as the quality of the TRNG in the nowadays true random number required devices and instruments. We present the design and the primary test results of our 10-Gbps TRNG, which is named TRNG2015, in the paper. The entropy source of the TRNG2015 is the jitter of ring oscillators. The TRNG2015 is fabricated in a 130nm CMOS process and assembled in a 6mm × 6 mm QFN48 package. It has one LVDS clock input and ten LVDS random data outputs. The output data rate depends on the input clock which is up to 1 GHz, and the output data rate is up to 1 Gbps per channel and up to 10 Gbps in total.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115348122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543133
Si Ma, Fei Li, W. Shen, Z. Ning, Yu-guang Xie, K. Zhu
A beam detection system has been developed for tracks, position and energy calibration of electron, which consists of a TPC detector1, a PDD2, a detector to be calibrated and a silicon-based energy detector. Its data acquisition(DAQ) system aims to realize readout, event built, online monitoring and reconstructing for 511 channels of TPC and 200 channels of PDD in 100Hz trigger rate provided by the electron beam device. In our design, the DAQ system is a small scale distributed system, which has been divided into two parts. One part communicates with readout electronics, based on client-server architecture, we call it ROS(Readout System). The other part receives sub-event from ROSs, merges and processes event data in each DAQ component based on DAQ-Middleware software framework, we named it ODP(Online Data Processing). The two parts running independently, which improves the performance, scalability and maintainability of the whole system. This paper will present the system and software architecture design, implement of the DAQ software and evaluation of its ROS performance.
研制了一种用于电子轨迹、位置和能量标定的束流探测系统，该系统由TPC探测器1、PDD2、待标定探测器和硅基能量探测器组成。其数据采集(DAQ)系统旨在实现电子束器件提供的100Hz触发率下511路TPC和200路PDD的读出、事件构建、在线监测和重构。在我们的设计中，DAQ系统是一个小规模的分布式系统，分为两部分。其中一部分与读出电子器件通信，基于客户机-服务器架构，我们称之为ROS(读出系统)。另一部分是接收来自ROSs的子事件，并基于DAQ- middleware软件框架对各个DAQ组件中的事件数据进行合并和处理，我们将其命名为ODP(Online data Processing)。两部分独立运行，提高了整个系统的性能、可扩展性和可维护性。本文将介绍系统和软件的架构设计、DAQ软件的实现以及对其ROS性能的评价。
{"title":"The DAQ system for a beam detection system based on TPC-THGEM","authors":"Si Ma, Fei Li, W. Shen, Z. Ning, Yu-guang Xie, K. Zhu","doi":"10.1109/RTC.2016.7543133","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543133","url":null,"abstract":"A beam detection system has been developed for tracks, position and energy calibration of electron, which consists of a TPC detector1, a PDD2, a detector to be calibrated and a silicon-based energy detector. Its data acquisition(DAQ) system aims to realize readout, event built, online monitoring and reconstructing for 511 channels of TPC and 200 channels of PDD in 100Hz trigger rate provided by the electron beam device. In our design, the DAQ system is a small scale distributed system, which has been divided into two parts. One part communicates with readout electronics, based on client-server architecture, we call it ROS(Readout System). The other part receives sub-event from ROSs, merges and processes event data in each DAQ component based on DAQ-Middleware software framework, we named it ODP(Online Data Processing). The two parts running independently, which improves the performance, scalability and maintainability of the whole system. This paper will present the system and software architecture design, implement of the DAQ software and evaluation of its ROS performance.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114169891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543123
L. Cardoso, C. Gaspar, J. Barbosa, F. Alessio
LHCb is one of the 4 experiments at the LHC accelerator at CERN. During the upgrade phase of the experiment, several new electronic boards and Front End chips that perform the data acquisition for the experiment will be added by the different sub-detectors. These new devices will be controlled and monitored via a system composed of GigaBit Transceiver (GBT) chips that manage the bi-directional slow control traffic to the Slow Control Adapter(s) (SCA) chips. The SCA chips provide several user buses to interface the new electronics devices. These devices will need to be integrated in the Experiment Control System (ECS) that drives LHCb. A set of tools was developed that provide an easy integration of the control and monitoring of the devices in the ECS. A server (GbtServ) provides the low level communication layer with the devices via the several user buses in the SCA chip and exposes an interface for control to the experiment SCADA (WinCC OA), the fwGbt component provides the interface between the SCADA and the GbtServ and the fwHw component, a tool that allows the abstraction of the devices models into the ECS. Using a Graphical User Interfaces or XML files describing the structure and registers of the devices, it creates the necessary model of the hardware as a data structure in the SCADA. It allows then the control and monitoring of the defined registers using their name, without the need to know the details of the hardware behind. The fwHw tool also provides the facility of defining and applying recipes - named sets of configurations which can be used to easily configure the hardware according to specific needs.
{"title":"Controlling DAQ electronics using a SCADA framework","authors":"L. Cardoso, C. Gaspar, J. Barbosa, F. Alessio","doi":"10.1109/RTC.2016.7543123","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543123","url":null,"abstract":"LHCb is one of the 4 experiments at the LHC accelerator at CERN. During the upgrade phase of the experiment, several new electronic boards and Front End chips that perform the data acquisition for the experiment will be added by the different sub-detectors. These new devices will be controlled and monitored via a system composed of GigaBit Transceiver (GBT) chips that manage the bi-directional slow control traffic to the Slow Control Adapter(s) (SCA) chips. The SCA chips provide several user buses to interface the new electronics devices. These devices will need to be integrated in the Experiment Control System (ECS) that drives LHCb. A set of tools was developed that provide an easy integration of the control and monitoring of the devices in the ECS. A server (GbtServ) provides the low level communication layer with the devices via the several user buses in the SCA chip and exposes an interface for control to the experiment SCADA (WinCC OA), the fwGbt component provides the interface between the SCADA and the GbtServ and the fwHw component, a tool that allows the abstraction of the devices models into the ECS. Using a Graphical User Interfaces or XML files describing the structure and registers of the devices, it creates the necessary model of the hardware as a data structure in the SCADA. It allows then the control and monitoring of the defined registers using their name, without the need to know the details of the hardware behind. The fwHw tool also provides the facility of defining and applying recipes - named sets of configurations which can be used to easily configure the hardware according to specific needs.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114464759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543144
Weihao Wu, M. Begel, Hucheng Chen, Kai Chen, F. Lanni, H. Takai, Shaochun Tang
The Global Feature Extractor (gFEX) is one of several modules in the LHC Run-3 upgrade of the Level 1 Calorimeter (L1Calo) trigger system in the ATLAS experiment. It is a single Advanced Telecommunications Computing Architecture (ATCA) module for large-area jet identification with three Xilinx Virtex UltraScale FPGAs for data processing and a system-on-chip (SoC) FPGA for control and monitoring. A pre-prototype board has been designed to verify all functionalities, which includes one Xilinx Virtex-7 FPGA, one Zynq FPGA, several MiniPODs, MicroPODs, DDR3 SDRAM and other components. The performance of the pre-prototype has been tested and evaluated. As a major challenge, the high-speed links in FPGAs are stable at 12.8 Gb/s with Bit Error Ratio (BER) <; 10-15 (no error detected). The low-latency parallel GPIO (General Purpose I/O) buses for communication between FPGAs are stable at 960 Mb/s. The peripheral components of Zynq FPGA like DDRs, UART, SPI flashes, Ethernet and so on, have also been verified. The test results of the pre-prototype board validate the gFEX technologies and architecture. Now the prototype board with three UltraScale FPGAs is on the way.
{"title":"The development of the global feature extractor for the LHC Run-3 upgrade of the L1 calorimeter trigger system","authors":"Weihao Wu, M. Begel, Hucheng Chen, Kai Chen, F. Lanni, H. Takai, Shaochun Tang","doi":"10.1109/RTC.2016.7543144","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543144","url":null,"abstract":"The Global Feature Extractor (gFEX) is one of several modules in the LHC Run-3 upgrade of the Level 1 Calorimeter (L1Calo) trigger system in the ATLAS experiment. It is a single Advanced Telecommunications Computing Architecture (ATCA) module for large-area jet identification with three Xilinx Virtex UltraScale FPGAs for data processing and a system-on-chip (SoC) FPGA for control and monitoring. A pre-prototype board has been designed to verify all functionalities, which includes one Xilinx Virtex-7 FPGA, one Zynq FPGA, several MiniPODs, MicroPODs, DDR3 SDRAM and other components. The performance of the pre-prototype has been tested and evaluated. As a major challenge, the high-speed links in FPGAs are stable at 12.8 Gb/s with Bit Error Ratio (BER) <; 10-15 (no error detected). The low-latency parallel GPIO (General Purpose I/O) buses for communication between FPGAs are stable at 960 Mb/s. The peripheral components of Zynq FPGA like DDRs, UART, SPI flashes, Ethernet and so on, have also been verified. The test results of the pre-prototype board validate the gFEX technologies and architecture. Now the prototype board with three UltraScale FPGAs is on the way.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114757614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543136
D. Cesini, A. Ferraro, A. Falabella, F. Giacomini, M. Manzali, U. Marconi, N. Neufeld, S. Valat, B. Voneki
The LHCb Collaboration is preparing a major upgrade of the detector and the Data Acquisition (DAQ) to be installed during the LHC-LS2. The new Event Builder computing farm for the DAQ requires about 500 nodes, and have to be capable of transporting order of 32 Tbps. The requested performance can possibly be achieved using high-bandwidth data-centre switches and commodity hardware. Several studies are ongoing to evaluate and compare network and hardware technologies, with the aim of optimising the performance and also the purchase and maintenance costs of the system. We are investigating if x86 low-power architectures can achieve equivalent performance as traditional servers when used for multi gigabit DAQ. In this talk we introduce an Event Builder implementation based on InfiniBand network and show preliminary tests with this network technology on x86 low-power architectures, such as Intel Atom C2750 and Intel Xeon D-1540, comparing measured bandwidth and power consumption.
LHC-LS2项目正在准备对探测器和数据采集(DAQ)进行重大升级。用于DAQ的新的Event Builder计算场需要大约500个节点，并且必须能够传输32tbps的数量级。所要求的性能可以使用高带宽数据中心交换机和商用硬件来实现。目前正在进行几项研究，以评估和比较网络和硬件技术，目的是优化性能以及系统的购买和维护成本。我们正在研究x86低功耗架构在用于多千兆数据采集时能否达到与传统服务器相当的性能。在这次演讲中，我们介绍了一个基于InfiniBand网络的Event Builder实现，并展示了该网络技术在x86低功耗架构(如Intel Atom C2750和Intel Xeon D-1540)上的初步测试，比较了测量的带宽和功耗。
{"title":"High throughput data acquisition with InfiniBand on x86 low-power architectures for the LHCb upgrade","authors":"D. Cesini, A. Ferraro, A. Falabella, F. Giacomini, M. Manzali, U. Marconi, N. Neufeld, S. Valat, B. Voneki","doi":"10.1109/RTC.2016.7543136","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543136","url":null,"abstract":"The LHCb Collaboration is preparing a major upgrade of the detector and the Data Acquisition (DAQ) to be installed during the LHC-LS2. The new Event Builder computing farm for the DAQ requires about 500 nodes, and have to be capable of transporting order of 32 Tbps. The requested performance can possibly be achieved using high-bandwidth data-centre switches and commodity hardware. Several studies are ongoing to evaluate and compare network and hardware technologies, with the aim of optimising the performance and also the purchase and maintenance costs of the system. We are investigating if x86 low-power architectures can achieve equivalent performance as traditional servers when used for multi gigabit DAQ. In this talk we introduce an Event Builder implementation based on InfiniBand network and show preliminary tests with this network technology on x86 low-power architectures, such as Intel Atom C2750 and Intel Xeon D-1540, comparing measured bandwidth and power consumption.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127574570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543071
Dong-xu Yang, Hongfei Zhang, Yi Feng, Q. Tang, Teng-Yun Chen, Jian Wang
An energy measurement method used for high-frequency narrow laser pulses based on a high performance field-programmable gate array (FPGA) chip is introduced in this paper. There are two parts contained in this method: signal conditioning and data processing. The signal conditioning part will transform the incident narrow laser pulse to electrical signal which has an appropriate width and the amplitude is linear to the energy of the laser pulse. The electrical signal will be digitalized by a high speed ADC and input to the FPGA chip in the data processing part. The amplitude of the electrical signal will be obtained by real-time calculations in the FPGA. The test result shows that the method is suitable for the laser pulse with FWHW low level with 200ps and frequency up to 20MHz.
{"title":"An energy measurement method of high-frequency narrow laser pulse based on FPGA","authors":"Dong-xu Yang, Hongfei Zhang, Yi Feng, Q. Tang, Teng-Yun Chen, Jian Wang","doi":"10.1109/RTC.2016.7543071","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543071","url":null,"abstract":"An energy measurement method used for high-frequency narrow laser pulses based on a high performance field-programmable gate array (FPGA) chip is introduced in this paper. There are two parts contained in this method: signal conditioning and data processing. The signal conditioning part will transform the incident narrow laser pulse to electrical signal which has an appropriate width and the amplitude is linear to the energy of the laser pulse. The electrical signal will be digitalized by a high speed ADC and input to the FPGA chip in the data processing part. The amplitude of the electrical signal will be obtained by real-time calculations in the FPGA. The test result shows that the method is suitable for the laser pulse with FWHW low level with 200ps and frequency up to 20MHz.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126590647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543140
B. Shaw, P. Amaudruz, D. Bishop
New data acquisition electronics is being developed at TRIUMF for the Gamma-Ray Infrastructure For Fundamental Investigations of Nuclei (GRIFFIN) spectrometer. Current FPGA capabilities have allowed opportunities for providing a more user friendly, web-based, hardware control interface that can be used without requiring additional custom software. Several software and firmware components are being developed, including a real-time waveform viewer, parameter control and read back, diagnostic counters, and a template-based configuration system utilizing MIDAS, and Javascript. This paper discusses the various protocols that were investigated, the benefits and challenges of the choices made, and the details of the interface implementations.
{"title":"Web-based parameter control and real-time waveform display for the GRIFFIN experiment","authors":"B. Shaw, P. Amaudruz, D. Bishop","doi":"10.1109/RTC.2016.7543140","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543140","url":null,"abstract":"New data acquisition electronics is being developed at TRIUMF for the Gamma-Ray Infrastructure For Fundamental Investigations of Nuclei (GRIFFIN) spectrometer. Current FPGA capabilities have allowed opportunities for providing a more user friendly, web-based, hardware control interface that can be used without requiring additional custom software. Several software and firmware components are being developed, including a real-time waveform viewer, parameter control and read back, diagnostic counters, and a template-based configuration system utilizing MIDAS, and Javascript. This paper discusses the various protocols that were investigated, the benefits and challenges of the choices made, and the details of the interface implementations.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543171
M. Tétrault, A. Therrien, W. Lemaire, R. Fontaine, J. Pratte
Radiation detection used in positron emission tomography (PET) exploit the timing information to remove background noise and refine the position measurement through time-of-flight (TOF) information. In PET, very fine time resolution (in the order of 10 ps FWHM) would not only improve contrast in the image, but would also enable real-time image reconstruction without iterative or back-projected algorithms. The current performance limitations will be pushed off through the optimization of faster light emission mechanisms (prompts photons), after which the burden of timing resolution will fall to the readout optoelectronics. Digital SPAD arrays offer compelling possibilities to minimize timing jitter in these future detector systems such per-cell timestamps granularity and per-cell configuration parameters, providing a highly flexible signal processing environment. However, processing hundreds of timestamps per detection event places a toll on the real-time processing, which increases rapidly with embedded channel count. Furthermore, if the processing is sent to an external device such as an FPGA, the bandwidth and related power requirements also increase. The simulation flow presented here offers perspectives on how many time to digital converters (TDC) would be required to reach the 10 ps FWHM CTR range for PET. Using this information, designers can estimate the compromises between timing performance, bandwidth requirements, data transmission, power consumption and real-time dataflow processing in the DAQ at the chip and system level. With a standard 1.1 × 1.1 × 3.0 mm3 LYSO scintillator, the coincidence timing resolution (CTR) changed by less than 3% within the range of 4 to 484 implemented TDCs for evaluated system conditions. On the other hand, an LYSO-based photonic crystal with 2.5% prompt emission rate needs a detector with at least 36 TDCs to reach within 3% CTR of an equivalent array with one TDC per SPAD. This gives significant insights on how this change of crystal material will affect system real time requirements for future detector design.
{"title":"Digital SPAD scintillation detector simulation flow to evaluate and minimize real-time requirements","authors":"M. Tétrault, A. Therrien, W. Lemaire, R. Fontaine, J. Pratte","doi":"10.1109/RTC.2016.7543171","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543171","url":null,"abstract":"Radiation detection used in positron emission tomography (PET) exploit the timing information to remove background noise and refine the position measurement through time-of-flight (TOF) information. In PET, very fine time resolution (in the order of 10 ps FWHM) would not only improve contrast in the image, but would also enable real-time image reconstruction without iterative or back-projected algorithms. The current performance limitations will be pushed off through the optimization of faster light emission mechanisms (prompts photons), after which the burden of timing resolution will fall to the readout optoelectronics. Digital SPAD arrays offer compelling possibilities to minimize timing jitter in these future detector systems such per-cell timestamps granularity and per-cell configuration parameters, providing a highly flexible signal processing environment. However, processing hundreds of timestamps per detection event places a toll on the real-time processing, which increases rapidly with embedded channel count. Furthermore, if the processing is sent to an external device such as an FPGA, the bandwidth and related power requirements also increase. The simulation flow presented here offers perspectives on how many time to digital converters (TDC) would be required to reach the 10 ps FWHM CTR range for PET. Using this information, designers can estimate the compromises between timing performance, bandwidth requirements, data transmission, power consumption and real-time dataflow processing in the DAQ at the chip and system level. With a standard 1.1 × 1.1 × 3.0 mm3 LYSO scintillator, the coincidence timing resolution (CTR) changed by less than 3% within the range of 4 to 484 implemented TDCs for evaluated system conditions. On the other hand, an LYSO-based photonic crystal with 2.5% prompt emission rate needs a detector with at least 36 TDCs to reach within 3% CTR of an equivalent array with one TDC per SPAD. This gives significant insights on how this change of crystal material will affect system real time requirements for future detector design.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132178470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543076
Lei Zhao, C. Ma, S. Chu, Xingshun Gao, Zouyi Jiang, R. Dong, Shubin Liu, Q. An
In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the major detectors. The WCDA electronics are responsible for the readout of 3600 Photomultiplier Tubes (PMTs), and a total of 400 Front End Electronics (FEE) modules are required. The main challenges in the WCDA readout electronics design include: precise time and charge measurement over a large dynamic input amplitude range (1 Photo Electron (P.E.) ~ 4000 P.E.), high quality of clock distribution and automatic clock phase compensation, and high speed data transfer due to the requirement of “triggerless” architecture. In this paper, we present the prototype design of the readout electronics for the LHAASO WCDA. We also conducted tests on the prototype electronics to evaluate the performance. The results indicate that a charge resolution better than 15%@ 1 P.E. and 2%@ 4000 P.E., and a time resolution better than 0.3 ns RMS are successfully achieved over the whole dynamic range, beyond the application requirement.
{"title":"Design of the readout electronics prototype for LHAASO WCDA","authors":"Lei Zhao, C. Ma, S. Chu, Xingshun Gao, Zouyi Jiang, R. Dong, Shubin Liu, Q. An","doi":"10.1109/RTC.2016.7543076","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543076","url":null,"abstract":"In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the major detectors. The WCDA electronics are responsible for the readout of 3600 Photomultiplier Tubes (PMTs), and a total of 400 Front End Electronics (FEE) modules are required. The main challenges in the WCDA readout electronics design include: precise time and charge measurement over a large dynamic input amplitude range (1 Photo Electron (P.E.) ~ 4000 P.E.), high quality of clock distribution and automatic clock phase compensation, and high speed data transfer due to the requirement of “triggerless” architecture. In this paper, we present the prototype design of the readout electronics for the LHAASO WCDA. We also conducted tests on the prototype electronics to evaluate the performance. The results indicate that a charge resolution better than 15%@ 1 P.E. and 2%@ 4000 P.E., and a time resolution better than 0.3 ns RMS are successfully achieved over the whole dynamic range, beyond the application requirement.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114226861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-06DOI: 10.1109/RTC.2016.7543087
Jian Zhuang, Jia-jie Li, Yichao Ma, Yi Liang, Haofu Liu, L. Hu, Lijiang Liao
In Chinese Spallation Neutron Source (CSNS), proton beam is used to strike metal tungsten target, and the target generates high flux neutron for experiments on neutron instruments. The precise time and beam current of proton hitting the target need to be measured. Then this time is broadcasted to the target station and the neutron instruments to work collaboratively. To calculate the neutron energy, this time is also needed to measuring the neutron time of flight(TOF). The beam current of proton is sent to physical analysis software to normalize neutron flux. The time synchronization technology based on WhiteRabbit, can achieve high precision time synchronization with a large range of nodes. A synchronization system is built in CSNS with WR nodes composed of signal acquisition, time synchronization and data packing-sending. The proton beam current is monitored with timestamp, for physical analysis software. And more, in CSNS, a real-time control system based on WR is built for measuring the proton hit time, broadcasting to the electronics system of detectors, and calculating TOF of neutrons.
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