Pub Date : 2016-05-31DOI: 10.1109/RTC.2016.7543113
F. Carrió
The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment at the Large Hadron Collider (LHC). The upgraded High Luminosity LHC will deliver five times the current nominal instantaneous luminosity. The ATLAS Phase II upgrade will upgrade the readout electronics of the TileCal for the HL-LHC. The majority of the front- and back-end electronics will be redesigned with a new readout strategy. In the upgraded readout architecture for Phase II, the frontend electronics consist of the Front-End Boards, Main Boards and the Daughter Boards. The Main Board digitizes the analog signals coming from the Front-End Boards (FEBs) connected to the PhotoMultiplier Tubes (PMTs), provides integrated data for minimum bias monitoring and includes electronics for PMT calibration. Three different FEB options with different signal acquisition strategies are under study: new 3-in-1 cards, QIE chip and FATALIC chip. The Daughter Board receives and distributes Detector Control System commands, clock and timing commands to the rest of the elements of the front-end electronics, as well as collects and transmits the digitized data to the backend electronics at the LHC frequency (~25 ns). In the back-end electronics, the TileCal PreProcessor (TilePPr) receives and stores the digitized data from the Daughter Boards in pipeline memories to cope with the latencies and rates specified in the new ATLAS DAQ architecture. The TilePPr interfaces between the data acquisition, trigger and control systems and the front-end electronics. In addition, the TilePPr distributes the clock and timing commands to the frontend electronics for synchronization with the LHC clock.
{"title":"Timing distribution and data flow for the ATLAS Tile Calorimeter Phase II upgrade","authors":"F. Carrió","doi":"10.1109/RTC.2016.7543113","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543113","url":null,"abstract":"The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment at the Large Hadron Collider (LHC). The upgraded High Luminosity LHC will deliver five times the current nominal instantaneous luminosity. The ATLAS Phase II upgrade will upgrade the readout electronics of the TileCal for the HL-LHC. The majority of the front- and back-end electronics will be redesigned with a new readout strategy. In the upgraded readout architecture for Phase II, the frontend electronics consist of the Front-End Boards, Main Boards and the Daughter Boards. The Main Board digitizes the analog signals coming from the Front-End Boards (FEBs) connected to the PhotoMultiplier Tubes (PMTs), provides integrated data for minimum bias monitoring and includes electronics for PMT calibration. Three different FEB options with different signal acquisition strategies are under study: new 3-in-1 cards, QIE chip and FATALIC chip. The Daughter Board receives and distributes Detector Control System commands, clock and timing commands to the rest of the elements of the front-end electronics, as well as collects and transmits the digitized data to the backend electronics at the LHC frequency (~25 ns). In the back-end electronics, the TileCal PreProcessor (TilePPr) receives and stores the digitized data from the Daughter Boards in pipeline memories to cope with the latencies and rates specified in the new ATLAS DAQ architecture. The TilePPr interfaces between the data acquisition, trigger and control systems and the front-end electronics. In addition, the TilePPr distributes the clock and timing commands to the frontend electronics for synchronization with the LHC clock.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129341991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-31DOI: 10.1109/RTC.2016.7543142
J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, M. Donszelmann, D. Francis, B. Gorini, D. Guest, F. Lanni, G. Miotto, L. Levinson, J. Narevicius, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, W. Wu, J. Zhang
From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.
{"title":"FELIX: The new approach for interfacing to front-end electronics for the ATLAS experiment","authors":"J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, M. Donszelmann, D. Francis, B. Gorini, D. Guest, F. Lanni, G. Miotto, L. Levinson, J. Narevicius, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, W. Wu, J. Zhang","doi":"10.1109/RTC.2016.7543142","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543142","url":null,"abstract":"From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"963 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123066261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543095
E. Barrera, M. Ruiz, A. Bustos, M. Afif, B. Radle, J. Fernández-Hernando, I. Prieto, R. Pedica, Miguel J. Barcala, J. Oller, R. Castro
Interlocks are the instrumented functions of ITER that protect the machine against failures of the plant system components or incorrect machine operation. Regarding I&C, the Interlock Control System (ICS) ensures that no failure of the conventional ITER controls can lead to a serious damage of the machine integrity or availability. The ICS is in charge of the supervision and control of all the ITER components involved in the instrumented protection of the Tokamak and its auxiliary systems. It is constituted by the Central Interlock System (CIS), the different Plant Interlock Systems (PIS) and its networks. The ICS does not include the sensors and actuators of the plant systems but it is in charge of their control. The ITER interlock system shall be designed, built and operated according to the highest quality standards. The international standard IEC-61508 has been chosen as the reference. In both CIS and PIS cases two main architectures are used: a slow architecture, for those functions with response time requirements slower than 100ms (300 ms for central interlock functions), based on PLC technologies, and a fast architecture, based on FPGA technologies, for the functions with faster requirement times. The proposed design for fast PIS is based on the use of RIO (Reconfigurable Input/Output) technology from National Instruments (compactRIO platform). In order to provide a high integrity solution, a FMEDA (Failure Modes Effects and Diagnostics Analysis) has been conducted to analyze the components behavior. According to the output of the FMEDA a set of diagnostics has been defined and additional redundancy was added to the architecture to improve the integrity figures. The defined configuration has been called the “double-decker solution”, with two chassis running in parallel, communicated between them using a synchronous high speed serial line, and using redundant modules to implement the input and output measurement/excitations and redundant analog and digital modules to implement the diagnostics of these input/output modules. The integrity figures for the “double decker” solution are obtained from the classification of the failure rates, obtaining for the different configurations a SFF (safe failure fraction) of 85% and a FPH (Probability of dangerous Failure per Hour) of less than 1E-07. The FPGA design includes all the hardware to support the data acquisition from the input modules, the implementation of the diagnostics functionalities for analog and digital modules, the voting schema and the activation/deactivation of digital outputs. The platform includes an external test platform, also based on compactRIO technology, to perform the validation of the system and to register the performance of the different interlock functions implemented. The response times obtained for the TTL input to TTL output interlock function ranges from 5μs to 20μs; for the analog input to TTL output the response time is in the range of 41 μs to 90 μs, and for inter
{"title":"Implementation of ITER fast plant interlock system using FPGAs with cRIO","authors":"E. Barrera, M. Ruiz, A. Bustos, M. Afif, B. Radle, J. Fernández-Hernando, I. Prieto, R. Pedica, Miguel J. Barcala, J. Oller, R. Castro","doi":"10.1109/rtc.2016.7543095","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543095","url":null,"abstract":"Interlocks are the instrumented functions of ITER that protect the machine against failures of the plant system components or incorrect machine operation. Regarding I&C, the Interlock Control System (ICS) ensures that no failure of the conventional ITER controls can lead to a serious damage of the machine integrity or availability. The ICS is in charge of the supervision and control of all the ITER components involved in the instrumented protection of the Tokamak and its auxiliary systems. It is constituted by the Central Interlock System (CIS), the different Plant Interlock Systems (PIS) and its networks. The ICS does not include the sensors and actuators of the plant systems but it is in charge of their control. The ITER interlock system shall be designed, built and operated according to the highest quality standards. The international standard IEC-61508 has been chosen as the reference. In both CIS and PIS cases two main architectures are used: a slow architecture, for those functions with response time requirements slower than 100ms (300 ms for central interlock functions), based on PLC technologies, and a fast architecture, based on FPGA technologies, for the functions with faster requirement times. The proposed design for fast PIS is based on the use of RIO (Reconfigurable Input/Output) technology from National Instruments (compactRIO platform). In order to provide a high integrity solution, a FMEDA (Failure Modes Effects and Diagnostics Analysis) has been conducted to analyze the components behavior. According to the output of the FMEDA a set of diagnostics has been defined and additional redundancy was added to the architecture to improve the integrity figures. The defined configuration has been called the “double-decker solution”, with two chassis running in parallel, communicated between them using a synchronous high speed serial line, and using redundant modules to implement the input and output measurement/excitations and redundant analog and digital modules to implement the diagnostics of these input/output modules. The integrity figures for the “double decker” solution are obtained from the classification of the failure rates, obtaining for the different configurations a SFF (safe failure fraction) of 85% and a FPH (Probability of dangerous Failure per Hour) of less than 1E-07. The FPGA design includes all the hardware to support the data acquisition from the input modules, the implementation of the diagnostics functionalities for analog and digital modules, the voting schema and the activation/deactivation of digital outputs. The platform includes an external test platform, also based on compactRIO technology, to perform the validation of the system and to register the performance of the different interlock functions implemented. The response times obtained for the TTL input to TTL output interlock function ranges from 5μs to 20μs; for the analog input to TTL output the response time is in the range of 41 μs to 90 μs, and for inter","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"1164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114162500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543124
S. Baymani, Konstantinos Alexopoulos, S. Valat
Exploring RapidIO RapidIO (http://rapidio.org/) technology is a packet-switched high-performance fabric, which has been under active development since 1997. The technology is used in all 4G/LTE basestations worldwide. RapidIO is often used in embedded systems that require high reliability, low latency and deterministic operations in a heterogeneous environment. RapidIO has several offloading features in hardware, therefore relieving the CPUs from time-consuming work. Most importantly, it allows for remote DMA and thus zero-copy data-transfer. In addition it lends itself readily to integration with FPGAs. In this paper we investigate RapidO as a technology for high-speed DAQ networks, in particular the DAQ system of an LHC experiment. We present measurements using a generic, multi-protocol event-building emulation tool which was developed for the LHCb experiment. Event building using a local area network, such as the one foreseen for the future LHCb DAQ puts heavy requirements on the underlying network as all data sources from the collider will want to send to the same destinations at the same time. This leads to an instantaneous overcommitment of the output buffers of the switches. We will present results from implementing a event building cluster based on RapidIO interconnect, focusing on the bandwidth capabilities of the technology as well as the scalability.
{"title":"Exploring RapidIO technology within a DAQ system event building network","authors":"S. Baymani, Konstantinos Alexopoulos, S. Valat","doi":"10.1109/rtc.2016.7543124","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543124","url":null,"abstract":"Exploring RapidIO RapidIO (http://rapidio.org/) technology is a packet-switched high-performance fabric, which has been under active development since 1997. The technology is used in all 4G/LTE basestations worldwide. RapidIO is often used in embedded systems that require high reliability, low latency and deterministic operations in a heterogeneous environment. RapidIO has several offloading features in hardware, therefore relieving the CPUs from time-consuming work. Most importantly, it allows for remote DMA and thus zero-copy data-transfer. In addition it lends itself readily to integration with FPGAs. In this paper we investigate RapidO as a technology for high-speed DAQ networks, in particular the DAQ system of an LHC experiment. We present measurements using a generic, multi-protocol event-building emulation tool which was developed for the LHCb experiment. Event building using a local area network, such as the one foreseen for the future LHCb DAQ puts heavy requirements on the underlying network as all data sources from the collider will want to send to the same destinations at the same time. This leads to an instantaneous overcommitment of the output buffers of the switches. We will present results from implementing a event building cluster based on RapidIO interconnect, focusing on the bandwidth capabilities of the technology as well as the scalability.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134361948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543115
J. Schacht, H. Laqua, I. Müller, J. Skodzik, H. Puttnies
The superconducting stellarator Wendelstein 7-X (W7-X) started plasma operation in December 2015 after the commissioning phase of the machine. The main technical and diagnostic systems have been finished successfully. The timing system is an important part of the Control, Data Acquisition and Communication systems of W7-X. The first version of the TTE-system is in routine operation at the W7-X experiment. Since 2004 it has been used for the commissioning of the control and data acquisition components, and also for the stellarator WEGA. The commission of the second version of the TTE-system is still on going and planned to be finished end of 2016. Starting with an introduction of the TTE-system of W7-X, this contribution describes the main features of the TTE-system. The actual state of the TTE-system and the network topology will be presented. Finally, first experiences of W7-X operational phase OP1.1 related to the TTE-system are discussed.
{"title":"The trigger-time-event-system for Wendelstein 7-X: Overview and first operational experiences","authors":"J. Schacht, H. Laqua, I. Müller, J. Skodzik, H. Puttnies","doi":"10.1109/rtc.2016.7543115","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543115","url":null,"abstract":"The superconducting stellarator Wendelstein 7-X (W7-X) started plasma operation in December 2015 after the commissioning phase of the machine. The main technical and diagnostic systems have been finished successfully. The timing system is an important part of the Control, Data Acquisition and Communication systems of W7-X. The first version of the TTE-system is in routine operation at the W7-X experiment. Since 2004 it has been used for the commissioning of the control and data acquisition components, and also for the stellarator WEGA. The commission of the second version of the TTE-system is still on going and planned to be finished end of 2016. Starting with an introduction of the TTE-system of W7-X, this contribution describes the main features of the TTE-system. The actual state of the TTE-system and the network topology will be presented. Finally, first experiences of W7-X operational phase OP1.1 related to the TTE-system are discussed.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"24 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127227910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543135
Y. Bai, D. Gaisbauer, S. Huber, I. Konorov, D. Levit, D. Steffen, S. Paul
In this paper we present the FPGA-based framework IFDAQ which is used for the development of the data acquisition systems for detectors in high energy physics. The framework supports Xilinx FPGA and provides a collection of the IP cores written in VHDL which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of the SERDES-based TDC channels, an interface to a multi-channel 80MS/s 10-bit ADC, data transmission and synchronization protocol between FPGA, event builder and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front-end and data concentrator. This modular design also helps to scale and adapt the data acquisition system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the straw drift chambers and the electromagnetic calorimeters of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this upgrade.
{"title":"Intelligent FPGA data acquisition framework","authors":"Y. Bai, D. Gaisbauer, S. Huber, I. Konorov, D. Levit, D. Steffen, S. Paul","doi":"10.1109/rtc.2016.7543135","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543135","url":null,"abstract":"In this paper we present the FPGA-based framework IFDAQ which is used for the development of the data acquisition systems for detectors in high energy physics. The framework supports Xilinx FPGA and provides a collection of the IP cores written in VHDL which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of the SERDES-based TDC channels, an interface to a multi-channel 80MS/s 10-bit ADC, data transmission and synchronization protocol between FPGA, event builder and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front-end and data concentrator. This modular design also helps to scale and adapt the data acquisition system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the straw drift chambers and the electromagnetic calorimeters of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this upgrade.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"9 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114129162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543121
P. Antonioli, C. Baldanza, D. Falchieri, F. Giorgi, A. Mati?, C. Tintori
This paper shows the results achieved with a test board that has been designed as a first step towards the upgrade of the ALICE TOF readout electronics foreseen in 2019-2020 at CERN LHC. The board features a radiation hard SERDES ASIC from CERN, named GBTx, which, in connection to the rad-hard optical transceiver VTRx, implements the newer generation optical links for many detector readout systems at LHC. The heart of the board is a commercial FPGA from Microsemi, an Igloo2 device, which is expected to cope with a moderately hostile radiation environment, as a total dose of 0.13 krads is expected in 10 years of beam collisions. The board has been extensively tested with a special attention devoted to the Igloo2-GBTx devices: a measurement of the optical link BER is presented, together with the test results obtained connecting the board to a PC using the standard ALICE DAQ board (C-RORC).
{"title":"Design and test of a GBTx based board for the upgrade of the ALICE TOF readout electronics","authors":"P. Antonioli, C. Baldanza, D. Falchieri, F. Giorgi, A. Mati?, C. Tintori","doi":"10.1109/rtc.2016.7543121","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543121","url":null,"abstract":"This paper shows the results achieved with a test board that has been designed as a first step towards the upgrade of the ALICE TOF readout electronics foreseen in 2019-2020 at CERN LHC. The board features a radiation hard SERDES ASIC from CERN, named GBTx, which, in connection to the rad-hard optical transceiver VTRx, implements the newer generation optical links for many detector readout systems at LHC. The heart of the board is a commercial FPGA from Microsemi, an Igloo2 device, which is expected to cope with a moderately hostile radiation environment, as a total dose of 0.13 krads is expected in 10 years of beam collisions. The board has been extensively tested with a special attention devoted to the Igloo2-GBTx devices: a measurement of the optical link BER is presented, together with the test results obtained connecting the board to a PC using the standard ALICE DAQ board (C-RORC).","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131029843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543080
R. Giordano, V. Izzo, S. Perrella, A. Aloisio
High-speed analog-to-digital converters (ADCs) are key components in a huge variety of systems, including trigger and data acquisition (TDAQ) systems of Nuclear and Sub-nuclear Physics experiments. Over the last decades, the sample rate and dynamic range of high-speed ADCs underwent a continuous growth and it required the development of suitable interface protocols, such as the new JESD204B serial interface protocol. In this work, we present an original JESD204B-compliant architecture we designed, which is able to operate an analog-to-digital converter in a remote fashion. Our design includes a deterministic-latency high-speed serial link, which is the only connection between the local and remote logic of the architecture and which preserves the deterministic timing features of the protocol. By means of our solution it is possible to read data out of several converters, even remote to each other, and keep them operating synchronously. Our link also supports forward error correction (FEC) capabilities, in the view of the operation in radiation areas (e.g. on-detector in TDAQ systems). We discuss an implementation of our concept in a latest generation FPGA (Xilinx Kintex-7 325T), its logic footprint, frequency performance and power consumption. We present measurements of the timing jitter and latency stability of JESD204B timing-critical signals forwarded over the link. We also describe a demo application of our architecture.
{"title":"A JESD204B-compliant architecture for remote and deterministic-latency operation","authors":"R. Giordano, V. Izzo, S. Perrella, A. Aloisio","doi":"10.1109/rtc.2016.7543080","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543080","url":null,"abstract":"High-speed analog-to-digital converters (ADCs) are key components in a huge variety of systems, including trigger and data acquisition (TDAQ) systems of Nuclear and Sub-nuclear Physics experiments. Over the last decades, the sample rate and dynamic range of high-speed ADCs underwent a continuous growth and it required the development of suitable interface protocols, such as the new JESD204B serial interface protocol. In this work, we present an original JESD204B-compliant architecture we designed, which is able to operate an analog-to-digital converter in a remote fashion. Our design includes a deterministic-latency high-speed serial link, which is the only connection between the local and remote logic of the architecture and which preserves the deterministic timing features of the protocol. By means of our solution it is possible to read data out of several converters, even remote to each other, and keep them operating synchronously. Our link also supports forward error correction (FEC) capabilities, in the view of the operation in radiation areas (e.g. on-detector in TDAQ systems). We discuss an implementation of our concept in a latest generation FPGA (Xilinx Kintex-7 325T), its logic footprint, frequency performance and power consumption. We present measurements of the timing jitter and latency stability of JESD204B timing-critical signals forwarded over the link. We also describe a demo application of our architecture.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124854900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543149
T. Kozak, Bernd Steffen, S. Pfeiffer, S. Schreiber
Bunch charge variations in Free Electron Lasers such as the Free Electron Laser in Hamburg (FLASH) or the European X-Ray Free Electron Laser (E-XFEL) impacts the longitudinal phase space distribution of the electrons resulting in different bunch peak currents, pulse duration and pulse shapes. The electron bunches are generated by short ultraviolet laser pulses impinging onto a photocathode inside a radio frequency (RF) accelerating cavity. At FLASH, bursts of bunches up to 800 pulses with an intra train repetition rate of 1 MHz are used and even higher repetition rates for the E-XFEL (up to 4.5 Mhz) are planned. Charge variations along these bunch-trains can be caused by variations of the laser pulse energies, instabilities of the accelerating fields in the RF cavity and time dependent effects in the photoemission process. To improve the intra bunch-train charge flatness and to compensate train-to-train fluctuations a dedicated digital control system, based on the Micro Telecommunication Computing Architecture (MicroTCA.4) standard, was designed, implemented and successfully tested at the FLASH. The system consists of a bunch charge detection module which analyzes data from toroid system and provides the input signal for the controller which drives a fast UV-Pockels Cell installed in the optical path of the photo-cathode laser. The Pockels cell alters the laser polarization and thus the transmission through a polarizer. The modulation of UV laser pulse energy with an iterative learning feed-forward minimizing the repetitive errors from bunch-train to bunch-train and a fast feedback algorithm implemented in a Field Programmable Gate Array (FPGA) allows for fast tuning of bunch charge inside the bunch-train. In this paper a detailed description of the system and first measurement results are presented.
{"title":"Fast intra bunch train charge feedback for FELs based on photo injector laser pulse modulation","authors":"T. Kozak, Bernd Steffen, S. Pfeiffer, S. Schreiber","doi":"10.1109/rtc.2016.7543149","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543149","url":null,"abstract":"Bunch charge variations in Free Electron Lasers such as the Free Electron Laser in Hamburg (FLASH) or the European X-Ray Free Electron Laser (E-XFEL) impacts the longitudinal phase space distribution of the electrons resulting in different bunch peak currents, pulse duration and pulse shapes. The electron bunches are generated by short ultraviolet laser pulses impinging onto a photocathode inside a radio frequency (RF) accelerating cavity. At FLASH, bursts of bunches up to 800 pulses with an intra train repetition rate of 1 MHz are used and even higher repetition rates for the E-XFEL (up to 4.5 Mhz) are planned. Charge variations along these bunch-trains can be caused by variations of the laser pulse energies, instabilities of the accelerating fields in the RF cavity and time dependent effects in the photoemission process. To improve the intra bunch-train charge flatness and to compensate train-to-train fluctuations a dedicated digital control system, based on the Micro Telecommunication Computing Architecture (MicroTCA.4) standard, was designed, implemented and successfully tested at the FLASH. The system consists of a bunch charge detection module which analyzes data from toroid system and provides the input signal for the controller which drives a fast UV-Pockels Cell installed in the optical path of the photo-cathode laser. The Pockels cell alters the laser polarization and thus the transmission through a polarizer. The modulation of UV laser pulse energy with an iterative learning feed-forward minimizing the repetitive errors from bunch-train to bunch-train and a fast feedback algorithm implemented in a Field Programmable Gate Array (FPGA) allows for fast tuning of bunch charge inside the bunch-train. In this paper a detailed description of the system and first measurement results are presented.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134174380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/rtc.2016.7543119
L. Meder, D. Emschermann, J. Fruhauf, W. Muller, J. Becker
In beam test setups detector elements together with a readout composed of Frontend Electronics and usually an Field-Programmable Gate Array (FPGA) based layer are being analyzed. The frontend electronics is in this scenario often directly connected to both the detector and the FPGA layer what in many cases requires sharing the ground potentials of these layers. This setup can become problematic if parts of the detector need to be operated at different high-voltage potentials, since all of the FPGA boards need to receive a common clock and timing reference in order to synchronize the readout. Thus, for the context of the CBM experiment a versatile Timing Synchronizer system was designed providing galvanically isolated timing distribution links.
{"title":"A timing synchronizer system for beam test setups requiring galvanic isolation","authors":"L. Meder, D. Emschermann, J. Fruhauf, W. Muller, J. Becker","doi":"10.1109/rtc.2016.7543119","DOIUrl":"https://doi.org/10.1109/rtc.2016.7543119","url":null,"abstract":"In beam test setups detector elements together with a readout composed of Frontend Electronics and usually an Field-Programmable Gate Array (FPGA) based layer are being analyzed. The frontend electronics is in this scenario often directly connected to both the detector and the FPGA layer what in many cases requires sharing the ground potentials of these layers. This setup can become problematic if parts of the detector need to be operated at different high-voltage potentials, since all of the FPGA boards need to receive a common clock and timing reference in order to synchronize the readout. Thus, for the context of the CBM experiment a versatile Timing Synchronizer system was designed providing galvanically isolated timing distribution links.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114402868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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