Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992602
Aalok U Gaitonde, Amulya Nimmagadda, A. Marconnet
Although Lithium ion batteries offer numerous advantages (e.g. energy density, efficiency, etc.) over other types of batteries, recent accidents involving consumer electronics have necessitated a deeper understanding of the thermal behavior of these batteries. Thermal transport across the multilayer stacks that form prismatic and spiral-wound batteries generally hinders heat removal from the system. In cylindrical batteries, most commonly found in laptops, electric vehicles and power banks, heat must conduct to the metallic shell through many layers of the anode-separator-cathode structure, which is of low effective thermal conductivity. This work presents thermal conductance and thermal conductivity measurements of dry 18650 cells using infrared microscopy. Two-dimensional temperature maps are captured and are averaged in the direction normal to the heat flow for analysis of the one-dimensional temperature profiles. Interfacial temperature jumps indicate thermal resistances and can be separated from the thermal gradients due to conduction within a single material. We measure both cross-plane thermal conductivity of the battery stack and interfacial thermal conductance. Interfacial thermal conductance and the thermal conductivity in active batteries is expected to be higher, due to the presence of a liquid electrolyte. This work demonstrates that the low cross plane thermal conductivity of the plastic separator material is one of the limiting factors in heat dissipation.
{"title":"Experimental characterization of thermal conductance across the separator-shell interface in dry cylindrical lithium ion batteries","authors":"Aalok U Gaitonde, Amulya Nimmagadda, A. Marconnet","doi":"10.1109/ITHERM.2017.7992602","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992602","url":null,"abstract":"Although Lithium ion batteries offer numerous advantages (e.g. energy density, efficiency, etc.) over other types of batteries, recent accidents involving consumer electronics have necessitated a deeper understanding of the thermal behavior of these batteries. Thermal transport across the multilayer stacks that form prismatic and spiral-wound batteries generally hinders heat removal from the system. In cylindrical batteries, most commonly found in laptops, electric vehicles and power banks, heat must conduct to the metallic shell through many layers of the anode-separator-cathode structure, which is of low effective thermal conductivity. This work presents thermal conductance and thermal conductivity measurements of dry 18650 cells using infrared microscopy. Two-dimensional temperature maps are captured and are averaged in the direction normal to the heat flow for analysis of the one-dimensional temperature profiles. Interfacial temperature jumps indicate thermal resistances and can be separated from the thermal gradients due to conduction within a single material. We measure both cross-plane thermal conductivity of the battery stack and interfacial thermal conductance. Interfacial thermal conductance and the thermal conductivity in active batteries is expected to be higher, due to the presence of a liquid electrolyte. This work demonstrates that the low cross plane thermal conductivity of the plastic separator material is one of the limiting factors in heat dissipation.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114722100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992508
P. Parida, A. Sridhar, Augusto J. Vega, M. Schultz, M. Gaynes, Ozgur Ozsun, Gerard McVicker, T. Brunschwiler, A. Buyuktosunoglu, T. Chainer
Chip embedded two phase evaporative cooling is an enabling technology to provide intra-chip cooling of high power chips and interlayer cooling for 3D chip stacks. Utilizing an interconnect-compatible dielectric fluid provides a cooling solution compatible with chip to chip interconnects for future high power 3D chip stacks. However, lack of high fidelity and computationally manageable conjugate thermal models limits the development of this technology. To address that, a thermal model for fast and accurate prediction of thermal and electrical behavior of an embedded two-phase liquid cooled micro-processor module is described in this paper. This model consists of a state-of-the-art conjugate heat transfer model for two-phase flow boiling through chip embedded micron-scale channels and a physics-based empirically tuned electrical model of the microprocessor. Extensive model validation using data from several experiments was performed to quantify the accuracy of this model under different operating conditions (including various chip operating frequencies and coolant mass flow rates). Results showed that this model can predict the electrical behavior as well as two-phase flow and heat transfer characteristics with very good accuracy. Overall, the chip junction temperature predictions were within two degrees of the experimental data and the temperature-dependent chip power predictions were within 10%.
{"title":"Thermal model for embedded two-phase liquid cooled microprocessor","authors":"P. Parida, A. Sridhar, Augusto J. Vega, M. Schultz, M. Gaynes, Ozgur Ozsun, Gerard McVicker, T. Brunschwiler, A. Buyuktosunoglu, T. Chainer","doi":"10.1109/ITHERM.2017.7992508","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992508","url":null,"abstract":"Chip embedded two phase evaporative cooling is an enabling technology to provide intra-chip cooling of high power chips and interlayer cooling for 3D chip stacks. Utilizing an interconnect-compatible dielectric fluid provides a cooling solution compatible with chip to chip interconnects for future high power 3D chip stacks. However, lack of high fidelity and computationally manageable conjugate thermal models limits the development of this technology. To address that, a thermal model for fast and accurate prediction of thermal and electrical behavior of an embedded two-phase liquid cooled micro-processor module is described in this paper. This model consists of a state-of-the-art conjugate heat transfer model for two-phase flow boiling through chip embedded micron-scale channels and a physics-based empirically tuned electrical model of the microprocessor. Extensive model validation using data from several experiments was performed to quantify the accuracy of this model under different operating conditions (including various chip operating frequencies and coolant mass flow rates). Results showed that this model can predict the electrical behavior as well as two-phase flow and heat transfer characteristics with very good accuracy. Overall, the chip junction temperature predictions were within two degrees of the experimental data and the temperature-dependent chip power predictions were within 10%.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130023772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992586
M. Gupta, A. Vallabhaneni, Satish Kumar
A physics-based reduced order self-consistent electro-thermal model is presented for AlGaN/GaN HEMT to obtain current and temperature in the device. The model uses device geometry and temperature dependent material properties as input parameters and requires minimal fitting parameters. The model has the ability to include the effects of self-heating, thermal spreading, and thermal cross-talk in a multi-finger device. The model is validated with the experimental data and physical simulations for single and multi-finger cases and provides reasonably accurate predictions for both current and temperature in the device. The model can capture the spatial variation of temperature profile across the device and therefore, can predict the finger-level variation in the drain current in a multi-finger HEMT. The model is computationally efficient, and can be used for design and analysis of GaN based devices and systems.
{"title":"A self-consistent reduced order model for current and temperature in GaN HEMTs","authors":"M. Gupta, A. Vallabhaneni, Satish Kumar","doi":"10.1109/ITHERM.2017.7992586","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992586","url":null,"abstract":"A physics-based reduced order self-consistent electro-thermal model is presented for AlGaN/GaN HEMT to obtain current and temperature in the device. The model uses device geometry and temperature dependent material properties as input parameters and requires minimal fitting parameters. The model has the ability to include the effects of self-heating, thermal spreading, and thermal cross-talk in a multi-finger device. The model is validated with the experimental data and physical simulations for single and multi-finger cases and provides reasonably accurate predictions for both current and temperature in the device. The model can capture the spatial variation of temperature profile across the device and therefore, can predict the finger-level variation in the drain current in a multi-finger HEMT. The model is computationally efficient, and can be used for design and analysis of GaN based devices and systems.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134498975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992646
Chun-Pei Chen, G. Subbarayan, Hung-Yun Lin, S. Gurrum
The fabrication process-induced variation in the yield strength of metal films in microelectronic devices critically impacts the reliability of inter-layer dielectric (ILD) stacks. However, estimation of the yield strength of buried films in multilayer stacks remains a significant challenge. The indentation technique, whose advantage is that it does not require a freestanding film, has been widely used to characterize thin films, but traditional analyses mostly focus on characterizing the top layer of the stack. In this paper, we propose an optimization-based inverse finite element analysis (IFEA) technique to estimate the yield strength of a buried metal film in the ILD stack. The technique is demonstrated by estimating the yield strength of the buried aluminum film in a TEOS-Al-Si3N4-Si stack. We carryout the optimization from multiple initial points in the parameter space to ensure the uniqueness of the estimated yield strength.
{"title":"Estimating the yield strength of metal films in ILD stacks using optimization-based inverse finite element analysis","authors":"Chun-Pei Chen, G. Subbarayan, Hung-Yun Lin, S. Gurrum","doi":"10.1109/ITHERM.2017.7992646","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992646","url":null,"abstract":"The fabrication process-induced variation in the yield strength of metal films in microelectronic devices critically impacts the reliability of inter-layer dielectric (ILD) stacks. However, estimation of the yield strength of buried films in multilayer stacks remains a significant challenge. The indentation technique, whose advantage is that it does not require a freestanding film, has been widely used to characterize thin films, but traditional analyses mostly focus on characterizing the top layer of the stack. In this paper, we propose an optimization-based inverse finite element analysis (IFEA) technique to estimate the yield strength of a buried metal film in the ILD stack. The technique is demonstrated by estimating the yield strength of the buried aluminum film in a TEOS-Al-Si3N4-Si stack. We carryout the optimization from multiple initial points in the parameter space to ensure the uniqueness of the estimated yield strength.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133890114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992622
Q. Nguyen, J. Roberts, J. Suhling, R. Jaeger
Electronic packages absorb moisture when exposed to uncontrolled humid conditions during manufacturing processes and service life. At high temperatures, the effects of moisture absorption on electronic packages become even more significant. A number of failure modes are caused by moisture effects such as popcorn cracking, delamination, and electrochemical migration. In this study, the effects of moisture on die stresses in Plastic Ball Grid Array (PBGA) packages have been explored. The tested PBGAs were 27 × 27 mm in size, with 416 solder balls on a 1 mm pitch. They were assembled with silicon die of two different die sizes were used (5 × 5 and 10 × 10 mm). The complete state of stress at various points on the die surface was obtained using stress sensing test chip technology. The samples were exposed to a harsh high temperature and high humidity environment (MSL 1–85 °C, 85% RH) for various time durations, and allowed to adsorb moisture. The variations of the die stresses at several locations were characterized as a function of time during the hygrothermal exposure. The weight of each sample was also measured during the moisture exposure to quantify the uptake of water. After the moisture exposure, the samples were then baked in thermal chamber (85 °C) to check the reversibility of moisture absorption and die stress variation. In addition to the experiments at the package level, an investigation on the moisture properties of the BT substrate and mold compound in the PBGA was completed. The moisture properties (diffusivity D, saturated concentration Csat, and coefficient of moisture expansion β) of each material were experimentally obtained. Unlike the traditional method of measuring the out-of-plane coefficient of moisture expansion (CME) using a TMA instrument, a new approach was used in this work to characterize the in-plane CMEs using a nanoindentation system. Finally, a finite element numerical simulation was performed, and the predictions were correlated with the experimental results. The measured moisture properties obtained earlier were used in the model. Unlike conventional approaches using the moisture-thermal analogy, an advanced approach was implemented to perform coupled multi-physics simulations of the moisture diffusion process without the limitations that can be seen in conventional method. Good agreements between numerical predictions and experimental results were observed. Both the measurements and numerical simulations provided a valuable insight on moisture induced failure phenomena in Plastic Ball Grid Array Packages.
{"title":"A study of moisture and thermally induced die stresses in plastic ball grid array packages","authors":"Q. Nguyen, J. Roberts, J. Suhling, R. Jaeger","doi":"10.1109/ITHERM.2017.7992622","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992622","url":null,"abstract":"Electronic packages absorb moisture when exposed to uncontrolled humid conditions during manufacturing processes and service life. At high temperatures, the effects of moisture absorption on electronic packages become even more significant. A number of failure modes are caused by moisture effects such as popcorn cracking, delamination, and electrochemical migration. In this study, the effects of moisture on die stresses in Plastic Ball Grid Array (PBGA) packages have been explored. The tested PBGAs were 27 × 27 mm in size, with 416 solder balls on a 1 mm pitch. They were assembled with silicon die of two different die sizes were used (5 × 5 and 10 × 10 mm). The complete state of stress at various points on the die surface was obtained using stress sensing test chip technology. The samples were exposed to a harsh high temperature and high humidity environment (MSL 1–85 °C, 85% RH) for various time durations, and allowed to adsorb moisture. The variations of the die stresses at several locations were characterized as a function of time during the hygrothermal exposure. The weight of each sample was also measured during the moisture exposure to quantify the uptake of water. After the moisture exposure, the samples were then baked in thermal chamber (85 °C) to check the reversibility of moisture absorption and die stress variation. In addition to the experiments at the package level, an investigation on the moisture properties of the BT substrate and mold compound in the PBGA was completed. The moisture properties (diffusivity D, saturated concentration Csat, and coefficient of moisture expansion β) of each material were experimentally obtained. Unlike the traditional method of measuring the out-of-plane coefficient of moisture expansion (CME) using a TMA instrument, a new approach was used in this work to characterize the in-plane CMEs using a nanoindentation system. Finally, a finite element numerical simulation was performed, and the predictions were correlated with the experimental results. The measured moisture properties obtained earlier were used in the model. Unlike conventional approaches using the moisture-thermal analogy, an advanced approach was implemented to perform coupled multi-physics simulations of the moisture diffusion process without the limitations that can be seen in conventional method. Good agreements between numerical predictions and experimental results were observed. Both the measurements and numerical simulations provided a valuable insight on moisture induced failure phenomena in Plastic Ball Grid Array Packages.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131539107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992638
R. Ghaffarian
This paper presents the reliability of a plastic land grid array (LGA) with 1156 pads, 1.0-mm pitch, and the reliability of a flip-chip ball grid array (FCBGA) with 1924 balls, 1-mm pitch, assembled with tin-lead solder onto printed circuit boards (PCBs). Surface finishes for PCBs were electroless nickel electroless palladium immersion gold (ENEPIG) and tin-lead hot air solder level (HASL). The LGA assemblies were first subjected to 200 thermal cycles (−55°C to 125°C) and then to 324 hours of aging at +125°C. The FCBGA assemblies were subjected to 200 thermal shock cycles (TS) in the range of −65°C to +150°C. Test results presented include daisy-chain resistances, SEM/X-section images, and dye and pry destructive failure analyses for HASL and ENEPIG surface finishes.
{"title":"Reliability of large I/O LGA and FCBGA assemblies under thermal shock/cycles and aging: Comparison of HASL and ENEPIG PCB finish","authors":"R. Ghaffarian","doi":"10.1109/ITHERM.2017.7992638","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992638","url":null,"abstract":"This paper presents the reliability of a plastic land grid array (LGA) with 1156 pads, 1.0-mm pitch, and the reliability of a flip-chip ball grid array (FCBGA) with 1924 balls, 1-mm pitch, assembled with tin-lead solder onto printed circuit boards (PCBs). Surface finishes for PCBs were electroless nickel electroless palladium immersion gold (ENEPIG) and tin-lead hot air solder level (HASL). The LGA assemblies were first subjected to 200 thermal cycles (−55°C to 125°C) and then to 324 hours of aging at +125°C. The FCBGA assemblies were subjected to 200 thermal shock cycles (TS) in the range of −65°C to +150°C. Test results presented include daisy-chain resistances, SEM/X-section images, and dye and pry destructive failure analyses for HASL and ENEPIG surface finishes.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131796516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992507
Youmin Yu, Nader Nikfar
Substrate is a critical component in an IC package. The thermal properties of a substrate must be accurately evaluated when developing IC packages. The very heterogeneous nature of substrate, consisting of highly conductive metal layers, thermally poor dielectric, layer-by-layer stack up, and vias between metal layers, poses many challenges to such thermal evaluations. This paper reports a novel approach to accurately compute effective thermal properties of a substrate. The approach starts with a component-level 1-D heat conduction model in each direction of a substrate with detailed design. The effective thermal conductivities of the substrate are extracted by applying Fourier's law and principle of thermal resistance network to the 1-D heat conduction problem. The extracted effective thermal conductivities are then verified at package-level simulations. A same package, first with the detailed substrate and then with the compact substrate (built with the extracted effective thermal conductivities), is simulated in turn for their respective junction-to-board thermal resistances. The agreement of the two thermal resistances immediately indicates the accuracy of the effective thermal conductivities. The approach has been validated and shows good accuracy. The proposed approach can be confidently adopted to predict thermal performance of laminate packages.
{"title":"A novel approach to extract effective thermal properties of substrate in IC packages","authors":"Youmin Yu, Nader Nikfar","doi":"10.1109/ITHERM.2017.7992507","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992507","url":null,"abstract":"Substrate is a critical component in an IC package. The thermal properties of a substrate must be accurately evaluated when developing IC packages. The very heterogeneous nature of substrate, consisting of highly conductive metal layers, thermally poor dielectric, layer-by-layer stack up, and vias between metal layers, poses many challenges to such thermal evaluations. This paper reports a novel approach to accurately compute effective thermal properties of a substrate. The approach starts with a component-level 1-D heat conduction model in each direction of a substrate with detailed design. The effective thermal conductivities of the substrate are extracted by applying Fourier's law and principle of thermal resistance network to the 1-D heat conduction problem. The extracted effective thermal conductivities are then verified at package-level simulations. A same package, first with the detailed substrate and then with the compact substrate (built with the extracted effective thermal conductivities), is simulated in turn for their respective junction-to-board thermal resistances. The agreement of the two thermal resistances immediately indicates the accuracy of the effective thermal conductivities. The approach has been validated and shows good accuracy. The proposed approach can be confidently adopted to predict thermal performance of laminate packages.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132283806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992631
P. Lall, D. Zhang, J. Suhling, David Locker
The effect of aging on mechanical properties of SAC 305 at low strain rate has been investigated. For high strain rate constitutive mechanical behavior, a number of researchers relied on Split Hopkinson Pressure bar and the strain rate range is from 500/s to 3000/s. However, for typical drop and shock, the strain rate range is from 1/s to 100/s. There is a general scarcity of data for solder materials in this strain rate range. Therefore knowing the mechanical properties of lead free solder at this high strain rate range is very important for design and optimization of package reliability. It is possible that failure may happen at initial shock incident or may result from cumulative damage from sequential shock and vibration events. In addition, isothermal aging and thermal cycling may cause significant changes of mechanical properties of solder alloys due to evolving of microstructure. These changes are large especially in harsh environment such as high temperature and long-term aging. Consequently, a complete understanding of high strain rate and high temperature behaviors of solder alloy after long period of aging is necessary to perform a better design and optimization in electronics. A viscoplastic model was proposed by Anand [1982, 1989] to describe materials that depend on both operating temperature and strain rate. Recently, it has been broadly used to characterize viscoplastic deformation of lead-free solder materials. However, the Anand constants of SAC305 for high strain rate and high temperature condition at long-term aging are not available. In order to compute the constants for this model, uniaxial tensile tests have been done at a wide range of high strain rate and high temperature conditions within different aging period. In this study, different weighted impact hammers were introduced which enable attaining different high strain rates around 1 to 100 /s. A load cell is on the top of the specimen-grip, which is used to calculate tensile load dynamically. Additionally, a small thermal chamber is used to control the operating temperatures. High-speed data acquisition system was built to capture the stress-strain curves of specimen. Tensile stress-strain curves have been plotted over a wide range of strain rates (8 =10, 35, 50, 75 /s) and temperatures (T = 25, 50, 75, 100, 125, 150, 175, 200°C) at different aging periods (Pristine, 60, 120, 180, 240, 300, 360 days). Totally, seven groups of Anand constants have been computed based non-linear least square curve fitting procedures. In addition, the correctness of the predicted model has been verified by comparing with experimental data.
{"title":"Evolution of high strain rate and high temperature mechanical properties of SAC305 with long term storage up to 1-year","authors":"P. Lall, D. Zhang, J. Suhling, David Locker","doi":"10.1109/ITHERM.2017.7992631","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992631","url":null,"abstract":"The effect of aging on mechanical properties of SAC 305 at low strain rate has been investigated. For high strain rate constitutive mechanical behavior, a number of researchers relied on Split Hopkinson Pressure bar and the strain rate range is from 500/s to 3000/s. However, for typical drop and shock, the strain rate range is from 1/s to 100/s. There is a general scarcity of data for solder materials in this strain rate range. Therefore knowing the mechanical properties of lead free solder at this high strain rate range is very important for design and optimization of package reliability. It is possible that failure may happen at initial shock incident or may result from cumulative damage from sequential shock and vibration events. In addition, isothermal aging and thermal cycling may cause significant changes of mechanical properties of solder alloys due to evolving of microstructure. These changes are large especially in harsh environment such as high temperature and long-term aging. Consequently, a complete understanding of high strain rate and high temperature behaviors of solder alloy after long period of aging is necessary to perform a better design and optimization in electronics. A viscoplastic model was proposed by Anand [1982, 1989] to describe materials that depend on both operating temperature and strain rate. Recently, it has been broadly used to characterize viscoplastic deformation of lead-free solder materials. However, the Anand constants of SAC305 for high strain rate and high temperature condition at long-term aging are not available. In order to compute the constants for this model, uniaxial tensile tests have been done at a wide range of high strain rate and high temperature conditions within different aging period. In this study, different weighted impact hammers were introduced which enable attaining different high strain rates around 1 to 100 /s. A load cell is on the top of the specimen-grip, which is used to calculate tensile load dynamically. Additionally, a small thermal chamber is used to control the operating temperatures. High-speed data acquisition system was built to capture the stress-strain curves of specimen. Tensile stress-strain curves have been plotted over a wide range of strain rates (8 =10, 35, 50, 75 /s) and temperatures (T = 25, 50, 75, 100, 125, 150, 175, 200°C) at different aging periods (Pristine, 60, 120, 180, 240, 300, 360 days). Totally, seven groups of Anand constants have been computed based non-linear least square curve fitting procedures. In addition, the correctness of the predicted model has been verified by comparing with experimental data.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"1976 7‐8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132703332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992459
Lu Qiu, S. Dubey, F. Choo, F. Duan
The heat transfer characteristics are experimentally investigated when a droplet train impinges onto a heated surface. A steady-state experimental method is applied to measure the heat transfer coefficient continuously. The boiling regime, transition of the splashing regime, and post-transition regime can be observed. The hydrodynamic pattern significantly changes with an increase of wall temperature. The associated heat transfer characteristics are diverse in different regimes. In the boiling regime, the heat flux increases with an increase of wall temperature. A peak value is reached when the splashing is just established. However, when it steps into the transition regime, the wall heat flux reduces with an increase in wall temperature. At the end of the transition regime, a sudden drop of the heat flux is found. In the post-transition regime, the heat flux increases with an increase of wall temperature again, whereas the heat transfer coefficient is kept a constant.
{"title":"Droplet train impinging onto a solid substrate surface","authors":"Lu Qiu, S. Dubey, F. Choo, F. Duan","doi":"10.1109/ITHERM.2017.7992459","DOIUrl":"https://doi.org/10.1109/ITHERM.2017.7992459","url":null,"abstract":"The heat transfer characteristics are experimentally investigated when a droplet train impinges onto a heated surface. A steady-state experimental method is applied to measure the heat transfer coefficient continuously. The boiling regime, transition of the splashing regime, and post-transition regime can be observed. The hydrodynamic pattern significantly changes with an increase of wall temperature. The associated heat transfer characteristics are diverse in different regimes. In the boiling regime, the heat flux increases with an increase of wall temperature. A peak value is reached when the splashing is just established. However, when it steps into the transition regime, the wall heat flux reduces with an increase in wall temperature. At the end of the transition regime, a sudden drop of the heat flux is found. In the post-transition regime, the heat flux increases with an increase of wall temperature again, whereas the heat transfer coefficient is kept a constant.","PeriodicalId":387542,"journal":{"name":"2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131664394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/ITHERM.2017.7992634
P. Lall, Shantanu Deshpande, L. Nguyen
Copper (Cu) wire bonding, which is a newer alternative to Gold (Au) wire bonding, gets affected greatly by the variety of operating conditions. Selection of different materials, such as epoxy molding compound (EMC) used in the molding process plays key role in defining lifetime for wirebond system. Higher ionic contamination adversely affects the reliability of Cu wirebonds. Interaction of the EMCs with different properties with the Cu wirebond under harsh environment in presence of bias has not been fully understood. Quantification of the acceleration of the wirebond degradation under bias conditions is yet to be established. Previous research mainly investigates failure mechanisms upon failure, however does not report progression of damage which is leading to the failure. This information and understanding of the progression mechanism can yield into development of prognostics based life prediction models. In this paper, Cu wire bonded parts were subjected to high temperature aging conditions. One set of packages was subjected to unbiased test, and another set was subjected to biased condition. Change in electric response of both sets was monitored and was correlated with degradation of Cu-Al interface using ball shear test. Effect of EMC properties as well as voltage bias on the wirebond was then established and discussed in details.
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