Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218436
B. Kumar
Interdomain routing protocols are responsible for transferring packets from one administrative domain (AD) to another. Some of the areas connected with interdomain policy routing are examined. A general interaction model of policy routing is discussed, and it is suggested that different policy routing protocols can be derived from some basic model. Criteria are developed for evaluating the effectiveness of policy routing protocols. Merits and shortcomings of all the current protocols for policy routing are discussed. It is shown that none of them is satisfactory for current needs of ADs. Future research models for developing new policy routing protocols are considered.<>
{"title":"Models, implementations and design options for inter-domain policy routing protocols","authors":"B. Kumar","doi":"10.1109/CMPEUR.1992.218436","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218436","url":null,"abstract":"Interdomain routing protocols are responsible for transferring packets from one administrative domain (AD) to another. Some of the areas connected with interdomain policy routing are examined. A general interaction model of policy routing is discussed, and it is suggested that different policy routing protocols can be derived from some basic model. Criteria are developed for evaluating the effectiveness of policy routing protocols. Merits and shortcomings of all the current protocols for policy routing are discussed. It is shown that none of them is satisfactory for current needs of ADs. Future research models for developing new policy routing protocols are considered.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127867282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218484
M. Satyanarayana, A. C. Rao, P. Suresh, J. Srinivas, P.V.S. Ramesam, R. Chittibabu B.
The authors simulated a problem entitled 'the automated pipe route planner in three-dimensional plant layout design into a nonlinear programming model' by using Rosenbrock's rotating direction method for unconstrained optimization. In this method, the coordinate system is rotated in each stage of minimization in such a manner that the first axis is oriented towards the locally estimated direction of the valley and all the other axes are made mutually orthogonal and normal to the first axis. The proposed method of knowledge based route planning for pipes provides a tool for pipe route finding problems in a layout plan. The iterative algorithm to produce the optimal solution is presented.<>
{"title":"An automated pipe-route planner in three dimensional plant layout design","authors":"M. Satyanarayana, A. C. Rao, P. Suresh, J. Srinivas, P.V.S. Ramesam, R. Chittibabu B.","doi":"10.1109/CMPEUR.1992.218484","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218484","url":null,"abstract":"The authors simulated a problem entitled 'the automated pipe route planner in three-dimensional plant layout design into a nonlinear programming model' by using Rosenbrock's rotating direction method for unconstrained optimization. In this method, the coordinate system is rotated in each stage of minimization in such a manner that the first axis is oriented towards the locally estimated direction of the valley and all the other axes are made mutually orthogonal and normal to the first axis. The proposed method of knowledge based route planning for pipes provides a tool for pipe route finding problems in a layout plan. The iterative algorithm to produce the optimal solution is presented.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133661997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218455
V. Kadary
The author describes a method for evaluating software productivity in the program development phase. The use of earned value index as the measure of productivity of a software team involves two steps. First, it requires appropriate preparation or revision of the work plan. The second step is the measurement itself, which is carried out either periodically or upon completion of a milestone. The detailed description of the procedures involved in the estimation process, together with practical examples, are given.<>
{"title":"On application of earned value index to software productivity metrics in embedded computer systems","authors":"V. Kadary","doi":"10.1109/CMPEUR.1992.218455","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218455","url":null,"abstract":"The author describes a method for evaluating software productivity in the program development phase. The use of earned value index as the measure of productivity of a software team involves two steps. First, it requires appropriate preparation or revision of the work plan. The second step is the measurement itself, which is carried out either periodically or upon completion of a milestone. The detailed description of the procedures involved in the estimation process, together with practical examples, are given.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132554744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218420
J. Sosnowski
Outlines some problems which result from transient faults in designing fault tolerant systems. Based on this analysis, a systematic approach to effective transient fault tolerance in redundant systems is presented. The main point of this approach is to design error handling procedures, taking into account a variety of available error detection mechanisms and the context of error appearance. Implementation of these strategies required some special hardware and software. This approach is illustrated for systems with double and triple modular redundancy.<>
{"title":"Transient fault tolerance in redundant systems","authors":"J. Sosnowski","doi":"10.1109/CMPEUR.1992.218420","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218420","url":null,"abstract":"Outlines some problems which result from transient faults in designing fault tolerant systems. Based on this analysis, a systematic approach to effective transient fault tolerance in redundant systems is presented. The main point of this approach is to design error handling procedures, taking into account a variety of available error detection mechanisms and the context of error appearance. Implementation of these strategies required some special hardware and software. This approach is illustrated for systems with double and triple modular redundancy.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218430
J.R. Gonzalez de Mendivil, J. R. Garitagoitia
A method for solving the deadlock detection problem in operating systems with single unit resources is introduced by using the formalism of the automata and languages theory. The waiting relations between processes are represented in a wait-string. The study of the properties of wait-strings which contain deadlocked processes allows a solution to be obtained for the deadlock detection problem in the form of a finite automation (FA). The designed FA, which accepts the wait-strings with deadlock, acts as a deadlock detection algorithm. Its performance is proved. The design method of the FA is itself a detection algorithm based on the same principles. Therefore its formal proof is also valid, and can be used when strong memory requirements are imposed.<>
{"title":"Syntactic approach to the deadlock detection problem","authors":"J.R. Gonzalez de Mendivil, J. R. Garitagoitia","doi":"10.1109/CMPEUR.1992.218430","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218430","url":null,"abstract":"A method for solving the deadlock detection problem in operating systems with single unit resources is introduced by using the formalism of the automata and languages theory. The waiting relations between processes are represented in a wait-string. The study of the properties of wait-strings which contain deadlocked processes allows a solution to be obtained for the deadlock detection problem in the form of a finite automation (FA). The designed FA, which accepts the wait-strings with deadlock, acts as a deadlock detection algorithm. Its performance is proved. The design method of the FA is itself a detection algorithm based on the same principles. Therefore its formal proof is also valid, and can be used when strong memory requirements are imposed.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128807794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218493
F. Proesmans, L. Claesen, M. Genoe, E. Verlind
The application strategy is described of a new verification methodology on the CATHEDRAL-I silicon compiler. The basic goal is to prove the feasibility of an automated verification process based on the presented SFG-tracing concept. This methodology permits the overall evaluation of the lower-level implementation versus the high-level behavioral signal flow graph. Gradually, correspondences between specific signals, called references signals, at the different design levels are mapped during the architecture synthesis. Efficient behavior comparison can be started as soon as those relationships are traced accurately and completely. This task was handled with the aid of the compiled-code symbolic simulator COSMOS.<>
{"title":"Verification strategy of the CATHEDRAL-I silicon compiler based on the SFG-tracing methodology","authors":"F. Proesmans, L. Claesen, M. Genoe, E. Verlind","doi":"10.1109/CMPEUR.1992.218493","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218493","url":null,"abstract":"The application strategy is described of a new verification methodology on the CATHEDRAL-I silicon compiler. The basic goal is to prove the feasibility of an automated verification process based on the presented SFG-tracing concept. This methodology permits the overall evaluation of the lower-level implementation versus the high-level behavioral signal flow graph. Gradually, correspondences between specific signals, called references signals, at the different design levels are mapped during the architecture synthesis. Efficient behavior comparison can be started as soon as those relationships are traced accurately and completely. This task was handled with the aid of the compiled-code symbolic simulator COSMOS.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125300202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218463
G. Klas, R. Lepold
The authors present a tool for modeling with generalized stochastic Petri nets (GSPNs). TOMSPIN was used for the modeling of multiprocessor architectures on the processor-memory-switch level. The requirements for an effective support of computer system design by a system evaluation tool based on GSPNs are outlined. It is shown that these requirements were met by TOMSPIN. The structure of the software package is described. Recently implemented algorithms for the computation of nonstandard results of GSPNs are discussed. They are illustrated by means of an example.<>
{"title":"TOMSPIN-a tool for modeling with stochastic Petri nets","authors":"G. Klas, R. Lepold","doi":"10.1109/CMPEUR.1992.218463","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218463","url":null,"abstract":"The authors present a tool for modeling with generalized stochastic Petri nets (GSPNs). TOMSPIN was used for the modeling of multiprocessor architectures on the processor-memory-switch level. The requirements for an effective support of computer system design by a system evaluation tool based on GSPNs are outlined. It is shown that these requirements were met by TOMSPIN. The structure of the software package is described. Recently implemented algorithms for the computation of nonstandard results of GSPNs are discussed. They are illustrated by means of an example.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134074762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218406
S. Crane, Naranker Dulay
Presents a configuration language based approach to the description and construction of distributed multiuser applications. The authors describe the facilities of the configuration language DARWIN which permit the description of multiuser applications in a manner identical to normal configuration-based parallel or distributed programs. The implementation platform, REX, is described, as is Conf, a distributed conferencing programs which, while simple, illustrates several of DARWIN's important and powerful features.<>
{"title":"Constructing multi-user applications in REX","authors":"S. Crane, Naranker Dulay","doi":"10.1109/CMPEUR.1992.218406","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218406","url":null,"abstract":"Presents a configuration language based approach to the description and construction of distributed multiuser applications. The authors describe the facilities of the configuration language DARWIN which permit the description of multiuser applications in a manner identical to normal configuration-based parallel or distributed programs. The implementation platform, REX, is described, as is Conf, a distributed conferencing programs which, while simple, illustrates several of DARWIN's important and powerful features.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132128578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218494
J.G. Samsom, L. Claesen, H. de Man
A formal method for the optimization of a specification in a guaranteed correct way is presented. As an example, the transformation from a behavioral specification of the Hough transform in an image space, towards an optimized specification, is presented. The transformations are meant to be used in an interactive environment. The main result presented is that, by using a limited set of transformations, an optimized description in terms of a silicon compiler can be derived in a guaranteed correct way.<>
{"title":"Correctness preserving transformations on the Hough algorithm","authors":"J.G. Samsom, L. Claesen, H. de Man","doi":"10.1109/CMPEUR.1992.218494","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218494","url":null,"abstract":"A formal method for the optimization of a specification in a guaranteed correct way is presented. As an example, the transformation from a behavioral specification of the Hough transform in an image space, towards an optimized specification, is presented. The transformations are meant to be used in an interactive environment. The main result presented is that, by using a limited set of transformations, an optimized description in terms of a silicon compiler can be derived in a guaranteed correct way.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124768117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218518
K. S. Ng
A wide variety of communication methods are described, both bit serial and bit parallel, used in current microprocessor and microcontroller designs. Nine different coprocessor interfaces are illustrated. Practical examples of burst and pipeline access, data synchronization, bus snooping address recognition, and resolution of masters provide a basis for further studies of interface architectures for interchip communication.<>
{"title":"A survey of microprocessor communication methods","authors":"K. S. Ng","doi":"10.1109/CMPEUR.1992.218518","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218518","url":null,"abstract":"A wide variety of communication methods are described, both bit serial and bit parallel, used in current microprocessor and microcontroller designs. Nine different coprocessor interfaces are illustrated. Practical examples of burst and pipeline access, data synchronization, bus snooping address recognition, and resolution of masters provide a basis for further studies of interface architectures for interchip communication.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122104329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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