D. J. Godfrey, R. Chater, A. K. Robinson, P.D. Augustus, J. R. Alderman, J.R. Davis, J. Kilner, P. Hemment
The diffusion of arsenic and boron in oxygen-implanted SOI layers has been studied using secondary ion mass spectrometry, (SIMS), Rutherford backscattering spectroscopy (RBS), spreading resistance profiling (SRP), and transmission electron microscopy (TEM). A SIMOX (separation by implantation of oxygen) was produced, and then a 27-nm oxide layer was grown prior to implantation of either arsenic (80 keV, 5*10/sup 15/ cm/sup -2/) or boron (15 keV, 2*10/sup 15/ cm/sup -2/). The samples were annealed at 900 degrees C for 10 min, 30 min, and 120 min in an inert ambient and analyzed using the above techniques. The experimental results have been compared with process modeling simulations where diffusion behavior appropriate to bulk silicon has been incorporated. It has been found that by using appropriate implant and anneal schedules it is possible to produce SIMOX material where the quality of the silicon overlayer allows the majority of diffusion behavior to be predicted using such models.<>
{"title":"Measurement and modelling of arsenic and boron diffusion in oxygen implanted silicon-on-insulator (SOI) layers","authors":"D. J. Godfrey, R. Chater, A. K. Robinson, P.D. Augustus, J. R. Alderman, J.R. Davis, J. Kilner, P. Hemment","doi":"10.1109/SOI.1988.95416","DOIUrl":"https://doi.org/10.1109/SOI.1988.95416","url":null,"abstract":"The diffusion of arsenic and boron in oxygen-implanted SOI layers has been studied using secondary ion mass spectrometry, (SIMS), Rutherford backscattering spectroscopy (RBS), spreading resistance profiling (SRP), and transmission electron microscopy (TEM). A SIMOX (separation by implantation of oxygen) was produced, and then a 27-nm oxide layer was grown prior to implantation of either arsenic (80 keV, 5*10/sup 15/ cm/sup -2/) or boron (15 keV, 2*10/sup 15/ cm/sup -2/). The samples were annealed at 900 degrees C for 10 min, 30 min, and 120 min in an inert ambient and analyzed using the above techniques. The experimental results have been compared with process modeling simulations where diffusion behavior appropriate to bulk silicon has been incorporated. It has been found that by using appropriate implant and anneal schedules it is possible to produce SIMOX material where the quality of the silicon overlayer allows the majority of diffusion behavior to be predicted using such models.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128643328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Maszara, G. Goetz, A. Caviglia, J.B. McKitterick
A novel silicon-on-insulator technique utilizing the bonding of oxidized silicon wafers has been investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces, which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm/sup 2/ at room temperature to approximately=2200 erg/cm/sup 2/ at 1400 degrees C, which is in the same range as the cohesive energy of bulk quartz. The strength was essentially independent of the bond time. Bonds created during a 10 s annealing at 800 degrees C were strong enough to withstand both the thinning of the top wafer to the desired thickness and the subsequent device processing. Three distinct phases of the bonding process were observed. The electrical properties of the bond between the wafers were tested using MOS capacitors. The results were consistent with a negative charge density at the bond interface of approximately 10/sup 11/ cm/sup -2/. A double etch-back procedure was used to thin the device wafer to the desired thickness. The characteristics of the resulting film are described. CMOS devices made in a 0.3- mu m-thick layer had subthreshold slopes of 68 mV/decade (for both n- and p-channel MOS transistors). The effective carrier lifetime was >30 mu s in 300-nm-thick Si films, and the interface state density at the Si-film/buried oxide interface was <5*10/sup 10/ cm/sup -2/.<>
{"title":"Silicon-on-insulator by wafer bonding and etch-back","authors":"W. Maszara, G. Goetz, A. Caviglia, J.B. McKitterick","doi":"10.1109/SOI.1988.95391","DOIUrl":"https://doi.org/10.1109/SOI.1988.95391","url":null,"abstract":"A novel silicon-on-insulator technique utilizing the bonding of oxidized silicon wafers has been investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces, which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm/sup 2/ at room temperature to approximately=2200 erg/cm/sup 2/ at 1400 degrees C, which is in the same range as the cohesive energy of bulk quartz. The strength was essentially independent of the bond time. Bonds created during a 10 s annealing at 800 degrees C were strong enough to withstand both the thinning of the top wafer to the desired thickness and the subsequent device processing. Three distinct phases of the bonding process were observed. The electrical properties of the bond between the wafers were tested using MOS capacitors. The results were consistent with a negative charge density at the bond interface of approximately 10/sup 11/ cm/sup -2/. A double etch-back procedure was used to thin the device wafer to the desired thickness. The characteristics of the resulting film are described. CMOS devices made in a 0.3- mu m-thick layer had subthreshold slopes of 68 mV/decade (for both n- and p-channel MOS transistors). The effective carrier lifetime was >30 mu s in 300-nm-thick Si films, and the interface state density at the Si-film/buried oxide interface was <5*10/sup 10/ cm/sup -2/.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123859007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It has been found, from the results of a design study carried out out on three-dimensional (3-D) SOI integration, that the expected improvements in speed and packing density over bulk technology are not large enough to make two-level 3-D viable in the context of VLSI circuits. However, the 3-D technique has been identified as having a major role in the area of mixed technology applications. The design and fabrication of a smart power-test-bed demonstration circuit, to evaluate the feasibility of this approach, are described. For this circuit a 50-70-V bulk DMOS power technology and a 3- mu m SOI CMOS controlling logic have been developed. To provide maximum design flexibility both of these technologies have been combined in a 3-D SOI gate array, suitable for semicustom interfacing and medium current/voltage driving applications. The evaluation circuit is configured as a 50-V/1-A stepper motor controller.<>
{"title":"The design and fabrication of a 3D smart motor controller in ZMR material","authors":"A. Mathewson","doi":"10.1109/SOI.1988.95437","DOIUrl":"https://doi.org/10.1109/SOI.1988.95437","url":null,"abstract":"It has been found, from the results of a design study carried out out on three-dimensional (3-D) SOI integration, that the expected improvements in speed and packing density over bulk technology are not large enough to make two-level 3-D viable in the context of VLSI circuits. However, the 3-D technique has been identified as having a major role in the area of mixed technology applications. The design and fabrication of a smart power-test-bed demonstration circuit, to evaluate the feasibility of this approach, are described. For this circuit a 50-70-V bulk DMOS power technology and a 3- mu m SOI CMOS controlling logic have been developed. To provide maximum design flexibility both of these technologies have been combined in a 3-D SOI gate array, suitable for semicustom interfacing and medium current/voltage driving applications. The evaluation circuit is configured as a 50-V/1-A stepper motor controller.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"389 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129007454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Some results obtained in a CMOS prototype line environment are reported to show the compatibility of SIMOX (separation by implantation of oxygen) technology with industrial applications. The main parameters of devices and circuits optimization are analyzed in terms of VLSI applications. New floating-body effects and solutions to improve the SOI performances are discussed. High-speed and radiation-hard technologies are examined.<>
{"title":"SIMOX and VLSI high speed and rad hard applications: discussion of floating body effects and circuits optimization","authors":"A. Auberton-Herve","doi":"10.1109/SOI.1988.95427","DOIUrl":"https://doi.org/10.1109/SOI.1988.95427","url":null,"abstract":"Some results obtained in a CMOS prototype line environment are reported to show the compatibility of SIMOX (separation by implantation of oxygen) technology with industrial applications. The main parameters of devices and circuits optimization are analyzed in terms of VLSI applications. New floating-body effects and solutions to improve the SOI performances are discussed. High-speed and radiation-hard technologies are examined.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121192228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Thomas, J.R. Davis, K. Reeson, P. Hemment, J. Keen, J. G. Castledine, D. Brumhead, M. Goulding, J. Alderman, J. Farr, L.G. Earwalker
Summary form only given. To maximize the performance of SOI-CMOS transistors, the silicon film under the gate should be depleted, which requires the use of thin-film SOI material. The authors have produced 1- mu m thin-film SOI-CMOS transistors in wafers produced by separation by oxygen implantation (SIMOX) and by oxidation of porous silicon (FIPOS) processes. The silicon film thicknesses were approximately 140 nm for the SIMOX wafers and 100 nm for the FIPOS wafers. The basic characteristics of transistors in the two types of material are similar, with high gains and current drives, near-ideal subthreshold slopes, and low junction leakages. In both cases the characteristics are free from the kink seen in partially depleted devices. Both types of n-channel device exhibit slight negative output resistance at high gate voltages. Low-field-inversion mobilities are comparable for the two types of SOI. For SIMOX material the n- and p-channel mobilities are 580 and 220 cm/sup 2//V/s, respectively; for FIPOS the figures are 520 and 235 cm/sup 2//V/s. The back channel mobilities of SIMOX transistors are over 90% of the front channel values; for FIPOS the back channel mobilities are 55-60% of the values for the front channels. The values of Delta L for both front and back channels and for both types of material that show no anomalous lateral diffusion of source/drain dopants has occurred.<>
{"title":"A comparison of fully depleted SOI-CMOS transistors in FIPOS and SIMOX substrates","authors":"N. Thomas, J.R. Davis, K. Reeson, P. Hemment, J. Keen, J. G. Castledine, D. Brumhead, M. Goulding, J. Alderman, J. Farr, L.G. Earwalker","doi":"10.1109/SOI.1988.95413","DOIUrl":"https://doi.org/10.1109/SOI.1988.95413","url":null,"abstract":"Summary form only given. To maximize the performance of SOI-CMOS transistors, the silicon film under the gate should be depleted, which requires the use of thin-film SOI material. The authors have produced 1- mu m thin-film SOI-CMOS transistors in wafers produced by separation by oxygen implantation (SIMOX) and by oxidation of porous silicon (FIPOS) processes. The silicon film thicknesses were approximately 140 nm for the SIMOX wafers and 100 nm for the FIPOS wafers. The basic characteristics of transistors in the two types of material are similar, with high gains and current drives, near-ideal subthreshold slopes, and low junction leakages. In both cases the characteristics are free from the kink seen in partially depleted devices. Both types of n-channel device exhibit slight negative output resistance at high gate voltages. Low-field-inversion mobilities are comparable for the two types of SOI. For SIMOX material the n- and p-channel mobilities are 580 and 220 cm/sup 2//V/s, respectively; for FIPOS the figures are 520 and 235 cm/sup 2//V/s. The back channel mobilities of SIMOX transistors are over 90% of the front channel values; for FIPOS the back channel mobilities are 55-60% of the values for the front channels. The values of Delta L for both front and back channels and for both types of material that show no anomalous lateral diffusion of source/drain dopants has occurred.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122850094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Dumin, S. Dabral, M. Freytag, P. Robertson, G. Carver, D. Novotny
SOS films 0.2- mu m, 0.5- mu m, and 1.0- mu m thick have been grown at rates from 0.5 to 26 mu m/min in a single-wafer epitaxial reactor. Both p-channel and n-channel MOS transistors were fabricated, using n/sup +/ poly-Si as a gate material. The channel lengths and widths were 20 mu m and 250 mu m, respectively. The p-channel transistors were enhancement devices with threshold voltages around -1.2 V. The n-channel transistors were depletion devices with threshold voltages around 0 V. The 1.0- mu m-thick films produced transistors with values of mu /sub n/ around 700 cm/sup 2//V-s and mu /sub p/ around 275 cm/sup 2//V-s and almost independent of growth rate. The 0.5- mu m-thick films produced transistors with lower mobilities until the growth rate exceeded 8 mu m/min. Films grown at growth rates above 8 mu m/min produced n-channel and p-channel transistors with mobilities of 700 cm/sup 2//V-s and 250 cm/sup 2//V-s, respectively. The 0.2- mu m-thick films produced lower mobility transistors until the growth rates exceeded 8 mu m/min, at which time the mobilities also reached the above-quoted values. Several films 0.1- mu m-thick grown at growth rates above 10 mu m/min had equally high mobilities. The subthreshold characteristics of these transistors indicated surface-state densities of about 10/sup 11/ states/cm/sup 2/. Leakage currents were less than 10/sup -11/ A. The mobility dropped about 20% from the threshold voltage to gate voltages of 5 V. The mobilities in the saturation region were about 20% less than the mobilities in the linear region.<>
{"title":"Ultra-thin high quality SOS films","authors":"D. Dumin, S. Dabral, M. Freytag, P. Robertson, G. Carver, D. Novotny","doi":"10.1109/SOI.1988.95389","DOIUrl":"https://doi.org/10.1109/SOI.1988.95389","url":null,"abstract":"SOS films 0.2- mu m, 0.5- mu m, and 1.0- mu m thick have been grown at rates from 0.5 to 26 mu m/min in a single-wafer epitaxial reactor. Both p-channel and n-channel MOS transistors were fabricated, using n/sup +/ poly-Si as a gate material. The channel lengths and widths were 20 mu m and 250 mu m, respectively. The p-channel transistors were enhancement devices with threshold voltages around -1.2 V. The n-channel transistors were depletion devices with threshold voltages around 0 V. The 1.0- mu m-thick films produced transistors with values of mu /sub n/ around 700 cm/sup 2//V-s and mu /sub p/ around 275 cm/sup 2//V-s and almost independent of growth rate. The 0.5- mu m-thick films produced transistors with lower mobilities until the growth rate exceeded 8 mu m/min. Films grown at growth rates above 8 mu m/min produced n-channel and p-channel transistors with mobilities of 700 cm/sup 2//V-s and 250 cm/sup 2//V-s, respectively. The 0.2- mu m-thick films produced lower mobility transistors until the growth rates exceeded 8 mu m/min, at which time the mobilities also reached the above-quoted values. Several films 0.1- mu m-thick grown at growth rates above 10 mu m/min had equally high mobilities. The subthreshold characteristics of these transistors indicated surface-state densities of about 10/sup 11/ states/cm/sup 2/. Leakage currents were less than 10/sup -11/ A. The mobility dropped about 20% from the threshold voltage to gate voltages of 5 V. The mobilities in the saturation region were about 20% less than the mobilities in the linear region.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"84 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113971963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. K. Robinson, K. Reeson, P. Hemment, N. Thomas, J.R. Davis, K. Christensen, C. Marsh, G. Booker, J. Kilner, R. Chater
It has recently been shown that SIMOX (separation by implantation of oxygen) technology can be extended to provide both vertical and lateral isolation of device islands by a single implantation stage. This technology (TDI) entails implantation of O/sup +/ ions through a deposited masking layer of SiO/sub 2/ in which windows are opened to define the silicon device islands. However, the structures had detrimental characteristics (e.g. nonplanar surfaces and entrapped silicon islands in the synthesized SiO/sub 2/) that detracted from the utility of the technique. A process is reported that produces improved structures, which are suitable for application to circuits.<>
{"title":"Total dielectric isolation (TDI) of silicon device islands by a single O/sup +/ implantation stage","authors":"A. K. Robinson, K. Reeson, P. Hemment, N. Thomas, J.R. Davis, K. Christensen, C. Marsh, G. Booker, J. Kilner, R. Chater","doi":"10.1109/SOI.1988.95432","DOIUrl":"https://doi.org/10.1109/SOI.1988.95432","url":null,"abstract":"It has recently been shown that SIMOX (separation by implantation of oxygen) technology can be extended to provide both vertical and lateral isolation of device islands by a single implantation stage. This technology (TDI) entails implantation of O/sup +/ ions through a deposited masking layer of SiO/sub 2/ in which windows are opened to define the silicon device islands. However, the structures had detrimental characteristics (e.g. nonplanar surfaces and entrapped silicon islands in the synthesized SiO/sub 2/) that detracted from the utility of the technique. A process is reported that produces improved structures, which are suitable for application to circuits.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116914368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
BESOI is made epitaxially growing a high-resistivity layer on a low-resistivity substrate, oxidizing the epilayer, and then thermally bonding a second oxidized wafer (the handle) onto the oxidized epilayer. The SOI film is then formed by etching the original substrate up to the epilayer, leaving the handle as the new substrate. The major incentive for using this technology is the thermal Si/SiO/sub 2/ interface between the SOI layer and the insulator. The author discusses briefly film thickness problems and the techniques whereby they can be minimized.<>
{"title":"Film uniformly in bond and etch-back silicon on insulator (BESOI)","authors":"C. Hunt","doi":"10.1109/SOI.1988.95429","DOIUrl":"https://doi.org/10.1109/SOI.1988.95429","url":null,"abstract":"BESOI is made epitaxially growing a high-resistivity layer on a low-resistivity substrate, oxidizing the epilayer, and then thermally bonding a second oxidized wafer (the handle) onto the oxidized epilayer. The SOI film is then formed by etching the original substrate up to the epilayer, leaving the handle as the new substrate. The major incentive for using this technology is the thermal Si/SiO/sub 2/ interface between the SOI layer and the insulator. The author discusses briefly film thickness problems and the techniques whereby they can be minimized.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124913756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors have examined in detail the electrochemistry of both n- and p-type single-crystal
作者详细地研究了n型和p型单晶的电化学性质
{"title":"Silicon electrochemistry related to the formation of porous silicon","authors":"M. Kelly, T. Guilinger, S. S. Tsao","doi":"10.1109/SOI.1988.95393","DOIUrl":"https://doi.org/10.1109/SOI.1988.95393","url":null,"abstract":"The authors have examined in detail the electrochemistry of both n- and p-type single-crystal","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"683 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116213506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Lateral isolation of individual circuit components in CMOS/SOI technology is most effectively accomplished by creating mesa structures in the top silicon film. This construction results in a parasitic transistor at the edge of the silicon mesa which produces a hump in the subthreshold I-V characteristics and can result in added leakage current. The effects of the parasitic transistor can be eliminated if its threshold voltage is made higher than that of the main transistor by appropriate doping of the sidewall. However, this selective doping is not easily achieved, particularly if the sidewall edges are vertical. An improved technique has been developed for self-aligned doping of the sidewall transistor that uses the deposition and etch of a conformal oxide to pattern the doped sidewall region. This process sequence eliminates many of the problems associated with prior processes.<>
{"title":"Self aligned doping of mesa sidewalls for SOI transistors","authors":"M. Matloubian, B. Mao, G. Pollack","doi":"10.1109/SOI.1988.95404","DOIUrl":"https://doi.org/10.1109/SOI.1988.95404","url":null,"abstract":"Summary form only given. Lateral isolation of individual circuit components in CMOS/SOI technology is most effectively accomplished by creating mesa structures in the top silicon film. This construction results in a parasitic transistor at the edge of the silicon mesa which produces a hump in the subthreshold I-V characteristics and can result in added leakage current. The effects of the parasitic transistor can be eliminated if its threshold voltage is made higher than that of the main transistor by appropriate doping of the sidewall. However, this selective doping is not easily achieved, particularly if the sidewall edges are vertical. An improved technique has been developed for self-aligned doping of the sidewall transistor that uses the deposition and etch of a conformal oxide to pattern the doped sidewall region. This process sequence eliminates many of the problems associated with prior processes.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125776380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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