Summary form only given. Recent improvements have rendered SIMOX (separation by implanted oxygen) material suitable for direct fabrication of radiation-hard and high-performance CMOS devices in the superficial Si film. A persistent problem is the presence of dislocations with undesirably high densities. These residual dislocations are attributed to the vast amounts of Si point defects that are generated in the collision cascades during the high-dose oxygen implantation. By careful optimization of the implant conditions the dislocation content has been reduced by several orders of magnitude to less than 10/sup 5/ cm/sup -2/. For this low-dislocation-content SIMOX material, the superficial Si film exhibits ordering of the oxide precipitates. In the as-implanted structure the dislocations are confined to the lower part of the superficial Si film, where no oxide precipitate ordering occurred. Precipitate ordering and silicon point defects have been shown to play an important role in the establishment of the final microstructure during oxygen implantation.<>
{"title":"Composition and microstructures of low dislocation content SIMOX structures","authors":"H. Baumgart, A. van Ommen","doi":"10.1109/SOI.1988.95394","DOIUrl":"https://doi.org/10.1109/SOI.1988.95394","url":null,"abstract":"Summary form only given. Recent improvements have rendered SIMOX (separation by implanted oxygen) material suitable for direct fabrication of radiation-hard and high-performance CMOS devices in the superficial Si film. A persistent problem is the presence of dislocations with undesirably high densities. These residual dislocations are attributed to the vast amounts of Si point defects that are generated in the collision cascades during the high-dose oxygen implantation. By careful optimization of the implant conditions the dislocation content has been reduced by several orders of magnitude to less than 10/sup 5/ cm/sup -2/. For this low-dislocation-content SIMOX material, the superficial Si film exhibits ordering of the oxide precipitates. In the as-implanted structure the dislocations are confined to the lower part of the superficial Si film, where no oxide precipitate ordering occurred. Precipitate ordering and silicon point defects have been shown to play an important role in the establishment of the final microstructure during oxygen implantation.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"52 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131987444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Devices made in very thin films (1000 AA or less) have a number of characteristics which are different from those of devices made in bulk material or thick SOI. In order to design these devices properly, it is important to understand these differences. To do this, the authors have derived an approximation to Poisson's equation valid for thin silicon films. This approximation is equivalent to assuming that the silicon film is replaced by a sheet of charge and zero thickness. Although this seems to be a radical approximation, the range of validity is surprisingly wide, primarily because the total dopant charge in these thin films is so small. The results of this simple model indicate that long channel transistors fabricated in thin SOI do have a number of properties that are different from transistors fabricated in thicker SOI films or in bulk films. In particular, the threshold voltages of the transistors are independent of doping (if the transistor is thin enough or lightly doped enough), the threshold voltages are dependent only logarithmically on the thickness of the film (if the total dose remains constant), and the front threshold voltage is linearly dependent on the back gate voltage over a wide range of back gate voltages. The dependence of the subthreshold slope on both the front and back interface-state densities can also be obtained from this model.<>
{"title":"An analytic model for very thin SOI transistors","authors":"J.B. McKitterick, A. Caviglia","doi":"10.1109/SOI.1988.95415","DOIUrl":"https://doi.org/10.1109/SOI.1988.95415","url":null,"abstract":"Summary form only given. Devices made in very thin films (1000 AA or less) have a number of characteristics which are different from those of devices made in bulk material or thick SOI. In order to design these devices properly, it is important to understand these differences. To do this, the authors have derived an approximation to Poisson's equation valid for thin silicon films. This approximation is equivalent to assuming that the silicon film is replaced by a sheet of charge and zero thickness. Although this seems to be a radical approximation, the range of validity is surprisingly wide, primarily because the total dopant charge in these thin films is so small. The results of this simple model indicate that long channel transistors fabricated in thin SOI do have a number of properties that are different from transistors fabricated in thicker SOI films or in bulk films. In particular, the threshold voltages of the transistors are independent of doping (if the transistor is thin enough or lightly doped enough), the threshold voltages are dependent only logarithmically on the thickness of the film (if the total dose remains constant), and the front threshold voltage is linearly dependent on the back gate voltage over a wide range of back gate voltages. The dependence of the subthreshold slope on both the front and back interface-state densities can also be obtained from this model.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121324858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The authors have investigated the capability of CMOS/SOS circuits fabricated in a 1.25- mu m DLM technology. The circuits included delay chains, a shift register, gate arrays, and a 8KX8 SRAM. Accurate circuit simulations were possible using the device parameters and current modeling procedures. The preradiation and postradiation performances of circuits were compared to their calculated capability. This included performance under transient radiation conditions. 64K SRAMS were fabricated with an access time under 20 ns. These circuits have demonstrated total dose tolerance in excess of 1 Mrad (Si) and transient upset of 5*10/sup 11/ rad (Si)/s.<>
只提供摘要形式。作者研究了用1.25 μ m DLM技术制作的CMOS/SOS电路的性能。电路包括延迟链、移位寄存器、门阵列和8KX8 SRAM。利用器件参数和当前的建模程序，可以实现精确的电路仿真。将电路的前辐射和后辐射性能与其计算能力进行了比较。这包括在瞬态辐射条件下的性能。制备了存取时间小于20ns的64K ram。这些电路的总耐受剂量超过1mrad (Si)，瞬态扰动为5*10/sup / 11/ rad (Si)/s。
{"title":"CMOS/SOS circuits for space applications","authors":"H. Veloric, R. Green","doi":"10.1109/SOI.1988.95457","DOIUrl":"https://doi.org/10.1109/SOI.1988.95457","url":null,"abstract":"Summary form only given. The authors have investigated the capability of CMOS/SOS circuits fabricated in a 1.25- mu m DLM technology. The circuits included delay chains, a shift register, gate arrays, and a 8KX8 SRAM. Accurate circuit simulations were possible using the device parameters and current modeling procedures. The preradiation and postradiation performances of circuits were compared to their calculated capability. This included performance under transient radiation conditions. 64K SRAMS were fabricated with an access time under 20 ns. These circuits have demonstrated total dose tolerance in excess of 1 Mrad (Si) and transient upset of 5*10/sup 11/ rad (Si)/s.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122770811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Tack, E. Simoen, X.Q. Li, C. Claeys, G. Declerck
Summary form only given. The operation of NMOS transistors made in laser-recrystallized SOI material has been investigated at both 77 K and 4 K. The back-gate voltage (and its history) turns out to have an important influence on the characteristics. It is found that by applying adequate pulses at the back gates, a variety of stable operating states, which are reflected in a variety of threshold voltages, can be established. This multistable behavior of SOI-NMOS transistors at low temperatures is illustrated for a bistable case at 77 K. By applying different back-gate conditions it is possible to obtain different high-threshold states. Stress measurements confirm the stability of the various states. A very similar behavior is also found for transistors operating at 4 K.<>
{"title":"The multi-stable behaviour of SOI-NMOS transistors at low temperatures","authors":"M. Tack, E. Simoen, X.Q. Li, C. Claeys, G. Declerck","doi":"10.1109/SOI.1988.95447","DOIUrl":"https://doi.org/10.1109/SOI.1988.95447","url":null,"abstract":"Summary form only given. The operation of NMOS transistors made in laser-recrystallized SOI material has been investigated at both 77 K and 4 K. The back-gate voltage (and its history) turns out to have an important influence on the characteristics. It is found that by applying adequate pulses at the back gates, a variety of stable operating states, which are reflected in a variety of threshold voltages, can be established. This multistable behavior of SOI-NMOS transistors at low temperatures is illustrated for a bistable case at 77 K. By applying different back-gate conditions it is possible to obtain different high-threshold states. Stress measurements confirm the stability of the various states. A very similar behavior is also found for transistors operating at 4 K.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130388877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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