To understand the formation and evolution of precipitates and defects the authors have studied structural changes in SIMOX (separation by implantation of oxygen) material annealed at temperatures covering the range from lower temperature thermal ramping through high-temperature isothermal annealing. Precipitates and defects were studied with electron microscopy techniques, including high-resolution imaging. Samples annealed for 2 h at lower temperatures from 700 degrees C to 750 degrees C show no structural changes compared to as-implanted material. Samples annealed at intermediate temperatures from 800 degrees C, to 950 degrees C show a series of unusual structural changes which result in the formation of stacking faults. Initially, at 800 degrees C and 850 degrees C small, 3- to 5-nm precipitates form very close (within 10 to 20 nm) to the wafer surface and generate one or two short
{"title":"Mechanisms of defect formation and growth in oxygen implanted SOI material during thermal ramping and isothermal annealing","authors":"S. Krause, C. O. Jung, T. Ravi, D. Burke","doi":"10.1109/SOI.1988.95420","DOIUrl":"https://doi.org/10.1109/SOI.1988.95420","url":null,"abstract":"To understand the formation and evolution of precipitates and defects the authors have studied structural changes in SIMOX (separation by implantation of oxygen) material annealed at temperatures covering the range from lower temperature thermal ramping through high-temperature isothermal annealing. Precipitates and defects were studied with electron microscopy techniques, including high-resolution imaging. Samples annealed for 2 h at lower temperatures from 700 degrees C to 750 degrees C show no structural changes compared to as-implanted material. Samples annealed at intermediate temperatures from 800 degrees C, to 950 degrees C show a series of unusual structural changes which result in the formation of stacking faults. Initially, at 800 degrees C and 850 degrees C small, 3- to 5-nm precipitates form very close (within 10 to 20 nm) to the wafer surface and generate one or two short","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125177068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The authors have investigated the electrochemistry of Si in strong hydrofluoric acid (HF) solutions using potentiodynamic and alternating-current techniques. Their aim was to elucidate the anodizing process in the oxidation of porous Si (FIPOS) SOI technology. A number of p-type (0.005 to 60 Omega -cm) and n-type (0.005 to 0.1 Omega -cm) resistivities have been studied, most of which anodize readily. Potentiodynamic experiments on such material show an anodic branch with three different regions. Frequency dispersion impedance measurements indicate that nondegenerate p-type material biased in the anodic direction has a large surface-state capacitance. The charge-transfer resistance (R/sub ct/) decreases with increasing anodic bias. Highly doped p- and n-type material (>0.15 Omega -cm) has a maximum R/sub ct/ at the rest potential. Complicated inductive and negative resistance features are seen in the anodizing regime.<>
{"title":"Electrochemical aspects of anodically etched Si in strong hydrofluoric acid solutions","authors":"J. L'ecuyer, J. Farr, J. Keen","doi":"10.1109/SOI.1988.95424","DOIUrl":"https://doi.org/10.1109/SOI.1988.95424","url":null,"abstract":"Summary form only given. The authors have investigated the electrochemistry of Si in strong hydrofluoric acid (HF) solutions using potentiodynamic and alternating-current techniques. Their aim was to elucidate the anodizing process in the oxidation of porous Si (FIPOS) SOI technology. A number of p-type (0.005 to 60 Omega -cm) and n-type (0.005 to 0.1 Omega -cm) resistivities have been studied, most of which anodize readily. Potentiodynamic experiments on such material show an anodic branch with three different regions. Frequency dispersion impedance measurements indicate that nondegenerate p-type material biased in the anodic direction has a large surface-state capacitance. The charge-transfer resistance (R/sub ct/) decreases with increasing anodic bias. Highly doped p- and n-type material (>0.15 Omega -cm) has a maximum R/sub ct/ at the rest potential. Complicated inductive and negative resistance features are seen in the anodizing regime.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127960969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. T. Liu, P. Fechner, J. Friedrick, G. Neudeck, L. Velo, L. Bousse, J. Plummer
Selective epitaxial lateral overgrowth (ELO) of silicon has been investigated in the SiH/sub 2/Cl/sub 2//HCl/H/sub 2/ system at reduced pressure and reduced temperature with emphasis on achieving high-quality silicon-on-insulator (SOI) structures for device applications. For these SOI structures to be viable in device applications, the ELO silicon must have good uniformity across the wafer. This would not be so difficult if the horizontal growth rate were much greater than the vertical growth rate. Presently this ratio is about 1:1. Because the vertical height is large it was necessary to etch back to form the thin (<1 mu m) ELO silicon over SiO/sub 2/. To detach the ELO silicon for forming these SOI structures, trench isolation was then applied close to the edge of the seed windows. Three key steps were required to make a high-quality ELO-SOI structure: the cleaning of the silicon surface in the oxide-masked wafers prior to growth, the planar merging of crystal growth fronts and the subsequent etching back to form thin ELO silicon. A uniformity of about 2% was obtained after growth and etchback under certain conditions.<>
{"title":"SOI structures by selective epitaxial lateral overgrowth","authors":"S. T. Liu, P. Fechner, J. Friedrick, G. Neudeck, L. Velo, L. Bousse, J. Plummer","doi":"10.1109/SOI.1988.95392","DOIUrl":"https://doi.org/10.1109/SOI.1988.95392","url":null,"abstract":"Selective epitaxial lateral overgrowth (ELO) of silicon has been investigated in the SiH/sub 2/Cl/sub 2//HCl/H/sub 2/ system at reduced pressure and reduced temperature with emphasis on achieving high-quality silicon-on-insulator (SOI) structures for device applications. For these SOI structures to be viable in device applications, the ELO silicon must have good uniformity across the wafer. This would not be so difficult if the horizontal growth rate were much greater than the vertical growth rate. Presently this ratio is about 1:1. Because the vertical height is large it was necessary to etch back to form the thin (<1 mu m) ELO silicon over SiO/sub 2/. To detach the ELO silicon for forming these SOI structures, trench isolation was then applied close to the edge of the seed windows. Three key steps were required to make a high-quality ELO-SOI structure: the cleaning of the silicon surface in the oxide-masked wafers prior to growth, the planar merging of crystal growth fronts and the subsequent etching back to form thin ELO silicon. A uniformity of about 2% was obtained after growth and etchback under certain conditions.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127002598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Achard, J. Mermet, H. Bono, J.P. Joly, A. Monroy, D. Chapuis, C. Cahill, B. Dunne, A. Mathewson
Summary form only given. The integration of 3-D structures with one-level SOI over bulk is reported. Two kinds of structures have been studied: smart power circuits with bulk LDMOS and laterally displaced CMOS on SOI, and the so-called SMOS (stacked MOS) devices with n or pMOS bulk transistors and the complementary one stacked above using the recrystallized SOI layer. The seeded-zone-melting Ar/sup +/ laser recrystallization technique was used, and tantalum polycide structures provided a refractory interconnection over bulk devices. The CMOS-on-SOI developed was 3-D compatible, i.e no thermal steps were above 950 degrees C and most were in the 800-900 degrees C. The impact of such processes during the recrystallization step on the characteristics of n and pMOS bulk devices was studied. The leakage current of n-type devices was sometimes degraded. The influence of such parameters as isolation oxide thickness, recrystallization conditions, and CMOS process temperature range was also investigated.<>
{"title":"Contribution to 3D SOI integration technologies using seeded laser ZMR and polycide refractory metallisation","authors":"H. Achard, J. Mermet, H. Bono, J.P. Joly, A. Monroy, D. Chapuis, C. Cahill, B. Dunne, A. Mathewson","doi":"10.1109/SOI.1988.95436","DOIUrl":"https://doi.org/10.1109/SOI.1988.95436","url":null,"abstract":"Summary form only given. The integration of 3-D structures with one-level SOI over bulk is reported. Two kinds of structures have been studied: smart power circuits with bulk LDMOS and laterally displaced CMOS on SOI, and the so-called SMOS (stacked MOS) devices with n or pMOS bulk transistors and the complementary one stacked above using the recrystallized SOI layer. The seeded-zone-melting Ar/sup +/ laser recrystallization technique was used, and tantalum polycide structures provided a refractory interconnection over bulk devices. The CMOS-on-SOI developed was 3-D compatible, i.e no thermal steps were above 950 degrees C and most were in the 800-900 degrees C. The impact of such processes during the recrystallization step on the characteristics of n and pMOS bulk devices was studied. The leakage current of n-type devices was sometimes degraded. The influence of such parameters as isolation oxide thickness, recrystallization conditions, and CMOS process temperature range was also investigated.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116434185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given, as follows. A 16*1 static RAM utilizing a radiation-hardened VHSIC CMOS/SOS process and tolerant circuits to achieve functionality beyond 1 Mrad total dose are reported. The RAM is completely static, using asynchronous circuits and requiring no clock inputs. Key circuits were designed to be tolerant of radiation-induced threshold voltage shifts and leakages. Two versions of the design were made along with process test structures and design rule verification modules. The two versions use 2.0- mu m and 1.6- mu m design rules, respectively. Address transition detectors were used to eliminate static bit-line clamps and maintain low operating current, typically under 3 mA. Circuits were designed to ensure that integral precharging did not cause glitches on the output pin. Special test patterns were used to verify that no access time 'push-out' occurs from address skew. Typical access time for 2.0- mu m design rules is 45 ns. The design generally uses conventional full CMOS logic for tolerance to postradiation leakage and threshold voltage shifts. However, the bit-line/sense amp circuitry and an internal read bus required other methods to achieve both high speed and tolerance.<>
{"title":"Radiation hardened 16 K VHSIC CMOS/SOS static RAM","authors":"M. Tennyson, G. Worley","doi":"10.1109/SOI.1988.95444","DOIUrl":"https://doi.org/10.1109/SOI.1988.95444","url":null,"abstract":"Summary form only given, as follows. A 16*1 static RAM utilizing a radiation-hardened VHSIC CMOS/SOS process and tolerant circuits to achieve functionality beyond 1 Mrad total dose are reported. The RAM is completely static, using asynchronous circuits and requiring no clock inputs. Key circuits were designed to be tolerant of radiation-induced threshold voltage shifts and leakages. Two versions of the design were made along with process test structures and design rule verification modules. The two versions use 2.0- mu m and 1.6- mu m design rules, respectively. Address transition detectors were used to eliminate static bit-line clamps and maintain low operating current, typically under 3 mA. Circuits were designed to ensure that integral precharging did not cause glitches on the output pin. Special test patterns were used to verify that no access time 'push-out' occurs from address skew. Typical access time for 2.0- mu m design rules is 45 ns. The design generally uses conventional full CMOS logic for tolerance to postradiation leakage and threshold voltage shifts. However, the bit-line/sense amp circuitry and an internal read bus required other methods to achieve both high speed and tolerance.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130983447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Dutta, G. A. Candela, D. Chandler-Horowitz, M. Peckerar
Summary form only given. The effect of annealing temperature on the various layers in a SIMOX (separation by implantation of oxygen) wafer has been nondestructively characterized using spectroscopic ellipsometry. Four different samples have been probed, which were all implanted under similar conditions but annealed at temperatures of 1150 degrees C, 1200 degrees C, 1250 degrees C, and 1300 degrees C. A modeling scheme has been developed to include the effect of the transition regions between the top Si and the buried oxide increases with anneal temperature, as expected, since more oxygen is pumped from Si and forms SiO/sub 2/. The interlayer between the top Si and the buried oxide becomes very sharp, indicating that the oxide precipitates present at the boundary merge with the buried oxide, and thus the top Si layer is effectively repaired for subsequent device fabrication. The lower transition region between the buried oxide and the substrate is also reduced by high temperature anneal.<>
{"title":"Spectroscopic ellipsometry of oxygen-ion-implanted silicon-on-insulator annealed at different temperatures","authors":"P. Dutta, G. A. Candela, D. Chandler-Horowitz, M. Peckerar","doi":"10.1109/SOI.1988.95408","DOIUrl":"https://doi.org/10.1109/SOI.1988.95408","url":null,"abstract":"Summary form only given. The effect of annealing temperature on the various layers in a SIMOX (separation by implantation of oxygen) wafer has been nondestructively characterized using spectroscopic ellipsometry. Four different samples have been probed, which were all implanted under similar conditions but annealed at temperatures of 1150 degrees C, 1200 degrees C, 1250 degrees C, and 1300 degrees C. A modeling scheme has been developed to include the effect of the transition regions between the top Si and the buried oxide increases with anneal temperature, as expected, since more oxygen is pumped from Si and forms SiO/sub 2/. The interlayer between the top Si and the buried oxide becomes very sharp, indicating that the oxide precipitates present at the boundary merge with the buried oxide, and thus the top Si layer is effectively repaired for subsequent device fabrication. The lower transition region between the buried oxide and the substrate is also reduced by high temperature anneal.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Zingg, H. Graf, W. Appel, P. Vohringer, B. Hofflinger
The authors present a technique for growing epitaxial lateral overgrowth (ELO) structures and thinning them for device application. The use of trichlorosilane makes it possible to obtain local epitaxy without the edition of HCl gas and still suppress nucleation on the oxide. Resultant resistivities were above 300 Omega -cm n-type. Local epitaxy was performed at as low as 830 degrees C making it possible to use this process after devices were realized in the substrate. Samples were planarized using a reflow photoresist and parallel-plate plasma etching. A mixture of CF/sub 4/ and O/sub 2/ was adjusted to obtain the same etch rate for silicon and organic compounds. Lapping with different grit sizes was used and shows promise with ELO structures. Polishing by combined chemical and mechanical action removes silicon only at the top of the ELO, like all mechanical processes. Additionally, polishing slurries that do not chemically attack SiO/sub 2/ films can be selected, making this an ideal technique for silicon islands on an oxide.<>
{"title":"Thinning techniques for 1 mu m ELO-SOI","authors":"R. Zingg, H. Graf, W. Appel, P. Vohringer, B. Hofflinger","doi":"10.1109/SOI.1988.95425","DOIUrl":"https://doi.org/10.1109/SOI.1988.95425","url":null,"abstract":"The authors present a technique for growing epitaxial lateral overgrowth (ELO) structures and thinning them for device application. The use of trichlorosilane makes it possible to obtain local epitaxy without the edition of HCl gas and still suppress nucleation on the oxide. Resultant resistivities were above 300 Omega -cm n-type. Local epitaxy was performed at as low as 830 degrees C making it possible to use this process after devices were realized in the substrate. Samples were planarized using a reflow photoresist and parallel-plate plasma etching. A mixture of CF/sub 4/ and O/sub 2/ was adjusted to obtain the same etch rate for silicon and organic compounds. Lapping with different grit sizes was used and shows promise with ELO structures. Polishing by combined chemical and mechanical action removes silicon only at the top of the ELO, like all mechanical processes. Additionally, polishing slurries that do not chemically attack SiO/sub 2/ films can be selected, making this an ideal technique for silicon islands on an oxide.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124700806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given, as follows. MOSFETs fabricated on silicon-on-insulator substrates have two additional parasitic MOS transistors in parallel with the main front channel. The back-gate transistor is controlled by the substrate with the buried oxide as the dielectric. The sidewall transistor is controlled by the front-gate through the sidewall dielectric. Five-terminal SOI MOSFETs were characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with body at the front and back interfaces can be explained by the standard bulk body bias equation, but the threshold voltage shift at the sidewall is smaller than that expected from this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model has been developed which accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation at large body biases.<>
{"title":"Reduction of threshold voltage at the SOI MOSFET sidewalls due to charge sharing with the front and back interfaces","authors":"M. Matloubian, R. Sundaresan, H. Lu","doi":"10.1109/SOI.1988.95449","DOIUrl":"https://doi.org/10.1109/SOI.1988.95449","url":null,"abstract":"Summary form only given, as follows. MOSFETs fabricated on silicon-on-insulator substrates have two additional parasitic MOS transistors in parallel with the main front channel. The back-gate transistor is controlled by the substrate with the buried oxide as the dielectric. The sidewall transistor is controlled by the front-gate through the sidewall dielectric. Five-terminal SOI MOSFETs were characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with body at the front and back interfaces can be explained by the standard bulk body bias equation, but the threshold voltage shift at the sidewall is smaller than that expected from this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model has been developed which accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation at large body biases.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126459055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Baumgart, M. Theunissen, M. Geyselaers, J. Mulder, W. Rutten, J. Haisma
Summary form only given. During zone-melting of the polycrystalline silicon layer a large temperature gradient exists between the molten Si layer and the underlying layer which contains already completed devices. The occurrence of defects in the thin monocrystalline layer and in the underlying substrate is closely related to the local temperature rise and to thermal gradients induced by the laser beam in the multilayer system. Therefore, precisely defined laser power and spot size conditions are required. It has been demonstrated that the thin silicon film can be made with a low defect density by using defect entrainment techniques. However, these techniques are not necessarily compatible with a damage free substrate. Substrate damage beneath the insulator has been investigated by preferential etching of angle bevelled cross-sections and by X-ray transmission topography. Another technological problem is wafer bow and warpage following the zone-melt recrystallization process. The conditions for minimizing these effects have been determined.<>
{"title":"Defect analysis of SOI structures made by CO/sub 2/-laser zone melt recrystallization","authors":"H. Baumgart, M. Theunissen, M. Geyselaers, J. Mulder, W. Rutten, J. Haisma","doi":"10.1109/SOI.1988.95421","DOIUrl":"https://doi.org/10.1109/SOI.1988.95421","url":null,"abstract":"Summary form only given. During zone-melting of the polycrystalline silicon layer a large temperature gradient exists between the molten Si layer and the underlying layer which contains already completed devices. The occurrence of defects in the thin monocrystalline layer and in the underlying substrate is closely related to the local temperature rise and to thermal gradients induced by the laser beam in the multilayer system. Therefore, precisely defined laser power and spot size conditions are required. It has been demonstrated that the thin silicon film can be made with a low defect density by using defect entrainment techniques. However, these techniques are not necessarily compatible with a damage free substrate. Substrate damage beneath the insulator has been investigated by preferential etching of angle bevelled cross-sections and by X-ray transmission topography. Another technological problem is wafer bow and warpage following the zone-melt recrystallization process. The conditions for minimizing these effects have been determined.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131835901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. A simple method for evaluating SIMOX (separation by implantation oxygen) material by measuring the effective carrier generation lifetime in the regions above and below the buried oxide, using standard transient capacitance techniques, has been developed. For SIMOX wafers, the epilayer above the buried oxide typically has sheet resistance values on the order of approximately 2*10/sup 4/ Omega / Square Operator . This resistance limits the application of the transient capacitance technique to gate oxide capacitors in a MOS/SOI process. By making a long and narrow MOS capacitor with an n/sup +/ guard band, it has been possible to reduce the effective series resistance of the capacitor to a few hundred ohms, thereby making the transient capacitance technique applicable to measuring lifetime in the thin epilayer above the buried oxide. The gate oxide capacitors were fabricated as part of a polysilicon gate CMOS-on-SOI process. Data were obtained for SOI samples with oxygen doses in the range 1.4-1.9*10/sup 18//cm/sup 2/. For example, for an Eaton-implanted wafer, the measured effective lifetime in the top epitaxial layer was 0.34 mu s; in the bulk beneath the buried oxide, the lifetime was 1.6 mu s. Comparable bulk wafer and epi-on-bulk wafer lifetimes were 22 mu s and 14 mu s. The results indicate that the technique is an effective method for evaluating SOI materials.<>
{"title":"SIMOX material characterization by the transient capacitance technique","authors":"A. Bahraman, J. Geneczko, M. Moriwaki","doi":"10.1109/SOI.1988.95401","DOIUrl":"https://doi.org/10.1109/SOI.1988.95401","url":null,"abstract":"Summary form only given. A simple method for evaluating SIMOX (separation by implantation oxygen) material by measuring the effective carrier generation lifetime in the regions above and below the buried oxide, using standard transient capacitance techniques, has been developed. For SIMOX wafers, the epilayer above the buried oxide typically has sheet resistance values on the order of approximately 2*10/sup 4/ Omega / Square Operator . This resistance limits the application of the transient capacitance technique to gate oxide capacitors in a MOS/SOI process. By making a long and narrow MOS capacitor with an n/sup +/ guard band, it has been possible to reduce the effective series resistance of the capacitor to a few hundred ohms, thereby making the transient capacitance technique applicable to measuring lifetime in the thin epilayer above the buried oxide. The gate oxide capacitors were fabricated as part of a polysilicon gate CMOS-on-SOI process. Data were obtained for SOI samples with oxygen doses in the range 1.4-1.9*10/sup 18//cm/sup 2/. For example, for an Eaton-implanted wafer, the measured effective lifetime in the top epitaxial layer was 0.34 mu s; in the bulk beneath the buried oxide, the lifetime was 1.6 mu s. Comparable bulk wafer and epi-on-bulk wafer lifetimes were 22 mu s and 14 mu s. The results indicate that the technique is an effective method for evaluating SOI materials.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134440574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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