N. Guillemot, J. Stoemenos, P. Normand, D. Tsoukalas
Summary form only given. Transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS) have been used to study the implantation damage created by the dopants and their diffusion during subsequent annealing. TEM observations were performed after implantation of phosphorus in SIMOX (separation by implantation of oxygen) structures as well as in bulk silicon. The observations showed that the SIMOX structures are, in general, more sensitive to implantation than bulk silicon, revealing a deeper amorphization after implantation and a rougher surface after annealing. SIMS measurements of the dopant concentration in the SIMOX structures showed an enhanced diffusivity of the impurities as well as a peak of concentration near the surface that is about 150 AA for arsenic and 250 AA for boron. The results indicate that: (1) the trapping of the impurities is due to dopant-contaminant immobile complexes rather than to segregation at the surface: and (2) the locally enhanced diffusion of the dopants, mainly arsenic, corresponds to the region amorphized by the implantation.<>
{"title":"Implantation damage in SIMOX structures","authors":"N. Guillemot, J. Stoemenos, P. Normand, D. Tsoukalas","doi":"10.1109/SOI.1988.95419","DOIUrl":"https://doi.org/10.1109/SOI.1988.95419","url":null,"abstract":"Summary form only given. Transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS) have been used to study the implantation damage created by the dopants and their diffusion during subsequent annealing. TEM observations were performed after implantation of phosphorus in SIMOX (separation by implantation of oxygen) structures as well as in bulk silicon. The observations showed that the SIMOX structures are, in general, more sensitive to implantation than bulk silicon, revealing a deeper amorphization after implantation and a rougher surface after annealing. SIMS measurements of the dopant concentration in the SIMOX structures showed an enhanced diffusivity of the impurities as well as a peak of concentration near the surface that is about 150 AA for arsenic and 250 AA for boron. The results indicate that: (1) the trapping of the impurities is due to dopant-contaminant immobile complexes rather than to segregation at the surface: and (2) the locally enhanced diffusion of the dopants, mainly arsenic, corresponds to the region amorphized by the implantation.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133886655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A two-dimensional device simulator, based on the finite-difference discretization has been developed to analyse the DC characteristics of thin-film SOI transistors. The simulation incorporate a model for avalanche generation at the drain junction, together with both bulk and surface recombination with the SOI film. The simulator has been used to model the characteristics of both p-channel and n-channel transistors fabricated on the same substrate. Accurate simulation of threshold voltage for both types of transistor has been achieved by incorporating a model for excess donor states created during oxygen implantation. The simulator has been used to investigate some of the limitations on the performance of 1- mu m transistors at high drain bias. The results are discussed briefly and qualitatively.<>
{"title":"Two-dimensional numerical simulation of short channel SOI transistors","authors":"G. A. Armstrong, N. Thomas, J.R. Davis","doi":"10.1109/SOI.1988.95399","DOIUrl":"https://doi.org/10.1109/SOI.1988.95399","url":null,"abstract":"A two-dimensional device simulator, based on the finite-difference discretization has been developed to analyse the DC characteristics of thin-film SOI transistors. The simulation incorporate a model for avalanche generation at the drain junction, together with both bulk and surface recombination with the SOI film. The simulator has been used to model the characteristics of both p-channel and n-channel transistors fabricated on the same substrate. Accurate simulation of threshold voltage for both types of transistor has been achieved by incorporating a model for excess donor states created during oxygen implantation. The simulator has been used to investigate some of the limitations on the performance of 1- mu m transistors at high drain bias. The results are discussed briefly and qualitatively.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133146043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. SOI devices fall into two categories: thick-film partially depleted (PD) MOSFETs and thin-film fully depleted (FD) MOSFETs. The basic operation differences between PD and FD MOSFETs have been explored with the aid of two-dimensional numerical modeling. It is found from both modeling and experimental data that FD MOSFETs offer a significant reduction in the two-dimensional short-channel effects and the kink effect found in the PD MOSFETs. The salient design features of the FD MOSFETs are described. CMOS MOSFETs fabricated with gate lengths as short as 400 nm exhibit very good saturation characteristics with electron mobilities of approximately 550 cm/sup 2//V-s. Ring oscillators with gate lengths of 1.2 mu m have shown inverter stage delays of 65 ps. These ring oscillators also show very well-behaved capacitive coupling to the underlying bulk substrate.<>
{"title":"SOI thin film fully depleted high performance devices","authors":"T. MacElwee","doi":"10.1109/SOI.1988.95445","DOIUrl":"https://doi.org/10.1109/SOI.1988.95445","url":null,"abstract":"Summary form only given. SOI devices fall into two categories: thick-film partially depleted (PD) MOSFETs and thin-film fully depleted (FD) MOSFETs. The basic operation differences between PD and FD MOSFETs have been explored with the aid of two-dimensional numerical modeling. It is found from both modeling and experimental data that FD MOSFETs offer a significant reduction in the two-dimensional short-channel effects and the kink effect found in the PD MOSFETs. The salient design features of the FD MOSFETs are described. CMOS MOSFETs fabricated with gate lengths as short as 400 nm exhibit very good saturation characteristics with electron mobilities of approximately 550 cm/sup 2//V-s. Ring oscillators with gate lengths of 1.2 mu m have shown inverter stage delays of 65 ps. These ring oscillators also show very well-behaved capacitive coupling to the underlying bulk substrate.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114215382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Malhi, M. Anderson, C.C. Shen, K. Bean, R. Sundaresan, G. Gopffarth, K. Lindberg, D. Yeakley, J. Smith
Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10- mu m layer on a 4-in wafer is +or-0.5 mu m, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield.<>
{"title":"Characteristics of full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material","authors":"S. Malhi, M. Anderson, C.C. Shen, K. Bean, R. Sundaresan, G. Gopffarth, K. Lindberg, D. Yeakley, J. Smith","doi":"10.1109/SOI.1988.95396","DOIUrl":"https://doi.org/10.1109/SOI.1988.95396","url":null,"abstract":"Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10- mu m layer on a 4-in wafer is +or-0.5 mu m, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124243424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Devices made in very thin films (1000 AA or less) have a number of characteristics which are different from those of devices made in bulk material or thick SOI. In order to design these devices properly, it is important to understand these differences. To do this, the authors have derived an approximation to Poisson's equation valid for thin silicon films. This approximation is equivalent to assuming that the silicon film is replaced by a sheet of charge and zero thickness. Although this seems to be a radical approximation, the range of validity is surprisingly wide, primarily because the total dopant charge in these thin films is so small. The results of this simple model indicate that long channel transistors fabricated in thin SOI do have a number of properties that are different from transistors fabricated in thicker SOI films or in bulk films. In particular, the threshold voltages of the transistors are independent of doping (if the transistor is thin enough or lightly doped enough), the threshold voltages are dependent only logarithmically on the thickness of the film (if the total dose remains constant), and the front threshold voltage is linearly dependent on the back gate voltage over a wide range of back gate voltages. The dependence of the subthreshold slope on both the front and back interface-state densities can also be obtained from this model.<>
{"title":"An analytic model for very thin SOI transistors","authors":"J.B. McKitterick, A. Caviglia","doi":"10.1109/SOI.1988.95415","DOIUrl":"https://doi.org/10.1109/SOI.1988.95415","url":null,"abstract":"Summary form only given. Devices made in very thin films (1000 AA or less) have a number of characteristics which are different from those of devices made in bulk material or thick SOI. In order to design these devices properly, it is important to understand these differences. To do this, the authors have derived an approximation to Poisson's equation valid for thin silicon films. This approximation is equivalent to assuming that the silicon film is replaced by a sheet of charge and zero thickness. Although this seems to be a radical approximation, the range of validity is surprisingly wide, primarily because the total dopant charge in these thin films is so small. The results of this simple model indicate that long channel transistors fabricated in thin SOI do have a number of properties that are different from transistors fabricated in thicker SOI films or in bulk films. In particular, the threshold voltages of the transistors are independent of doping (if the transistor is thin enough or lightly doped enough), the threshold voltages are dependent only logarithmically on the thickness of the film (if the total dose remains constant), and the front threshold voltage is linearly dependent on the back gate voltage over a wide range of back gate voltages. The dependence of the subthreshold slope on both the front and back interface-state densities can also be obtained from this model.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121324858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Capacitors have been fabricated in thinned double solid phase epitaxial (DSPE) silicon on sapphire (SOS). The silicon films are 100-nm thick and doped with phosphorus to 5e+16/cm/sup 2/. The capacitor structures are gated Hall bars with a polysilicon gate on a 25-nm oxide with the source and drain doped N/sup +/. Capacitance data were taken with a lock-in amplifier at low frequencies. Experimental data indicated four regions in a thin-film C-V plot. Three of these regions are the classic accumulation, inversion, and depletion regions. The fourth region is unique to electrically thin films and is called the fully depleted region. The value of the capacitance in region four has been shown to depend quantitatively on the electrically active traps in thin SOS/SOI structures. Thus a thin-film capacitance voltage plot is a sensitive technique for measuring electrically active traps in SOI structures. A model has been developed that explains C-V plots on the thinned, as-purchased SOS and how that relates to C-V plots on the improved SOS. A computer simulation program was written to solve Poisson's equation exactly and predict C-V plots using the proposed model. On the basis of the simulation, the trap model and data show very good agreement. Reduction of trap levels by a factor of 30 in the DSPE material has been measured.<>
{"title":"C-V analysis of ultrathin DSPE SOS","authors":"M. Burgener, G. Garcia, R. Reedy","doi":"10.1109/SOI.1988.95409","DOIUrl":"https://doi.org/10.1109/SOI.1988.95409","url":null,"abstract":"Summary form only given. Capacitors have been fabricated in thinned double solid phase epitaxial (DSPE) silicon on sapphire (SOS). The silicon films are 100-nm thick and doped with phosphorus to 5e+16/cm/sup 2/. The capacitor structures are gated Hall bars with a polysilicon gate on a 25-nm oxide with the source and drain doped N/sup +/. Capacitance data were taken with a lock-in amplifier at low frequencies. Experimental data indicated four regions in a thin-film C-V plot. Three of these regions are the classic accumulation, inversion, and depletion regions. The fourth region is unique to electrically thin films and is called the fully depleted region. The value of the capacitance in region four has been shown to depend quantitatively on the electrically active traps in thin SOS/SOI structures. Thus a thin-film capacitance voltage plot is a sensitive technique for measuring electrically active traps in SOI structures. A model has been developed that explains C-V plots on the thinned, as-purchased SOS and how that relates to C-V plots on the improved SOS. A computer simulation program was written to solve Poisson's equation exactly and predict C-V plots using the proposed model. On the basis of the simulation, the trap model and data show very good agreement. Reduction of trap levels by a factor of 30 in the DSPE material has been measured.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115656466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Colinge, J. Kang, W. McFarland, C. Stout, R. Walker
Summary form only given, as follows. High-speed CMOS logic circuits have been realized in thin-film (100-nm) SIMOX (separation by implantation of oxygen) films annealed at 1250 degrees C. LOCOS (local oxidation of silicon) isolation was used, and the gate oxide thickness was 22 nm. Boron concentration was 1E17 and 5E16 cm/sup -3/ in n- and p-channel devices, respectively. Since no silicide was used, source and drain sheet resistance was about 200 Omega / Square Operator . Only one level of metal was used. Since no kink is observed in thin films, regular nshort and pshort SPICE models were used to simulate circuit operation. Circuits with the following performances were obtained at V/sub dd/=3.3 V: 2:1 multiplexer operating at 1.4 Gb/s (50 mW), voltage-controlled oscillator with an output frequency of up to 1.8 GHz (75 mW), and output stages with 250-ps rise and fall times (output impedance=25 Omega ). The output voltage swing is ECL, and a power dissipation of 65 mW is observed at a 312 Mb/s data rate. A 2:1 frequency divider operating with an input frequency of 2 GHz and dissipating 12 mW was fabricated. Simulation indicates 3-GHz operation if silicide is used and higher speed performance if the circuit is realized with two metal levels.<>
{"title":"Gigahertz CMOS/SIMOX circuits","authors":"J. Colinge, J. Kang, W. McFarland, C. Stout, R. Walker","doi":"10.1109/SOI.1988.95438","DOIUrl":"https://doi.org/10.1109/SOI.1988.95438","url":null,"abstract":"Summary form only given, as follows. High-speed CMOS logic circuits have been realized in thin-film (100-nm) SIMOX (separation by implantation of oxygen) films annealed at 1250 degrees C. LOCOS (local oxidation of silicon) isolation was used, and the gate oxide thickness was 22 nm. Boron concentration was 1E17 and 5E16 cm/sup -3/ in n- and p-channel devices, respectively. Since no silicide was used, source and drain sheet resistance was about 200 Omega / Square Operator . Only one level of metal was used. Since no kink is observed in thin films, regular nshort and pshort SPICE models were used to simulate circuit operation. Circuits with the following performances were obtained at V/sub dd/=3.3 V: 2:1 multiplexer operating at 1.4 Gb/s (50 mW), voltage-controlled oscillator with an output frequency of up to 1.8 GHz (75 mW), and output stages with 250-ps rise and fall times (output impedance=25 Omega ). The output voltage swing is ECL, and a power dissipation of 65 mW is observed at a 312 Mb/s data rate. A 2:1 frequency divider operating with an input frequency of 2 GHz and dissipating 12 mW was fabricated. Simulation indicates 3-GHz operation if silicide is used and higher speed performance if the circuit is realized with two metal levels.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. In lightly doped or near-intrinsic thin-film SOI MOSFETs, the Fermi potential phi /sub B/ is close to zero. If threshold is defined by extrapolation to zero current from the linear region, then at the threshold condition the concentration of free carriers close to the surface is not zero, and may be greater than that of impurity charges in these films. In this case simulation shows that the front-surface potential Psi /sub sf/, which is the band bending from a hypothetical neutral film body to the front surface, is substantially greater than 2 phi /sub B/. Therefore, the definition of threshold condition Psi /sub sf/=2 phi /sub B/ as the onset of strong inversion is not consistent with the experimental technique of determining threshold by extrapolation. The simulations indicate that critical surface-potential bending of phi /sub B/+0.35 V is required to reach the threshold condition at zero back-gate bias when phi /sub B/ is less than 0.35 V. This critical surface-potential bending is found to be a weak function of back-gate bias. The threshold voltage and surface potentials of fully depleted SOI MOSFETs at the threshold condition are not significantly affected by the presence of inversion-layer charge even if it is much greater than the impurity charge as in the case of lightly doped Si films. The front-gate linear transconductance is relatively insensitive to the back-gate device parameters even though the front-gate threshold voltage is dependent on them. Simulations show that the transconductance remains nearly constant up to about 10/sup 15/ cm/sup -3/ and then falls off rapidly with increasing doping concentration as a result of mobility degradation. The transconductance is independent of Si film thickness if the mobility effect is not significant and the source/drain resistance is not high enough to become the limiting factor.<>
{"title":"Threshold voltage and transconductance of fully depleted thin-film SOI MOSFETs","authors":"C. Lee, P. Wyatt","doi":"10.1109/SOI.1988.95414","DOIUrl":"https://doi.org/10.1109/SOI.1988.95414","url":null,"abstract":"Summary form only given. In lightly doped or near-intrinsic thin-film SOI MOSFETs, the Fermi potential phi /sub B/ is close to zero. If threshold is defined by extrapolation to zero current from the linear region, then at the threshold condition the concentration of free carriers close to the surface is not zero, and may be greater than that of impurity charges in these films. In this case simulation shows that the front-surface potential Psi /sub sf/, which is the band bending from a hypothetical neutral film body to the front surface, is substantially greater than 2 phi /sub B/. Therefore, the definition of threshold condition Psi /sub sf/=2 phi /sub B/ as the onset of strong inversion is not consistent with the experimental technique of determining threshold by extrapolation. The simulations indicate that critical surface-potential bending of phi /sub B/+0.35 V is required to reach the threshold condition at zero back-gate bias when phi /sub B/ is less than 0.35 V. This critical surface-potential bending is found to be a weak function of back-gate bias. The threshold voltage and surface potentials of fully depleted SOI MOSFETs at the threshold condition are not significantly affected by the presence of inversion-layer charge even if it is much greater than the impurity charge as in the case of lightly doped Si films. The front-gate linear transconductance is relatively insensitive to the back-gate device parameters even though the front-gate threshold voltage is dependent on them. Simulations show that the transconductance remains nearly constant up to about 10/sup 15/ cm/sup -3/ and then falls off rapidly with increasing doping concentration as a result of mobility degradation. The transconductance is independent of Si film thickness if the mobility effect is not significant and the source/drain resistance is not high enough to become the limiting factor.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126780716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. To evaluate the performance of SOI circuits at high temperatures, CMOS 4K SRAMs were fabricated on SIMOX (separation by implantation of oxygen) and bulk starting material. Four varieties were included in this study: bulk (5 mu m epi on n/sup +/), and SIMOX/SOI with three silicon-layer thicknesses (0.5 mu m, 0.75 mu m, and 1.0 mu m). This combination allows the assessment of three device structures: standard bulk devices, standard SOI devices (S/D contacting the buried oxide), and semi-bulk SOI devices which operate like bulk devices but are dielectrically isolated. All the SOI SRAMs were functional to the maximum temperature available, 300 degrees C. The bulk circuits also functioned at elevated temperatures, but lost functionality between 250 degrees C and 275 degrees C due to the rapidly increasing leakage current associated with the well junction. The synchronous access time increased approximately linearly with temperature for all devices, and was nearly twice the measured room-temperature value at 300 degrees C. Leakage current increased strongly with temperature for all devices, with the thin SOI devices having the least static current at the highest temperatures.<>
只提供摘要形式。为了评估SOI电路在高温下的性能，采用SIMOX(氧注入分离)和块状起始材料制备了CMOS 4K sram。本研究包括四种品种:块状(n/sup +/上5 μ m epi)和SIMOX/SOI，具有三种硅层厚度(0.5 μ m, 0.75 μ m和1.0 μ m)。这种组合可以评估三种器件结构:标准块状器件，标准SOI器件(S/D与埋地氧化物接触)，半块状SOI器件与块状器件一样工作，但介质隔离。所有SOI sram都能在最高可用温度300℃下工作，整体电路也能在高温下工作，但在250℃至275℃之间，由于与井结相关的泄漏电流迅速增加而失去功能。所有器件的同步存取时间都随温度近似线性增加，在300℃时几乎是室温测量值的两倍。所有器件的泄漏电流都随温度的升高而强烈增加，在最高温度下，薄SOI器件的静态电流最小。
{"title":"Demonstration of the benefits of SOI for high temperature operation","authors":"W. Krull, J.C. Lee","doi":"10.1109/SOI.1988.95439","DOIUrl":"https://doi.org/10.1109/SOI.1988.95439","url":null,"abstract":"Summary form only given. To evaluate the performance of SOI circuits at high temperatures, CMOS 4K SRAMs were fabricated on SIMOX (separation by implantation of oxygen) and bulk starting material. Four varieties were included in this study: bulk (5 mu m epi on n/sup +/), and SIMOX/SOI with three silicon-layer thicknesses (0.5 mu m, 0.75 mu m, and 1.0 mu m). This combination allows the assessment of three device structures: standard bulk devices, standard SOI devices (S/D contacting the buried oxide), and semi-bulk SOI devices which operate like bulk devices but are dielectrically isolated. All the SOI SRAMs were functional to the maximum temperature available, 300 degrees C. The bulk circuits also functioned at elevated temperatures, but lost functionality between 250 degrees C and 275 degrees C due to the rapidly increasing leakage current associated with the well junction. The synchronous access time increased approximately linearly with temperature for all devices, and was nearly twice the measured room-temperature value at 300 degrees C. Leakage current increased strongly with temperature for all devices, with the thin SOI devices having the least static current at the highest temperatures.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129825421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The drain junction leakage current, which is representative of the silicon film quality, can be separated from the subthreshold leakage by applying proper biases to the front and back gates. Preliminary results indicate that the junction leakage increases superlinearly with the drain voltage and cannot be explained by S-R-H generation. In addition, the leakage current shows two distinctive regions in the drain voltage. In the low voltage region, below 5 V, its voltage dependence is relatively weak. In the higher voltage region (but below the avalanche breakdown) the leakage depends much more strongly on the drain voltage. The junction leakage in the lower drain voltage region is also found to be very sensitive to temperature. Measurements of leakage as a function of temperature show that the activation energy slightly decreases with increasing voltage, indicating the lowering of an emission barrier by increasing electric field. This leakage current can be well explained by the Poole Frenkel emission model. More rigorous analyses indicate that the leakage mechanism is a mixture of field-enhanced thermal emission and thermally assisted field emission. Drain junction leakage in the higher voltage region shows a good fit to the Fowler-Nordheim field-emission model. Soft breakdown in p/n junction diodes containing metallic impurities has been ascribed to Fowler-Nordheim field emission due to localized high electric fields near metallic precipitates. This argument may be applicable to SIMOX/MOSFETs.<>
{"title":"Drain junction leakage current in SIMOX/MOSFETs","authors":"J. Hwang, P. McMullin, M. Hanes, D. Schmidt","doi":"10.1109/SOI.1988.95431","DOIUrl":"https://doi.org/10.1109/SOI.1988.95431","url":null,"abstract":"Summary form only given. The drain junction leakage current, which is representative of the silicon film quality, can be separated from the subthreshold leakage by applying proper biases to the front and back gates. Preliminary results indicate that the junction leakage increases superlinearly with the drain voltage and cannot be explained by S-R-H generation. In addition, the leakage current shows two distinctive regions in the drain voltage. In the low voltage region, below 5 V, its voltage dependence is relatively weak. In the higher voltage region (but below the avalanche breakdown) the leakage depends much more strongly on the drain voltage. The junction leakage in the lower drain voltage region is also found to be very sensitive to temperature. Measurements of leakage as a function of temperature show that the activation energy slightly decreases with increasing voltage, indicating the lowering of an emission barrier by increasing electric field. This leakage current can be well explained by the Poole Frenkel emission model. More rigorous analyses indicate that the leakage mechanism is a mixture of field-enhanced thermal emission and thermally assisted field emission. Drain junction leakage in the higher voltage region shows a good fit to the Fowler-Nordheim field-emission model. Soft breakdown in p/n junction diodes containing metallic impurities has been ascribed to Fowler-Nordheim field emission due to localized high electric fields near metallic precipitates. This argument may be applicable to SIMOX/MOSFETs.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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