Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551915
M. Pourfath, V. Sverdlov, S. Selberherr
With the progress of miniaturization the size of electronic devices is presently scaling down into the nanometer region, where quantum mechanical effects play an important role. Appropriate technology computer-aided design tools are essential to explore the physics of nanoscale devices and to find methods to optimize their functionality and performance. In this work we review the approaches to quantum mechanical modeling of carrier transport in nanoscale electronic devices. Numerical analyses for graphene nanoribbons are presented as a case study.
{"title":"Modeling demands for nanoscale devices","authors":"M. Pourfath, V. Sverdlov, S. Selberherr","doi":"10.1109/DRC.2010.5551915","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551915","url":null,"abstract":"With the progress of miniaturization the size of electronic devices is presently scaling down into the nanometer region, where quantum mechanical effects play an important role. Appropriate technology computer-aided design tools are essential to explore the physics of nanoscale devices and to find methods to optimize their functionality and performance. In this work we review the approaches to quantum mechanical modeling of carrier transport in nanoscale electronic devices. Numerical analyses for graphene nanoribbons are presented as a case study.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128311134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551935
G. Xu, J. Bai, C. Torres, E. B. Song, J. Tang, Yanlin Zhou, X. Duan, Y. Zhang, Y. Huang, K. Wang
Graphene nanoribbon (GNR) is a quasi one-dimensional film, in which a bandgap exists through the quantum confinement and/or localization effect. Compared to bulk graphene, GNR has high potential in achieving high Ion/Ioff ratio. The carrier mobility of GNR, however, exhibits strong degradation because of the uncontrollable edge roughness and/or states. Most reported GNR-FETs are patterned using ebeam-lithography processes, where the spot size of the electron beam limits the edge smoothness1. In this work, we present a GNR fabrication method based on a nanowire-mask, where the edge roughness is determined by the surface roughness of the nanowire (<1nm) 2. With four-terminal measurement setup, single layer nanoribbon (SLR) devices show μhole∼1180cm2/(Vs), Ion/Ioff >7 and low frequency noise figure A∼10−6 at 300K. Moreover, short-channel SLR (∼250nm) shows conductance quantization at 77K3, and confirms that the quasi-ballistic transport properties can be achieved through this method.
石墨烯纳米带(GNR)是一种准一维薄膜，通过量子约束和/或局域化效应存在带隙。与块体石墨烯相比，GNR在实现高离子/电离比方面具有很高的潜力。然而，由于不可控的边缘粗糙度和/或状态，GNR的载流子迁移率表现出强烈的退化。大多数报道的gnr - fet使用电子束光刻工艺进行图像化，其中电子束的光斑大小限制了边缘的光滑性1。在这项工作中，我们提出了一种基于纳米线掩膜的GNR制造方法，其中边缘粗糙度由纳米线的表面粗糙度决定(2)。采用四端测量装置，单层纳米带(SLR)器件在300K时显示μ空穴~ 1180cm2/(Vs)，离子/ off >7，低频噪声图A ~ 10−6。此外，短通道SLR (~ 250nm)在77K3处显示出电导量子化，并证实了通过这种方法可以实现准弹道输运性质。
{"title":"Nanowire-mask based fabrication of high mobility and low noise graphene nanoribbon short-channel field-effect transistors","authors":"G. Xu, J. Bai, C. Torres, E. B. Song, J. Tang, Yanlin Zhou, X. Duan, Y. Zhang, Y. Huang, K. Wang","doi":"10.1109/DRC.2010.5551935","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551935","url":null,"abstract":"Graphene nanoribbon (GNR) is a quasi one-dimensional film, in which a bandgap exists through the quantum confinement and/or localization effect. Compared to bulk graphene, GNR has high potential in achieving high I<inf>on</inf>/I<inf>off</inf> ratio. The carrier mobility of GNR, however, exhibits strong degradation because of the uncontrollable edge roughness and/or states. Most reported GNR-FETs are patterned using ebeam-lithography processes, where the spot size of the electron beam limits the edge smoothness<sup>1</sup>. In this work, we present a GNR fabrication method based on a nanowire-mask, where the edge roughness is determined by the surface roughness of the nanowire (<1nm) <sup>2</sup>. With four-terminal measurement setup, single layer nanoribbon (SLR) devices show μ<inf>hole</inf>∼1180cm<sup>2</sup>/(Vs), I<inf>on</inf>/I<inf>off</inf> >7 and low frequency noise figure A∼10<sup>−6</sup> at 300K. Moreover, short-channel SLR (∼250nm) shows conductance quantization at 77K<sup>3</sup>, and confirms that the quasi-ballistic transport properties can be achieved through this method.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132760840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551871
Chen-Guan Lee, A. Dodabalapur
Amorphous metal-oxide semiconductors have attracted a significant amount of attention in the past few years because of their high mobility, stability in ambient air and potential to be processed by solution approaches. Performance uniformity throughout a sample is very important for all kinds of solution processes, including spin coating, inkjet printing and drop casting. Thickness variation [1] and annealing process are two main sources of performance fluctuation. In this study, we combined solution-processed zinc tin oxide (ZTO) and solution-processed high-k dielectric, ZrO2 [2], to study the effect of pre-bake before the ZTO annealing on the device performance and performance uniformity. A top contact structure (Fig. 1) is employed while the substrate and the gate electrode are glass and AuPd, respectively.
{"title":"Solution-processed zinc-tin oxide thin-film transistors with high performance and improved uniformity","authors":"Chen-Guan Lee, A. Dodabalapur","doi":"10.1109/DRC.2010.5551871","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551871","url":null,"abstract":"Amorphous metal-oxide semiconductors have attracted a significant amount of attention in the past few years because of their high mobility, stability in ambient air and potential to be processed by solution approaches. Performance uniformity throughout a sample is very important for all kinds of solution processes, including spin coating, inkjet printing and drop casting. Thickness variation [1] and annealing process are two main sources of performance fluctuation. In this study, we combined solution-processed zinc tin oxide (ZTO) and solution-processed high-k dielectric, ZrO2 [2], to study the effect of pre-bake before the ZTO annealing on the device performance and performance uniformity. A top contact structure (Fig. 1) is employed while the substrate and the gate electrode are glass and AuPd, respectively.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130425248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551864
I. Íñiguez-de-la-Torre, V. Kaushal, M. Margala, T. González, J. Mateos
In this work, we have performed a Monte Carlo (MC) simulation to study the THz response of two types of nanometer devices at room temperature, so called three terminal Y-Branch Junction (YBJ) [1] and Ballistic Deflection Transistor (BDT) [2]. This sub-millimeter frequency range in the electromagnetic spectrum is attracting more and more interest due to its broad range of applications, from medical diagnostic to industrial quality control or security-screening tools. Our modeling tool consists of an ensemble MC simulator of the electron dynamics, self-consistently coupled with a 2D Poisson solver (with the finite differences approach) [3]. This tool is quite appropriate for time domain simulation of these ballistic devices at room temperature, as it has already been demonstrated in previous works that provides very good match to measured results [3]. Both types of semiconductor nanodevices, based on high mobility InGaAs channels, due to their small size have a very high surface/volume ratio, so that surface effects at the boundaries play a significant role in the device behavior. To include the depletion effect, a negative surface charge density, σ, is included in the simulator, with a value extracted from measurements.
{"title":"Sub-THz frequency analysis in nano-scale devices at room temperature","authors":"I. Íñiguez-de-la-Torre, V. Kaushal, M. Margala, T. González, J. Mateos","doi":"10.1109/DRC.2010.5551864","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551864","url":null,"abstract":"In this work, we have performed a Monte Carlo (MC) simulation to study the THz response of two types of nanometer devices at room temperature, so called three terminal Y-Branch Junction (YBJ) [1] and Ballistic Deflection Transistor (BDT) [2]. This sub-millimeter frequency range in the electromagnetic spectrum is attracting more and more interest due to its broad range of applications, from medical diagnostic to industrial quality control or security-screening tools. Our modeling tool consists of an ensemble MC simulator of the electron dynamics, self-consistently coupled with a 2D Poisson solver (with the finite differences approach) [3]. This tool is quite appropriate for time domain simulation of these ballistic devices at room temperature, as it has already been demonstrated in previous works that provides very good match to measured results [3]. Both types of semiconductor nanodevices, based on high mobility InGaAs channels, due to their small size have a very high surface/volume ratio, so that surface effects at the boundaries play a significant role in the device behavior. To include the depletion effect, a negative surface charge density, σ, is included in the simulator, with a value extracted from measurements.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127790111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551886
I. Milosavljevic, K. Shinohara, D. Regan, S. Burnham, A. Corrion, P. Hashimoto, D. Wong, M. Hu, C. Butler, A. Schmitz, P. Willadsen, M. Micovic
GaN based HEMT device performance has been steadily improving, offering a combination of high electron velocity and high breakdown field. This makes them a prime candidate for high performance millimeter-wave solid-state power amplifiers (PAs). Further improving high frequency performance requires not only laterally scaling the gate length but also vertically scaling the barrier thickness. Scaling the device, however, must not come at the expense of increased access resistance. The GaN/AlN material system is suitable for vertical device scaling since it provides a high electron density in the channel while reducing the barrier thickness. However, due to AlN's large band gap, a low contact resistance between electrodes and the channel is difficult to achieve. In fact, a high on-resistance (Ron) of >2.0Ω·mm has been reported for GaN/AlN HEMTs using conventional alloyed ohmic contacts [1]
{"title":"Vertically scaled GaN/AlN DH-HEMTs with regrown n+GaN ohmic contacts by MBE","authors":"I. Milosavljevic, K. Shinohara, D. Regan, S. Burnham, A. Corrion, P. Hashimoto, D. Wong, M. Hu, C. Butler, A. Schmitz, P. Willadsen, M. Micovic","doi":"10.1109/DRC.2010.5551886","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551886","url":null,"abstract":"GaN based HEMT device performance has been steadily improving, offering a combination of high electron velocity and high breakdown field. This makes them a prime candidate for high performance millimeter-wave solid-state power amplifiers (PAs). Further improving high frequency performance requires not only laterally scaling the gate length but also vertically scaling the barrier thickness. Scaling the device, however, must not come at the expense of increased access resistance. The GaN/AlN material system is suitable for vertical device scaling since it provides a high electron density in the channel while reducing the barrier thickness. However, due to AlN's large band gap, a low contact resistance between electrodes and the channel is difficult to achieve. In fact, a high on-resistance (Ron) of >2.0Ω·mm has been reported for GaN/AlN HEMTs using conventional alloyed ohmic contacts [1]","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130861594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551897
Jan Genoe, K. Myny, S. Steudel, S. Smout, P. Vicca, B. van der Putten, A. Tripathi, N. V. van Aerle, G. Gelinck, W. Dehaene, P. Heremans
Last year, advances in organic device technology (such as device scaling, high K-dielectrics [1], … ) enabled a substantial progress in performance. This resulted in an increase in the data rate of plastic transponder circuits from about 2 kbit/s [2] to EPC-compatible speeds (50 kbit/s). The organic semiconductor pentacene deposited from solution was replaced by a better-performing vapor-phase deposited pentacene, with a mobility being a factor of 3 higher. The isolation of pentacene transistors in this new process is achieved by an integrated shadow mask, shown in Fig. 1, that results in a reliable isolation of the semiconductor area testified by off-currents below 10pA. We replaced the organic polymer (low-k) dielectric with a 100-nm thick high-k dielectric, sputtered Al2O3, resulting in an 8-fold higher specific accumulation capacitance. That, in turn, allowed for downscaling the transistor channel length from 5µm to 2µm, while maintaining a high output resistance in saturation - and therefore also high inverter gain and noise margins. A cross-section of this process flow is depicted in Fig. 1. Fig. 2 shows a micrograph image of a 5-stage ring oscillator realized in this technology on foil optimized for speed. This organic thin-film circuit technology allows to design with lower overlap capacitance and to downscale the transistor channel length, within the boundaries achievable by existing high-throughput manufacturing tools (e.g. steppers used in backplane manufacturing). In this work, we varied the channel lengths (L) of the TFTs in the circuits between 20µm and 2µm and limited the gate-source and gate-drain overlap capacitances by decreasing the width of the finger-shaped source and drain contacts, that fully overlap the gate, from 5µm to 2µm. Fig. 2 shows a micrograph image of one transistor. Typical transfer curves of transistors fabricated in this technology, having L = 5µm and 2µm, are depicted in Fig. 3 and Fig. 4 respectively. The transistors are normally-on and their charge carrier (hole) mobility exceeds 0.5cm2/Vs. Fig. 5 shows typical transfer curves of a zerovgs-load inverters with channel lengths of 5µm and 2µm. The ratio between drive and load transistor is 10∶1. The inverters have high gains and noise margins. The stage delay (τD) of inverters in this technology is plotted as a function of the supply voltage in Fig. 6. The stage delay is determined from 19-stage ring oscillators. The figure shows τD for inverters with channel lengths from 20µm to 2µm and gate-overlap of the transistor-fingers ranging from 5µm to 2µm. Stage delays below 1µs, and as low as 400ns, are shown at VDD=10V. To our knowledge, no plastic technology was shown before with such speeds at these low power voltages. The effect of decreasing the overlap capacitance is also shown for the two smaller channel lengths: shrinking the overlap from 5µm to 2µm improves the stage delay by a factor of 1.5 to 2. We proceeded with the design and realization of 8bit organic
{"title":"Organic transistor technology options for device performance versus technology options for increased circuit reliability and yield on foil","authors":"Jan Genoe, K. Myny, S. Steudel, S. Smout, P. Vicca, B. van der Putten, A. Tripathi, N. V. van Aerle, G. Gelinck, W. Dehaene, P. Heremans","doi":"10.1109/DRC.2010.5551897","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551897","url":null,"abstract":"Last year, advances in organic device technology (such as device scaling, high K-dielectrics [1], … ) enabled a substantial progress in performance. This resulted in an increase in the data rate of plastic transponder circuits from about 2 kbit/s [2] to EPC-compatible speeds (50 kbit/s). The organic semiconductor pentacene deposited from solution was replaced by a better-performing vapor-phase deposited pentacene, with a mobility being a factor of 3 higher. The isolation of pentacene transistors in this new process is achieved by an integrated shadow mask, shown in Fig. 1, that results in a reliable isolation of the semiconductor area testified by off-currents below 10pA. We replaced the organic polymer (low-k) dielectric with a 100-nm thick high-k dielectric, sputtered Al2O3, resulting in an 8-fold higher specific accumulation capacitance. That, in turn, allowed for downscaling the transistor channel length from 5µm to 2µm, while maintaining a high output resistance in saturation - and therefore also high inverter gain and noise margins. A cross-section of this process flow is depicted in Fig. 1. Fig. 2 shows a micrograph image of a 5-stage ring oscillator realized in this technology on foil optimized for speed. This organic thin-film circuit technology allows to design with lower overlap capacitance and to downscale the transistor channel length, within the boundaries achievable by existing high-throughput manufacturing tools (e.g. steppers used in backplane manufacturing). In this work, we varied the channel lengths (L) of the TFTs in the circuits between 20µm and 2µm and limited the gate-source and gate-drain overlap capacitances by decreasing the width of the finger-shaped source and drain contacts, that fully overlap the gate, from 5µm to 2µm. Fig. 2 shows a micrograph image of one transistor. Typical transfer curves of transistors fabricated in this technology, having L = 5µm and 2µm, are depicted in Fig. 3 and Fig. 4 respectively. The transistors are normally-on and their charge carrier (hole) mobility exceeds 0.5cm2/Vs. Fig. 5 shows typical transfer curves of a zerovgs-load inverters with channel lengths of 5µm and 2µm. The ratio between drive and load transistor is 10∶1. The inverters have high gains and noise margins. The stage delay (τD) of inverters in this technology is plotted as a function of the supply voltage in Fig. 6. The stage delay is determined from 19-stage ring oscillators. The figure shows τD for inverters with channel lengths from 20µm to 2µm and gate-overlap of the transistor-fingers ranging from 5µm to 2µm. Stage delays below 1µs, and as low as 400ns, are shown at VDD=10V. To our knowledge, no plastic technology was shown before with such speeds at these low power voltages. The effect of decreasing the overlap capacitance is also shown for the two smaller channel lengths: shrinking the overlap from 5µm to 2µm improves the stage delay by a factor of 1.5 to 2. We proceeded with the design and realization of 8bit organic","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134084608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551958
W. Prost, F. Tegude
Nanowires can excellently be controlled during synthesis with respect to physical and chemical characteristics, including composition, size, electronic and optical properties. They may be used both as devices and interconnects, and thus can open doors for downscaled integration concepts not seen before. The non-lithographic bottom up synthesis approach on the nanoscale may be extremely costeffective, especially when making use of the large material diversity stemming from decoupling of device from substrate material without loss of structural quality, e.g. growing metallic, Ge or III–V nanowires on Si substrates. Going down to very small dimensions one may make use of quantum confinement effects like reduced phonon scattering and related high carrier mobility, tunable electrical and optical properties, or implementing heterostructures for quantum dot and single electron devices.
{"title":"Fabrication and RF performance of InAs nanowire FET","authors":"W. Prost, F. Tegude","doi":"10.1109/DRC.2010.5551958","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551958","url":null,"abstract":"Nanowires can excellently be controlled during synthesis with respect to physical and chemical characteristics, including composition, size, electronic and optical properties. They may be used both as devices and interconnects, and thus can open doors for downscaled integration concepts not seen before. The non-lithographic bottom up synthesis approach on the nanoscale may be extremely costeffective, especially when making use of the large material diversity stemming from decoupling of device from substrate material without loss of structural quality, e.g. growing metallic, Ge or III–V nanowires on Si substrates. Going down to very small dimensions one may make use of quantum confinement effects like reduced phonon scattering and related high carrier mobility, tunable electrical and optical properties, or implementing heterostructures for quantum dot and single electron devices.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133042066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551879
Hongwei Chen, Maojun Wang, K. J. Chen
Owing to superior physical properties such as high electron saturation velocity and high electric breakdown field, GaN-based high electron mobility transistors (HEMTs) are capable of delivering superior performance in microwave amplifiers, high power switches, and high temperature integrated circuits (ICs). Compared to the conventional D-mode HEMTs with negative threshold voltages, enhancement-mode (E-mode) or normally-off HEMTs are desirable in these applications, for reduced circuit design complexity and fail-safe operation. Fluorine plasma treatment has been used to fabricate E-mode HEMTs [1], and is a robust process for the channel threshold voltage modulation. However, there is no standard equipment for this process and various groups have reported a wide range of process parameters [1–4]. In this work, we demonstrate the self-aligned enhancement-mode AlGaN/GaN HEMTs fabricated with a standard fluorine ion implantation. Ion implantation is widely used in semiconductor industry with well-controlled dose and precise implantation profile.
{"title":"Self-aligned enhancement-mode AlGaN/GaN HEMTs using 25 keV fluorine ion implantation","authors":"Hongwei Chen, Maojun Wang, K. J. Chen","doi":"10.1109/DRC.2010.5551879","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551879","url":null,"abstract":"Owing to superior physical properties such as high electron saturation velocity and high electric breakdown field, GaN-based high electron mobility transistors (HEMTs) are capable of delivering superior performance in microwave amplifiers, high power switches, and high temperature integrated circuits (ICs). Compared to the conventional D-mode HEMTs with negative threshold voltages, enhancement-mode (E-mode) or normally-off HEMTs are desirable in these applications, for reduced circuit design complexity and fail-safe operation. Fluorine plasma treatment has been used to fabricate E-mode HEMTs [1], and is a robust process for the channel threshold voltage modulation. However, there is no standard equipment for this process and various groups have reported a wide range of process parameters [1–4]. In this work, we demonstrate the self-aligned enhancement-mode AlGaN/GaN HEMTs fabricated with a standard fluorine ion implantation. Ion implantation is widely used in semiconductor industry with well-controlled dose and precise implantation profile.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"601 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133071114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551985
D. Dai, J. Bowers, Zhiwen Lu, J. Campbell, Yimin Kang
By combining Si (with a low k-value, <0.1) and Ge (with a high absorption in the infrared range), Ge/Si photodetectors have been demonstrated with high performances [1–2]. Since data-com transceivers are typically operated up to 70°C [3], it is important to characterize the temperature dependence of the photodetectors and to reduce the temperature dependence. However, very little work has been done for analyzing the temperature dependence of Ge/Si SACM APDs. In this paper, we present the characterization of normal-incidence Ge/Si SACM APDs from 10°C to 60°C. Fig. 1 (a) shows the cross section of the present normal-incidence SACM Ge/Si APD, which is the same as that in Ref. [1]. In our experiment, the APD sample has a diameter D=30µm and operated at the wavelength λ=1300nm. Fig. 2 shows the measured dark currents (see the dotted curves) at different temperatures as the bias voltage increases. The I-V curves for the case with an optical illumination of P= −20dBm are also shown in the same figure to give a comparison (see the dashed curves). In our experiment, the temperature ranged from −73°C to 27°C. As the temperature decreases, not only the dark current level changes but also the breakdown voltage decreases. Here the breakdown voltage Vbd is defined as the voltage where the dark current is 100µA. The temperature dependence of the breakdown voltage Vbd is then shown in the inset. One sees that the voltage Vbd increases with the temperature. This is due to the temperature dependence of phonon scattering [4]. Fig. 33 shows the dark current Idark (in logarithmic scale) versus 1/(kT) for different bias voltages. The dark current increases by nearly a factor 2 every 10 °C when Vbias= −15V, which is similar to that for a Ge-Si PIN photodiode shown in Ref. [3]. We have also measured the dark current from 200K–300K. Fig. 4 shows the activation energy extracted from dark current versus temperature, using the relation Id∞T2exp(-Ea /kT). The activation energy decreases as bias voltage increases. This can be explained as follows. At higher bias voltages, the depletion layer becomes wider and consequently the G-R in the space charge region increases. Thus, the dominant source of the dark current becomes the G-R current, which is less sensitive to the temperature.
{"title":"Temperature dependence of Ge/Si avalanche photodiodes","authors":"D. Dai, J. Bowers, Zhiwen Lu, J. Campbell, Yimin Kang","doi":"10.1109/DRC.2010.5551985","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551985","url":null,"abstract":"By combining Si (with a low k-value, <0.1) and Ge (with a high absorption in the infrared range), Ge/Si photodetectors have been demonstrated with high performances [1–2]. Since data-com transceivers are typically operated up to 70°C [3], it is important to characterize the temperature dependence of the photodetectors and to reduce the temperature dependence. However, very little work has been done for analyzing the temperature dependence of Ge/Si SACM APDs. In this paper, we present the characterization of normal-incidence Ge/Si SACM APDs from 10°C to 60°C. Fig. 1 (a) shows the cross section of the present normal-incidence SACM Ge/Si APD, which is the same as that in Ref. [1]. In our experiment, the APD sample has a diameter D=30µm and operated at the wavelength λ=1300nm. Fig. 2 shows the measured dark currents (see the dotted curves) at different temperatures as the bias voltage increases. The I-V curves for the case with an optical illumination of P= −20dBm are also shown in the same figure to give a comparison (see the dashed curves). In our experiment, the temperature ranged from −73°C to 27°C. As the temperature decreases, not only the dark current level changes but also the breakdown voltage decreases. Here the breakdown voltage Vbd is defined as the voltage where the dark current is 100µA. The temperature dependence of the breakdown voltage Vbd is then shown in the inset. One sees that the voltage Vbd increases with the temperature. This is due to the temperature dependence of phonon scattering [4]. Fig. 33 shows the dark current Idark (in logarithmic scale) versus 1/(kT) for different bias voltages. The dark current increases by nearly a factor 2 every 10 °C when Vbias= −15V, which is similar to that for a Ge-Si PIN photodiode shown in Ref. [3]. We have also measured the dark current from 200K–300K. Fig. 4 shows the activation energy extracted from dark current versus temperature, using the relation Id∞T2exp(-Ea /kT). The activation energy decreases as bias voltage increases. This can be explained as follows. At higher bias voltages, the depletion layer becomes wider and consequently the G-R in the space charge region increases. Thus, the dominant source of the dark current becomes the G-R current, which is less sensitive to the temperature.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551905
Yeqing Lu, A. Seabaugh, P. Fay, S. Koester, S. Laux, W. Haensch, S. Koswatta
Tunneling field-effect transistors (TFETs) are attracting a lot of interest because of their potential to reduce power dissipation in logic applications [1–3]. Performance of TFETs is expected to improve with increasing electrostatic control as provided by ultra-thin body (UTB) based single-gate (SG), double-gate (DG), and nanowire based gate-all-around (GAA) structures, respectively (Fig. 1) [4]. Increasing geometrical confinement, however, could also lead to significant quantum confinement effects [4, 5], especially in III–V materials, which is detrimental to TFET performance. A previous study compared the operation of InAs based SG, DG, and GAA TFETs using quantum transport simulations [4]. Because of the use of the tight-binding model for the device structure in [4], however, the important tradeoff between electrostatics vs. quantum confinement in different geometries could not be clearly distinguished. In this work, we use detailed analytical calculations to compare the operation of SG, DG, and GAA TFETs in InAs (Fig. 1), and examine the competing effects of electrostatics vs. quantum confinement. We demonstrate an important tradeoff between the superior electrostatic control vs. current injection efficiency in TFETs with increasing lateral confinement, which will be an essential consideration for future TFET design.
{"title":"Geometry dependent tunnel FET performance - dilemma of electrostatics vs. quantum confinement","authors":"Yeqing Lu, A. Seabaugh, P. Fay, S. Koester, S. Laux, W. Haensch, S. Koswatta","doi":"10.1109/DRC.2010.5551905","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551905","url":null,"abstract":"Tunneling field-effect transistors (TFETs) are attracting a lot of interest because of their potential to reduce power dissipation in logic applications [1–3]. Performance of TFETs is expected to improve with increasing electrostatic control as provided by ultra-thin body (UTB) based single-gate (SG), double-gate (DG), and nanowire based gate-all-around (GAA) structures, respectively (Fig. 1) [4]. Increasing geometrical confinement, however, could also lead to significant quantum confinement effects [4, 5], especially in III–V materials, which is detrimental to TFET performance. A previous study compared the operation of InAs based SG, DG, and GAA TFETs using quantum transport simulations [4]. Because of the use of the tight-binding model for the device structure in [4], however, the important tradeoff between electrostatics vs. quantum confinement in different geometries could not be clearly distinguished. In this work, we use detailed analytical calculations to compare the operation of SG, DG, and GAA TFETs in InAs (Fig. 1), and examine the competing effects of electrostatics vs. quantum confinement. We demonstrate an important tradeoff between the superior electrostatic control vs. current injection efficiency in TFETs with increasing lateral confinement, which will be an essential consideration for future TFET design.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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