Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551882
M. Rodwell, W. Frensley, S. Steiger, E. Chagarov, S. Lee, H. Ryu, Y. Tan, G. Hegde, L. Wang, J. Law, T. Boykin, G. Klimek, P. Asbeck, A. Kummel, J. Schulman
III–V FETs are being developed for potential application in 0.3–3 THz systems and VLSI. To increase bandwidth, we must increase the drive current Id = qns vinjWg per unit gate width Wg, requiring both high sheet carrier concentrations ns and high injection velocities vinj. Present III–V NFETs restrict control region transport to the single isotropic Γ band minimum. As the gate dielectric is thinned, Id becomes limited by the effective mass m*, and is only increased by using materials with increased m* and hence increased transit times.1 The deep wavefunction also makes Γ -valley transport in low-m*materials unsuitable for < 22-nm gate length (Lg) FETs. Yet, the L-valleys in many III–V materials2 have very low transverse mt and very high longitudinal mass m1. L-valley bound state energies depend upon orientation, and the directions of confinement, growth, and transport can be chosen to selectively populate valleys having low mass in the transport direction3,4. The high perpendicular mass permits placement of multiple quantum wells spaced by a few nm, or population of multiple states of a thicker well spaced by ∼10–100 meV. Using combinations of Γ and L valleys, ns can be increased, m* kept low, and vertical confinement improved, key requirements for <20-nm Lg III–V FETs.
{"title":"III–V FET channel designs for high current densities and thin inversion layers","authors":"M. Rodwell, W. Frensley, S. Steiger, E. Chagarov, S. Lee, H. Ryu, Y. Tan, G. Hegde, L. Wang, J. Law, T. Boykin, G. Klimek, P. Asbeck, A. Kummel, J. Schulman","doi":"10.1109/DRC.2010.5551882","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551882","url":null,"abstract":"III–V FETs are being developed for potential application in 0.3–3 THz systems and VLSI. To increase bandwidth, we must increase the drive current I<inf>d</inf> = qn<inf>s</inf> v<inf>inj</inf>W<inf>g</inf> per unit gate width W<inf>g</inf>, requiring both high sheet carrier concentrations n<inf>s</inf> and high injection velocities v<inf>inj</inf>. Present III–V NFETs restrict control region transport to the single isotropic Γ band minimum. As the gate dielectric is thinned, I<inf>d</inf> becomes limited by the effective mass m*, and is only increased by using materials with increased m* and hence increased transit times.<sup>1</sup> The deep wavefunction also makes Γ -valley transport in low-m*materials unsuitable for < 22-nm gate length (L<inf>g</inf>) FETs. Yet, the L-valleys in many III–V materials<sup>2</sup> have very low transverse m<inf>t</inf> and very high longitudinal mass m<inf>1</inf>. L-valley bound state energies depend upon orientation, and the directions of confinement, growth, and transport can be chosen to selectively populate valleys having low mass in the transport direction<sup>3,4</sup>. The high perpendicular mass permits placement of multiple quantum wells spaced by a few nm, or population of multiple states of a thicker well spaced by ∼10–100 meV. Using combinations of Γ and L valleys, n<inf>s</inf> can be increased, m* kept low, and vertical confinement improved, key requirements for <20-nm L<inf>g</inf> III–V FETs.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114541569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551977
R. Sporea, M. Trainor, N. Young, J. Shannon, S. Silva
The source-gated transistor (SGT) is a new type of transistor in which the current is controlled by a potential barrier at the source and by a gate which modulates the effective height of the source barrier. It is an ideal device architecture to be used with the low mobility materials typically applied to large area electronics, as it provides low saturation voltages and high output impedances. Furthermore, the high internal fields and low concentration of excess carriers lead to higher speed and better stability compared with FETs, particularly in disordered, low mobility semiconductors. As such, the SGT is especially well suited to thin-film analog circuits.
{"title":"Performance improvements in polysilicon source-gated transistors","authors":"R. Sporea, M. Trainor, N. Young, J. Shannon, S. Silva","doi":"10.1109/DRC.2010.5551977","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551977","url":null,"abstract":"The source-gated transistor (SGT) is a new type of transistor in which the current is controlled by a potential barrier at the source and by a gate which modulates the effective height of the source barrier. It is an ideal device architecture to be used with the low mobility materials typically applied to large area electronics, as it provides low saturation voltages and high output impedances. Furthermore, the high internal fields and low concentration of excess carriers lead to higher speed and better stability compared with FETs, particularly in disordered, low mobility semiconductors. As such, the SGT is especially well suited to thin-film analog circuits.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115161933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551961
L. Chu, R. Chu, C. A. Lin, T. Lin, T. Chiang, J. Kwo, M. Hong
When channel materials other than Si are being considered to enhance the carrier mobility, Ge has always been one viable candidate since it possesses higher carrier mobility than those of Si. However, it is difficult to achieve a high-quality oxide/Ge interface comparable to SiO2/Si due to unfavorable surface properties and water-soluble native oxides of Ge. Over the past 4–5 years, two major techniques have been shown to effectively passivate the Ge surface by utilizing Si(SiO2) [1] and thermally grown stoichiometric GeO2 [2,3] as the passivation layers, thus giving low Dit's of ∼1011 cm−2eV−1. However, the use of the interfacial passivation layers (IPL) encountered a major hindrance primarily due to their relatively lower к values which have an adverse effect on the critical requirement of great reduction of equivalent oxide thickness (EOT) for future CMOS applications. An effective approach to achieve the ultimate EOT down-scaling is to directly deposit high-к dielectrics on Ge without IPLs, while maintaining a high к value and decent oxide/Ge interface quality.
{"title":"Achieving high-performance Ge MOS devices using high-к gate dielectrics Ga2O3(Gd2O3) of sub-nm EOT","authors":"L. Chu, R. Chu, C. A. Lin, T. Lin, T. Chiang, J. Kwo, M. Hong","doi":"10.1109/DRC.2010.5551961","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551961","url":null,"abstract":"When channel materials other than Si are being considered to enhance the carrier mobility, Ge has always been one viable candidate since it possesses higher carrier mobility than those of Si. However, it is difficult to achieve a high-quality oxide/Ge interface comparable to SiO<inf>2</inf>/Si due to unfavorable surface properties and water-soluble native oxides of Ge. Over the past 4–5 years, two major techniques have been shown to effectively passivate the Ge surface by utilizing Si(SiO<inf>2</inf>) [1] and thermally grown stoichiometric GeO<inf>2</inf> [2,3] as the passivation layers, thus giving low D<inf>it</inf>'s of ∼10<sup>11</sup> cm<sup>−2</sup>eV<sup>−1</sup>. However, the use of the interfacial passivation layers (IPL) encountered a major hindrance primarily due to their relatively lower к values which have an adverse effect on the critical requirement of great reduction of equivalent oxide thickness (EOT) for future CMOS applications. An effective approach to achieve the ultimate EOT down-scaling is to directly deposit high-к dielectrics on Ge without IPLs, while maintaining a high к value and decent oxide/Ge interface quality.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115031902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551978
B. Bayraktaroglu, K. Leedy
Nanocrystalline ZnO (nc-ZnO) thin film transistors (TFT) are being developed for applications that require much higher performance than TFTs available from other all thin film technologies. Because of their unique closely packed nanocolumnar structures, uniform quality nc-ZnO films can be fabricated over large non-conformal surfaces. Excellent performance characteristics were demonstrated with devices fabricated on GaAs1 and Si2 substrates. Devices with 2µm gate lengths had field effect mobilities in excess of 100 cm2/V.s, drain current on/off ratios of better than 1012, transconductance of 80mS/mm and current densities higher than 400mA/mm. High frequency cut-off frequency values of fT=2.45GHz and fmax=7.45GHz were demonstrated with 1.2µm gate length devices.
{"title":"Growth temperature influence on nanocrystalline ZnO thin film FET performance","authors":"B. Bayraktaroglu, K. Leedy","doi":"10.1109/DRC.2010.5551978","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551978","url":null,"abstract":"Nanocrystalline ZnO (nc-ZnO) thin film transistors (TFT) are being developed for applications that require much higher performance than TFTs available from other all thin film technologies. Because of their unique closely packed nanocolumnar structures, uniform quality nc-ZnO films can be fabricated over large non-conformal surfaces. Excellent performance characteristics were demonstrated with devices fabricated on GaAs1 and Si2 substrates. Devices with 2µm gate lengths had field effect mobilities in excess of 100 cm2/V.s, drain current on/off ratios of better than 1012, transconductance of 80mS/mm and current densities higher than 400mA/mm. High frequency cut-off frequency values of fT=2.45GHz and fmax=7.45GHz were demonstrated with 1.2µm gate length devices.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128267812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551857
J. Shaw, H. Tseng, S. Rajwade, Lieh-Ting Tung, R. Buhrman, E. Kan
Magnetic tunnel junction (MTJ) has attracted great interest due to its high tunneling magnetoresistance (TMR) ratio,1 where sputter deposition of MgO between CoFeB electrodes is a strong candidate. The improvement in TMR is believed to result from B diffusion into the MgO to form a polycrystalline Mg-B-O layer with a shaper interface after annealing.2 Decrease in trap states can lead to smaller leakage currents and improvement in tunneling conductance. Therefore, a thorough electrical characterization on the CoFeB/Mg-B-O quality is crucial to model the TMR increase and associated reliability. Although the trap charge in the MTJ structure will change the tunneling path and cause serious parametric drift, it is difficult to directly measure its magnitude. Instead, we made CoFeB/MgO/Si MOS capacitors with process flow illustrated in Fig. 1, which can independently determine the interface traps, oxide charge and stress-induced leakage current (SILC) through conductance, high-frequency capacitance-voltage (HFCV) and IV measurements. We can then characterize the boron diffusion and annealing effects on Mg-B-O.
{"title":"Interface and oxide quality of CoFeB/MgO/Si tunnel junctions","authors":"J. Shaw, H. Tseng, S. Rajwade, Lieh-Ting Tung, R. Buhrman, E. Kan","doi":"10.1109/DRC.2010.5551857","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551857","url":null,"abstract":"Magnetic tunnel junction (MTJ) has attracted great interest due to its high tunneling magnetoresistance (TMR) ratio,1 where sputter deposition of MgO between CoFeB electrodes is a strong candidate. The improvement in TMR is believed to result from B diffusion into the MgO to form a polycrystalline Mg-B-O layer with a shaper interface after annealing.2 Decrease in trap states can lead to smaller leakage currents and improvement in tunneling conductance. Therefore, a thorough electrical characterization on the CoFeB/Mg-B-O quality is crucial to model the TMR increase and associated reliability. Although the trap charge in the MTJ structure will change the tunneling path and cause serious parametric drift, it is difficult to directly measure its magnitude. Instead, we made CoFeB/MgO/Si MOS capacitors with process flow illustrated in Fig. 1, which can independently determine the interface traps, oxide charge and stress-induced leakage current (SILC) through conductance, high-frequency capacitance-voltage (HFCV) and IV measurements. We can then characterize the boron diffusion and annealing effects on Mg-B-O.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"515 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132755025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551887
V. Jain, E. Lobisser, A. Baraskar, B. Thibeault, M. Rodwell, Z. Griffith, M. Urteaga, S. Bartsch, D. Loubychev, A. Snyder, Y. Wu, J. Fastenau, W.K. Liu
We report a 110 nm InP/In0.53Ga0.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating a simultaneous ft/fmax of 465/660 GHz and operating at power densities in excess of 50 mW/µm2. To our knowledge this is the smallest junction width reported for a III–V DHBT. The narrow 110 nm emitter junction permits the devices to be biased simultaneously at high voltages and high current densities (Je) with peak RF performance at 41 mW/µm2 (Je = 23.6 mA/µm2, Vce = 1.75 V). Devices incorporate low contact resistance, refractory, in-situ Mo emitter contact to a highly doped, regrown InGaAs cap. A low stress, sputter deposited, refractory, dry-etched W/Ti0.1W0.9 emitter metal process was developed demonstrating both high emitter yield and scalability to sub-100 nm junctions. Previously reported dry etch processes involving Ti/Ti0.1W0.9 metals could not be scaled below 180 nm junction widths due to high metal stress resulting in very low emitter yield [1, 2]. The emitter metal contacts reported here are 100 nm wide and the emitter-base junction width is 110 nm. On-wafer Through-Reflect-Line (TRL) calibration structures were used to measure the RF performance of devices from 140 – 180 GHz.
{"title":"High performance 110 nm InGaAs/InP DHBTs in dry-etched in-situ refractory emitter contact technology","authors":"V. Jain, E. Lobisser, A. Baraskar, B. Thibeault, M. Rodwell, Z. Griffith, M. Urteaga, S. Bartsch, D. Loubychev, A. Snyder, Y. Wu, J. Fastenau, W.K. Liu","doi":"10.1109/DRC.2010.5551887","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551887","url":null,"abstract":"We report a 110 nm InP/In<inf>0.53</inf>Ga<inf>0.47</inf>As/InP double heterojunction bipolar transistor (DHBT) demonstrating a simultaneous f<inf>t</inf>/f<inf>max</inf> of 465/660 GHz and operating at power densities in excess of 50 mW/µm<sup>2</sup>. To our knowledge this is the smallest junction width reported for a III–V DHBT. The narrow 110 nm emitter junction permits the devices to be biased simultaneously at high voltages and high current densities (J<inf>e</inf>) with peak RF performance at 41 mW/µm<sup>2</sup> (J<inf>e</inf> = 23.6 mA/µm<sup>2</sup>, V<inf>ce</inf> = 1.75 V). Devices incorporate low contact resistance, refractory, in-situ Mo emitter contact to a highly doped, regrown InGaAs cap. A low stress, sputter deposited, refractory, dry-etched W/Ti<inf>0.1</inf>W<inf>0.9</inf> emitter metal process was developed demonstrating both high emitter yield and scalability to sub-100 nm junctions. Previously reported dry etch processes involving Ti/Ti<inf>0.1</inf>W<inf>0.9</inf> metals could not be scaled below 180 nm junction widths due to high metal stress resulting in very low emitter yield [1, 2]. The emitter metal contacts reported here are 100 nm wide and the emitter-base junction width is 110 nm. On-wafer Through-Reflect-Line (TRL) calibration structures were used to measure the RF performance of devices from 140 – 180 GHz.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133446793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551860
H. George, A. Orlov, G. Snider
Single electron tunneling transistors (SETs) are the most sensitive electrometers available, capable of measuring small fractions of electron charge, with sensitivities down to 10−6 e/√Hz [1]. This makes the SET the best device for applications which require sensing of small changes of charge in nanostructures. Typically, an SET is used to measure the change in charge within a system while some external voltage Vin is swept, Fig. 1. Since there is a parasitic capacitance, Cp, between the sweeping voltage and the SET, to keep the operating point of the SET stable, a compensating voltage, Vcanc, is added to the SET gate in order to cancel the effect of the sweeping voltage. Ideally, this makes the SET immune to the changes in sweeping voltage so that it only responds to other charge fluctuations in the surrounding area. This cancellation scheme is used in many applications where charge transfer events (Fig. 1) are induced by large external electric fields such as the charging of a memory node in single electron memory devices [2]. The majority of metal based SETs to date are fabricated on oxidized silicon substrates. However, for devices fabricated on oxidized Si substrates, the charge cancellation scheme breaks down once a certain threshold is exceeded and charging effects on the SET island are not controlled (Fig. 2a). These charging processes are revealed as Coulomb blockade oscillations (CBOs), which continue even when the gate voltage ramp is stopped. We believe that inversion/accumulation regions are created under the gate electrodes in the semiconductor substrate while the device is operating. This effect will mask the charge transfer events of interest that the SET is intended to detect; instead, the SET detects the parasitic charging from the semiconducting substrate.
{"title":"Substrate effects on metal-oxide single electron transistors electrometer measurements.","authors":"H. George, A. Orlov, G. Snider","doi":"10.1109/DRC.2010.5551860","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551860","url":null,"abstract":"Single electron tunneling transistors (SETs) are the most sensitive electrometers available, capable of measuring small fractions of electron charge, with sensitivities down to 10−6 e/√Hz [1]. This makes the SET the best device for applications which require sensing of small changes of charge in nanostructures. Typically, an SET is used to measure the change in charge within a system while some external voltage Vin is swept, Fig. 1. Since there is a parasitic capacitance, Cp, between the sweeping voltage and the SET, to keep the operating point of the SET stable, a compensating voltage, Vcanc, is added to the SET gate in order to cancel the effect of the sweeping voltage. Ideally, this makes the SET immune to the changes in sweeping voltage so that it only responds to other charge fluctuations in the surrounding area. This cancellation scheme is used in many applications where charge transfer events (Fig. 1) are induced by large external electric fields such as the charging of a memory node in single electron memory devices [2]. The majority of metal based SETs to date are fabricated on oxidized silicon substrates. However, for devices fabricated on oxidized Si substrates, the charge cancellation scheme breaks down once a certain threshold is exceeded and charging effects on the SET island are not controlled (Fig. 2a). These charging processes are revealed as Coulomb blockade oscillations (CBOs), which continue even when the gate voltage ramp is stopped. We believe that inversion/accumulation regions are created under the gate electrodes in the semiconductor substrate while the device is operating. This effect will mask the charge transfer events of interest that the SET is intended to detect; instead, the SET detects the parasitic charging from the semiconducting substrate.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"33 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130536675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551872
R. Ghandi, B. Bouno, M. Domeij, S. Shayestehaminzadeh, C. Zetterling, M. Ostling
The 4H-SiC bipolar junction transistors (BJT) are considered as efficient high power switching devices due to the ability of obtaining very low specific on-resistance compared to FET based devices. However, one drawback with the present high voltage BJTs is the relatively low current gain. To reduce the power required by the drive circuit, it is important to increase the common-emitter current gain (β). 4H-SiC (0001) Si-face has become a favorable plane for vertical power BJTs with epitaxial layers that shows higher mobility along the c-axis and provides higher current gain [1]. Furthermore, important progress on improving the current gain focused on the quality of surface passivation at the SiC/SiO2 interface has been reported during previous years [2–3]. Higher quality of passivation can provide less interface traps and thereby minimizes the surface recombination current. Conventionally, vertical 4H-SiC BJTs are fabricated along the [11̲00] direction on (0001) Si-face. However due to anisotropic properties of 4H-SiC, different orientations on Si-face can also affect the base current of the BJT through variation of mobility and interface traps density distribution along each direction. In this work, single-finger small area BJTs are fabricated on (0001) Si-face along [12̲10], [011̲0], [112̲0] and [11̲00] directions. This design can provide various orientations of BJTs that corresponds to an angular range between 0 to 180 degrees relative to conventional [11̲00] direction. The goal was to find a correlation between different crystallographic orientation, mobility and interface traps density distribution through transistor characteristics and finally comparison with simulation. Fig.1 shows a cross section and top view of fabricated BJTs. The n+ emitter epi-layer is 1.35 µm nitrogen doped to 6×1018 cm−3 and capped by 200-nm-thick 2×1019 cm−3 layer. The base epi-layer is 650 nm Al-doped with concentration of 4.3×1017 cm−3. The drift n− epilayer is 20 µm thick and doped to 6×1015 cm−3. Inductively coupled plasma (ICP) etching with an oxide mask was used to form emitter and base mesas. Fig.2 is a comparison of the maximum current gain with different orientations normalized to the maximum current gain along [11̲00] before surface passivation and contact metallization. The results indicate that the maximum current gain is orientation-dependent and has a maximum for BJTs with the emitter edge aligned to the [112̲0] direction. The variation effect of planar mobility and interface traps concentration on the current gain is simulated based on the previous work [4] and is illustrated in Fig.3. The simulation shows that interface oxide charges has more influence on the current gain compared to the mobility and higher current gain is attributed to lower oxide interface charges. The orientation dependence of the transistor parameters such as maximum current gain after passivation and the base resistance will be evaluated and compared with simulation.
{"title":"Influence of crystal orientation on the current gain in 4H-SiC BJTs","authors":"R. Ghandi, B. Bouno, M. Domeij, S. Shayestehaminzadeh, C. Zetterling, M. Ostling","doi":"10.1109/DRC.2010.5551872","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551872","url":null,"abstract":"The 4H-SiC bipolar junction transistors (BJT) are considered as efficient high power switching devices due to the ability of obtaining very low specific on-resistance compared to FET based devices. However, one drawback with the present high voltage BJTs is the relatively low current gain. To reduce the power required by the drive circuit, it is important to increase the common-emitter current gain (β). 4H-SiC (0001) Si-face has become a favorable plane for vertical power BJTs with epitaxial layers that shows higher mobility along the c-axis and provides higher current gain [1]. Furthermore, important progress on improving the current gain focused on the quality of surface passivation at the SiC/SiO2 interface has been reported during previous years [2–3]. Higher quality of passivation can provide less interface traps and thereby minimizes the surface recombination current. Conventionally, vertical 4H-SiC BJTs are fabricated along the [11̲00] direction on (0001) Si-face. However due to anisotropic properties of 4H-SiC, different orientations on Si-face can also affect the base current of the BJT through variation of mobility and interface traps density distribution along each direction. In this work, single-finger small area BJTs are fabricated on (0001) Si-face along [12̲10], [011̲0], [112̲0] and [11̲00] directions. This design can provide various orientations of BJTs that corresponds to an angular range between 0 to 180 degrees relative to conventional [11̲00] direction. The goal was to find a correlation between different crystallographic orientation, mobility and interface traps density distribution through transistor characteristics and finally comparison with simulation. Fig.1 shows a cross section and top view of fabricated BJTs. The n+ emitter epi-layer is 1.35 µm nitrogen doped to 6×1018 cm−3 and capped by 200-nm-thick 2×1019 cm−3 layer. The base epi-layer is 650 nm Al-doped with concentration of 4.3×1017 cm−3. The drift n− epilayer is 20 µm thick and doped to 6×1015 cm−3. Inductively coupled plasma (ICP) etching with an oxide mask was used to form emitter and base mesas. Fig.2 is a comparison of the maximum current gain with different orientations normalized to the maximum current gain along [11̲00] before surface passivation and contact metallization. The results indicate that the maximum current gain is orientation-dependent and has a maximum for BJTs with the emitter edge aligned to the [112̲0] direction. The variation effect of planar mobility and interface traps concentration on the current gain is simulated based on the previous work [4] and is illustrated in Fig.3. The simulation shows that interface oxide charges has more influence on the current gain compared to the mobility and higher current gain is attributed to lower oxide interface charges. The orientation dependence of the transistor parameters such as maximum current gain after passivation and the base resistance will be evaluated and compared with simulation.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"592 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123421715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551933
Q. Zhang, Y. Lu, G. Xing, C. Richter, S. Koester, S. Koswatta
On the ITRS roadmap [1], the physical gate length, LG, has been rapidly scaling down, and will reach values below ∼ 10nm beyond 2020 (see Table I, shaded region). The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling [2–4]. Nevertheless, sub-10nm LG scaling will be a great challenge because of the significant mobility degradation [5] and channel thickness variations [2] in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-10nm LG scaling. It has been recently shown that the atomic-thin- body (ATB) geometry can meet the electrostatic requirements for LG ≤ 10nm [6]. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps [7] have been widely considered for high-performance digital electronics [8–10]. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently [6], including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. LG scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ∼ 1nm), and larger effective masses obtained from bandstructure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (ION ) [11]. The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap [1].
{"title":"Graphene nanoribbon Schottky-barrier FETs for end-of-the-roadmap CMOS: Challenges and opportunities","authors":"Q. Zhang, Y. Lu, G. Xing, C. Richter, S. Koester, S. Koswatta","doi":"10.1109/DRC.2010.5551933","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551933","url":null,"abstract":"On the ITRS roadmap [1], the physical gate length, LG, has been rapidly scaling down, and will reach values below ∼ 10nm beyond 2020 (see Table I, shaded region). The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling [2–4]. Nevertheless, sub-10nm LG scaling will be a great challenge because of the significant mobility degradation [5] and channel thickness variations [2] in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-10nm LG scaling. It has been recently shown that the atomic-thin- body (ATB) geometry can meet the electrostatic requirements for LG ≤ 10nm [6]. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps [7] have been widely considered for high-performance digital electronics [8–10]. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently [6], including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. LG scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ∼ 1nm), and larger effective masses obtained from bandstructure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (ION ) [11]. The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap [1].","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122152552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551960
G. Cohen, E. Cartier, S. Bangsaruntip, A. Majumdar, W. Haensch, L. Gignac, S. Mittal, J. Sleight
Gate-all-around p-i-n silicon nanowires (NW) diodes with effective nanowire diameter from 15 nm down to 4 nm (±1.3 nm) were fabricated to enable interface state density (Nit) measurements using the charge pumping (CP) method. The Nit of the NWs was also measured by the conductance method and was in good agreement with the CP method. The linear relation between the CP current and the pulse frequency was not maintained in the smallest diameter NWs. The dependency on the pulse rise and fall times was also investigated and is correlated to the lifetime of the traps. The impact of the cylindrical geometry on the measured CP current is discussed.
{"title":"Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter","authors":"G. Cohen, E. Cartier, S. Bangsaruntip, A. Majumdar, W. Haensch, L. Gignac, S. Mittal, J. Sleight","doi":"10.1109/DRC.2010.5551960","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551960","url":null,"abstract":"Gate-all-around p-i-n silicon nanowires (NW) diodes with effective nanowire diameter from 15 nm down to 4 nm (±1.3 nm) were fabricated to enable interface state density (Nit) measurements using the charge pumping (CP) method. The Nit of the NWs was also measured by the conductance method and was in good agreement with the CP method. The linear relation between the CP current and the pulse frequency was not maintained in the smallest diameter NWs. The dependency on the pulse rise and fall times was also investigated and is correlated to the lifetime of the traps. The impact of the cylindrical geometry on the measured CP current is discussed.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128765734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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