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III–V FET channel designs for high current densities and thin inversion layers 高电流密度和薄反转层的III-V场效应管沟道设计
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551882
M. Rodwell, W. Frensley, S. Steiger, E. Chagarov, S. Lee, H. Ryu, Y. Tan, G. Hegde, L. Wang, J. Law, T. Boykin, G. Klimek, P. Asbeck, A. Kummel, J. Schulman
III–V FETs are being developed for potential application in 0.3–3 THz systems and VLSI. To increase bandwidth, we must increase the drive current Id = qns vinjWg per unit gate width Wg, requiring both high sheet carrier concentrations ns and high injection velocities vinj. Present III–V NFETs restrict control region transport to the single isotropic Γ band minimum. As the gate dielectric is thinned, Id becomes limited by the effective mass m*, and is only increased by using materials with increased m* and hence increased transit times.1 The deep wavefunction also makes Γ -valley transport in low-m*materials unsuitable for < 22-nm gate length (Lg) FETs. Yet, the L-valleys in many III–V materials2 have very low transverse mt and very high longitudinal mass m1. L-valley bound state energies depend upon orientation, and the directions of confinement, growth, and transport can be chosen to selectively populate valleys having low mass in the transport direction3,4. The high perpendicular mass permits placement of multiple quantum wells spaced by a few nm, or population of multiple states of a thicker well spaced by ∼10–100 meV. Using combinations of Γ and L valleys, ns can be increased, m* kept low, and vertical confinement improved, key requirements for <20-nm Lg III–V FETs.
III-V型场效应管正在开发中,用于0.3-3太赫兹系统和VLSI的潜在应用。为了增加带宽,我们必须增加每单位栅极宽度Wg的驱动电流Id = qns vinjWg,这需要高载流子浓度ns和高注入速度vinj。目前III-V型非场效应管将控制区域输运限制在单个各向同性Γ最小带。当栅极电介质变薄时,Id受到有效质量m*的限制,并且只有使用增加m*的材料才能增加Id,从而增加传递时间深波函数还使得低m*材料中的Γ -谷输运不适用于< 22 nm栅极长度(Lg)场效应管。然而,许多III-V材料中的l -谷具有非常低的横向mt和非常高的纵向质量m1。l -谷束缚态能量取决于取向,并且可以选择约束、生长和输运的方向来选择性地填充在输运方向上具有低质量的谷3,4。高垂直质量允许放置间隔几nm的多个量子阱,或者间隔约10-100 meV的较厚阱的多个态的填充。使用Γ和L谷的组合,可以增加ns,保持低m*,并改善垂直约束,这是g III-V场效应管的关键要求。
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引用次数: 36
Performance improvements in polysilicon source-gated transistors 多晶硅源门控晶体管的性能改进
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551977
R. Sporea, M. Trainor, N. Young, J. Shannon, S. Silva
The source-gated transistor (SGT) is a new type of transistor in which the current is controlled by a potential barrier at the source and by a gate which modulates the effective height of the source barrier. It is an ideal device architecture to be used with the low mobility materials typically applied to large area electronics, as it provides low saturation voltages and high output impedances. Furthermore, the high internal fields and low concentration of excess carriers lead to higher speed and better stability compared with FETs, particularly in disordered, low mobility semiconductors. As such, the SGT is especially well suited to thin-film analog circuits.
源门控晶体管(SGT)是一种新型晶体管,其电流由源端的势垒和调制源势垒有效高度的栅极控制。它是一种理想的器件结构,用于低迁移率材料,通常应用于大面积电子产品,因为它提供低饱和电压和高输出阻抗。此外,与fet相比,高内部场和低浓度的过量载流子导致更高的速度和更好的稳定性,特别是在无序,低迁移率的半导体中。因此,SGT特别适合于薄膜模拟电路。
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引用次数: 0
Achieving high-performance Ge MOS devices using high-к gate dielectrics Ga2O3(Gd2O3) of sub-nm EOT 采用亚纳米EOT的高栅极介质Ga2O3(Gd2O3)实现高性能Ge MOS器件
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551961
L. Chu, R. Chu, C. A. Lin, T. Lin, T. Chiang, J. Kwo, M. Hong
When channel materials other than Si are being considered to enhance the carrier mobility, Ge has always been one viable candidate since it possesses higher carrier mobility than those of Si. However, it is difficult to achieve a high-quality oxide/Ge interface comparable to SiO2/Si due to unfavorable surface properties and water-soluble native oxides of Ge. Over the past 4–5 years, two major techniques have been shown to effectively passivate the Ge surface by utilizing Si(SiO2) [1] and thermally grown stoichiometric GeO2 [2,3] as the passivation layers, thus giving low Dit's of ∼1011 cm−2eV−1. However, the use of the interfacial passivation layers (IPL) encountered a major hindrance primarily due to their relatively lower к values which have an adverse effect on the critical requirement of great reduction of equivalent oxide thickness (EOT) for future CMOS applications. An effective approach to achieve the ultimate EOT down-scaling is to directly deposit high-к dielectrics on Ge without IPLs, while maintaining a high к value and decent oxide/Ge interface quality.
当考虑除Si以外的通道材料来提高载流子迁移率时,Ge一直是一个可行的候选材料,因为它比Si具有更高的载流子迁移率。然而,由于Ge的表面性质和水溶性天然氧化物的不利,很难获得与SiO2/Si相当的高质量氧化物/Ge界面。在过去的4-5年里,已经有两种主要的技术被证明可以有效地钝化锗表面,即利用Si(SiO2)[1]和热生长的化学测量物GeO2[2,3]作为钝化层,从而获得低Dit,约为1011 cm−2eV−1。然而,界面钝化层(IPL)的使用遇到了主要障碍,主要是由于它们相对较低的值,这对未来CMOS应用中大幅降低等效氧化物厚度(EOT)的关键要求有不利影响。实现最终EOT缩减的有效方法是直接在Ge上沉积高介电体而不使用ipl,同时保持高的介电体值和良好的氧化物/Ge界面质量。
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引用次数: 2
Growth temperature influence on nanocrystalline ZnO thin film FET performance 生长温度对纳米晶ZnO薄膜FET性能的影响
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551978
B. Bayraktaroglu, K. Leedy
Nanocrystalline ZnO (nc-ZnO) thin film transistors (TFT) are being developed for applications that require much higher performance than TFTs available from other all thin film technologies. Because of their unique closely packed nanocolumnar structures, uniform quality nc-ZnO films can be fabricated over large non-conformal surfaces. Excellent performance characteristics were demonstrated with devices fabricated on GaAs1 and Si2 substrates. Devices with 2µm gate lengths had field effect mobilities in excess of 100 cm2/V.s, drain current on/off ratios of better than 1012, transconductance of 80mS/mm and current densities higher than 400mA/mm. High frequency cut-off frequency values of fT=2.45GHz and fmax=7.45GHz were demonstrated with 1.2µm gate length devices.
纳米晶ZnO (nc-ZnO)薄膜晶体管(TFT)正被开发用于比其他全薄膜技术要求更高性能的应用。由于其独特的紧密排列的纳米柱结构,可以在大型非共形表面上制备均匀质量的nc-ZnO薄膜。在GaAs1和Si2衬底上制备的器件表现出优异的性能特征。栅极长度为2 μ m的器件具有超过100 cm2/V的场效应迁移率。s,漏极通断比大于1012,跨导80mS/mm,电流密度大于400mA/mm。采用1.2µm栅极长度器件,得到了fT=2.45GHz和fmax=7.45GHz的高频截止频率值。
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引用次数: 0
Interface and oxide quality of CoFeB/MgO/Si tunnel junctions CoFeB/MgO/Si隧道结的界面和氧化物质量
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551857
J. Shaw, H. Tseng, S. Rajwade, Lieh-Ting Tung, R. Buhrman, E. Kan
Magnetic tunnel junction (MTJ) has attracted great interest due to its high tunneling magnetoresistance (TMR) ratio,1 where sputter deposition of MgO between CoFeB electrodes is a strong candidate. The improvement in TMR is believed to result from B diffusion into the MgO to form a polycrystalline Mg-B-O layer with a shaper interface after annealing.2 Decrease in trap states can lead to smaller leakage currents and improvement in tunneling conductance. Therefore, a thorough electrical characterization on the CoFeB/Mg-B-O quality is crucial to model the TMR increase and associated reliability. Although the trap charge in the MTJ structure will change the tunneling path and cause serious parametric drift, it is difficult to directly measure its magnitude. Instead, we made CoFeB/MgO/Si MOS capacitors with process flow illustrated in Fig. 1, which can independently determine the interface traps, oxide charge and stress-induced leakage current (SILC) through conductance, high-frequency capacitance-voltage (HFCV) and IV measurements. We can then characterize the boron diffusion and annealing effects on Mg-B-O.
磁隧道结(MTJ)由于其高隧道磁电阻(TMR)比而引起了人们的极大兴趣,其中在CoFeB电极之间溅射沉积MgO是一个强有力的候选者。TMR的提高被认为是由于B扩散到MgO中,在退火后形成具有成形界面的多晶Mg-B-O层阱态的减小可以减小漏电流,提高隧道电导。因此,对CoFeB/Mg-B-O质量进行全面的电学表征对于模拟TMR增加和相关可靠性至关重要。虽然MTJ结构中的陷阱电荷会改变隧穿路径并引起严重的参数漂移,但其大小难以直接测量。相反,我们制作了CoFeB/MgO/Si MOS电容器,其工艺流程如图1所示,可以通过电导,高频电容电压(HFCV)和IV测量独立确定界面陷阱,氧化物电荷和应力诱导泄漏电流(SILC)。然后我们可以表征硼在Mg-B-O上的扩散和退火效应。
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引用次数: 1
High performance 110 nm InGaAs/InP DHBTs in dry-etched in-situ refractory emitter contact technology 干蚀刻原位难熔发射极触点技术中的高性能110nm InGaAs/InP dhbt
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551887
V. Jain, E. Lobisser, A. Baraskar, B. Thibeault, M. Rodwell, Z. Griffith, M. Urteaga, S. Bartsch, D. Loubychev, A. Snyder, Y. Wu, J. Fastenau, W.K. Liu
We report a 110 nm InP/In0.53Ga0.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating a simultaneous ft/fmax of 465/660 GHz and operating at power densities in excess of 50 mW/µm2. To our knowledge this is the smallest junction width reported for a III–V DHBT. The narrow 110 nm emitter junction permits the devices to be biased simultaneously at high voltages and high current densities (Je) with peak RF performance at 41 mW/µm2 (Je = 23.6 mA/µm2, Vce = 1.75 V). Devices incorporate low contact resistance, refractory, in-situ Mo emitter contact to a highly doped, regrown InGaAs cap. A low stress, sputter deposited, refractory, dry-etched W/Ti0.1W0.9 emitter metal process was developed demonstrating both high emitter yield and scalability to sub-100 nm junctions. Previously reported dry etch processes involving Ti/Ti0.1W0.9 metals could not be scaled below 180 nm junction widths due to high metal stress resulting in very low emitter yield [1, 2]. The emitter metal contacts reported here are 100 nm wide and the emitter-base junction width is 110 nm. On-wafer Through-Reflect-Line (TRL) calibration structures were used to measure the RF performance of devices from 140 – 180 GHz.
我们报道了110 nm InP/In0.53Ga0.47As/InP双异质结双极晶体管(DHBT),其同时ft/fmax为465/660 GHz,工作功率密度超过50 mW/µm2。据我们所知,这是III-V型DHBT报道的最小结宽。窄的110 nm发射极结允许器件在高电压和高电流密度(Je)下同时偏置,峰值射频性能为41 mW/µm2 (Je = 23.6 mA/µm2, Vce = 1.75 V)。器件将低接触电阻,难熔,原位Mo发射极接触到高掺杂,再生的InGaAs帽。开发了干蚀刻W/Ti0.1W0.9发射极金属工艺,展示了高发射极良率和亚100 nm结的可扩展性。先前报道的涉及Ti/Ti0.1W0.9金属的干式蚀刻工艺由于高金属应力导致极低的发射极产率而无法缩放到180 nm以下的结宽[1,2]。本文报道的发射极金属触点宽度为100nm,发射极-基极结宽度为110nm。采用晶圆通反射线(TRL)校准结构测量140 - 180 GHz器件的射频性能。
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引用次数: 4
Substrate effects on metal-oxide single electron transistors electrometer measurements. 衬底对金属氧化物单电子晶体管静电计测量的影响。
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551860
H. George, A. Orlov, G. Snider
Single electron tunneling transistors (SETs) are the most sensitive electrometers available, capable of measuring small fractions of electron charge, with sensitivities down to 10−6 e/√Hz [1]. This makes the SET the best device for applications which require sensing of small changes of charge in nanostructures. Typically, an SET is used to measure the change in charge within a system while some external voltage Vin is swept, Fig. 1. Since there is a parasitic capacitance, Cp, between the sweeping voltage and the SET, to keep the operating point of the SET stable, a compensating voltage, Vcanc, is added to the SET gate in order to cancel the effect of the sweeping voltage. Ideally, this makes the SET immune to the changes in sweeping voltage so that it only responds to other charge fluctuations in the surrounding area. This cancellation scheme is used in many applications where charge transfer events (Fig. 1) are induced by large external electric fields such as the charging of a memory node in single electron memory devices [2]. The majority of metal based SETs to date are fabricated on oxidized silicon substrates. However, for devices fabricated on oxidized Si substrates, the charge cancellation scheme breaks down once a certain threshold is exceeded and charging effects on the SET island are not controlled (Fig. 2a). These charging processes are revealed as Coulomb blockade oscillations (CBOs), which continue even when the gate voltage ramp is stopped. We believe that inversion/accumulation regions are created under the gate electrodes in the semiconductor substrate while the device is operating. This effect will mask the charge transfer events of interest that the SET is intended to detect; instead, the SET detects the parasitic charging from the semiconducting substrate.
单电子隧道晶体管(set)是目前最灵敏的静电计,能够测量一小部分电子电荷,灵敏度低至10−6 e/√Hz[1]。这使得SET成为需要感应纳米结构中电荷微小变化的应用的最佳设备。通常,SET用于测量当某些外部电压被扫频时系统内电荷的变化,如图1所示。由于在扫频电压和SET之间存在寄生电容Cp,为了保持SET工作点的稳定,在SET栅极上增加一个补偿电压Vcanc,以抵消扫频电压的影响。理想情况下,这使得SET不受扫频电压变化的影响,因此它只响应周围区域的其他电荷波动。这种抵消方案在许多应用中使用,其中电荷转移事件(图1)是由大的外部电场引起的,例如单电子存储器件[2]中存储节点的充电。迄今为止,大多数金属基set都是在氧化硅衬底上制造的。然而,对于在氧化硅衬底上制造的器件,一旦超过一定阈值,电荷抵消方案就会失效,并且SET岛上的电荷效应无法控制(图2a)。这些充电过程显示为库仑阻塞振荡(cbo),即使栅极电压斜坡停止,这种振荡也会继续。我们认为,当器件工作时,在半导体衬底的栅电极下会产生反转/积累区域。这种效应将掩盖SET要检测的感兴趣的电荷转移事件;相反,SET检测来自半导体衬底的寄生电荷。
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引用次数: 0
Influence of crystal orientation on the current gain in 4H-SiC BJTs 晶体取向对4H-SiC BJTs电流增益的影响
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551872
R. Ghandi, B. Bouno, M. Domeij, S. Shayestehaminzadeh, C. Zetterling, M. Ostling
The 4H-SiC bipolar junction transistors (BJT) are considered as efficient high power switching devices due to the ability of obtaining very low specific on-resistance compared to FET based devices. However, one drawback with the present high voltage BJTs is the relatively low current gain. To reduce the power required by the drive circuit, it is important to increase the common-emitter current gain (β). 4H-SiC (0001) Si-face has become a favorable plane for vertical power BJTs with epitaxial layers that shows higher mobility along the c-axis and provides higher current gain [1]. Furthermore, important progress on improving the current gain focused on the quality of surface passivation at the SiC/SiO2 interface has been reported during previous years [2–3]. Higher quality of passivation can provide less interface traps and thereby minimizes the surface recombination current. Conventionally, vertical 4H-SiC BJTs are fabricated along the [11̲00] direction on (0001) Si-face. However due to anisotropic properties of 4H-SiC, different orientations on Si-face can also affect the base current of the BJT through variation of mobility and interface traps density distribution along each direction. In this work, single-finger small area BJTs are fabricated on (0001) Si-face along [12̲10], [011̲0], [112̲0] and [11̲00] directions. This design can provide various orientations of BJTs that corresponds to an angular range between 0 to 180 degrees relative to conventional [11̲00] direction. The goal was to find a correlation between different crystallographic orientation, mobility and interface traps density distribution through transistor characteristics and finally comparison with simulation. Fig.1 shows a cross section and top view of fabricated BJTs. The n+ emitter epi-layer is 1.35 µm nitrogen doped to 6×1018 cm−3 and capped by 200-nm-thick 2×1019 cm−3 layer. The base epi-layer is 650 nm Al-doped with concentration of 4.3×1017 cm−3. The drift n− epilayer is 20 µm thick and doped to 6×1015 cm−3. Inductively coupled plasma (ICP) etching with an oxide mask was used to form emitter and base mesas. Fig.2 is a comparison of the maximum current gain with different orientations normalized to the maximum current gain along [11̲00] before surface passivation and contact metallization. The results indicate that the maximum current gain is orientation-dependent and has a maximum for BJTs with the emitter edge aligned to the [112̲0] direction. The variation effect of planar mobility and interface traps concentration on the current gain is simulated based on the previous work [4] and is illustrated in Fig.3. The simulation shows that interface oxide charges has more influence on the current gain compared to the mobility and higher current gain is attributed to lower oxide interface charges. The orientation dependence of the transistor parameters such as maximum current gain after passivation and the base resistance will be evaluated and compared with simulation.
与基于FET的器件相比,4H-SiC双极结晶体管(BJT)能够获得非常低的比导通电阻,因此被认为是高效的高功率开关器件。然而,目前高压bjt的一个缺点是相对较低的电流增益。为了降低驱动电路所需的功率,增加共发射极电流增益(β)是很重要的。4H-SiC (0001) Si-face已成为具有外延层的垂直功率bjt的有利平面,其沿c轴具有更高的迁移率并提供更高的电流增益[1]。此外,在提高SiC/SiO2界面表面钝化质量的电流增益方面也取得了重要进展[2-3]。高质量的钝化可以提供更少的界面陷阱,从而最小化表面复合电流。传统上,垂直的4H-SiC bjt是在(0001)si面上沿[11 × 00]方向制造的。然而,由于4H-SiC的各向异性,硅面的不同取向也会通过改变每个方向的迁移率和界面陷阱密度分布来影响BJT的基极电流。在这项工作中,单指小面积bjt沿[12 10],[011 0],[112 0]和[11 00]方向在(0001)si面上制作。这种设计可以提供不同的bjt方向,对应于相对于传统方向0到180度的角度范围。目的是通过晶体管特性找到不同晶体取向、迁移率和界面陷阱密度分布之间的相关性,并最终与模拟进行比较。图1显示了制造的bjt的截面和俯视图。n+发射极外延层是1.35 μ m的氮掺杂到6×1018 cm−3,并覆盖200 nm厚的2×1019 cm−3层。基底外延层为650 nm掺铝,浓度为4.3×1017 cm−3。漂移层厚度为20µm,掺杂浓度为6×1015 cm−3。采用电感耦合等离子体(ICP)腐蚀氧化掩膜形成发射极和基极。图2为表面钝化和接触金属化前沿[11 × 00]方向的最大电流增益归一化对比图。结果表明,最大电流增益与方向有关,并且当发射极边缘对准[112 * 0]方向时,bjt具有最大电流增益。在前人研究[4]的基础上,模拟了平面迁移率和界面陷阱浓度对电流增益的变化效应,如图3所示。仿真结果表明,界面氧化电荷比迁移率对电流增益的影响更大,且界面氧化电荷越低,电流增益越高。对晶体管参数(如钝化后的最大电流增益和基极电阻)的方向依赖性进行了评估,并与仿真结果进行了比较。
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引用次数: 0
Graphene nanoribbon Schottky-barrier FETs for end-of-the-roadmap CMOS: Challenges and opportunities 石墨烯纳米带肖特基势垒场效应管:挑战与机遇
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551933
Q. Zhang, Y. Lu, G. Xing, C. Richter, S. Koester, S. Koswatta
On the ITRS roadmap [1], the physical gate length, LG, has been rapidly scaling down, and will reach values below ∼ 10nm beyond 2020 (see Table I, shaded region). The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling [2–4]. Nevertheless, sub-10nm LG scaling will be a great challenge because of the significant mobility degradation [5] and channel thickness variations [2] in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-10nm LG scaling. It has been recently shown that the atomic-thin- body (ATB) geometry can meet the electrostatic requirements for LG ≤ 10nm [6]. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps [7] have been widely considered for high-performance digital electronics [8–10]. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently [6], including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. LG scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ∼ 1nm), and larger effective masses obtained from bandstructure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (ION ) [11]. The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap [1].
在ITRS路线图[1]中,物理栅极长度LG已经迅速缩小,并将在2020年之后达到低于~ 10nm的值(见表1,阴影区域)。单门(SG)极薄SOI (ETSOI) MOSFET,双门(DG) FinFET和栅极全能(GAA) Si纳米线(SiNW) MOSFET的几何形状可能有助于这种缩放[2-4]。然而,低于10nm的LG缩放将是一个巨大的挑战,因为上述几何形状中显著的迁移率下降[5]和通道厚度变化[2],由于静电短通道考虑所需的几纳米体厚度。因此,需要新的器件几何形状和技术,以同时保持10纳米以下LG缩放的静电完整性和优越的输运特性。最近有研究表明,原子薄体(ATB)几何结构可以满足LG≤10nm的静电要求[6]。在ATB极限下,基于具有可调谐带隙的石墨烯纳米带(gnr)的碳电子器件[7]已被广泛考虑用于高性能数字电子器件[8-10]。本文自一致地模拟了GNR肖特基势垒(SB)场效应管的弹道输运[6],包括热离子发射和隧穿。我们展示了与Si mosfet相比,gnr具有更好的栅极长度可扩展性,尽管必须克服重大的材料相关挑战。10nm以下的LG缩放主要受到直接源-漏极隧道效应和关闭状态下的双极性效应的限制,这可以通过更窄的能带宽度(约1nm)和更大的有效质量来抑制。如果可以实现负的金属-石墨烯SB-height,则GNR SB-FET可以在没有明显串联电阻效应的情况下工作,并提供高导通电流(ION)[11]。最终GNR sb - fet的性能可与ITRS路线图的MOSFET目标相媲美[1]。
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引用次数: 3
Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter 门控p-i-n硅纳米线中界面态密度随纳米线直径的函数测量
Pub Date : 2010-06-21 DOI: 10.1109/DRC.2010.5551960
G. Cohen, E. Cartier, S. Bangsaruntip, A. Majumdar, W. Haensch, L. Gignac, S. Mittal, J. Sleight
Gate-all-around p-i-n silicon nanowires (NW) diodes with effective nanowire diameter from 15 nm down to 4 nm (±1.3 nm) were fabricated to enable interface state density (Nit) measurements using the charge pumping (CP) method. The Nit of the NWs was also measured by the conductance method and was in good agreement with the CP method. The linear relation between the CP current and the pulse frequency was not maintained in the smallest diameter NWs. The dependency on the pulse rise and fall times was also investigated and is correlated to the lifetime of the traps. The impact of the cylindrical geometry on the measured CP current is discussed.
制备了有效纳米线直径从15 nm到4 nm(±1.3 nm)的栅极全能p-i-n硅纳米线(NW)二极管,利用电荷泵送(CP)方法测量界面态密度(Nit)。用电导法测量了NWs的Nit,结果与CP法吻合较好。在最小直径的NWs中,CP电流与脉冲频率之间不保持线性关系。对脉冲上升和下降时间的依赖关系也进行了研究,并与陷阱的寿命相关。讨论了圆柱几何形状对测量CP电流的影响。
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引用次数: 3
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68th Device Research Conference
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