Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551904
F. Medjdoub, D. Marcon, J. Das, J. Derluyn, K. Cheng, S. Degroote, M. Germain, S. Decoutere
In this paper, state-of-the-art 1 mm RF power GaN-on-Si HEMTs using thick in-situ grown SiN cap layer are presented. Output power density POUT exceeding 10 W/mm is reproducibly achieved above 50 V drain voltage while still limited by thermal issues. In order to assess the device stability, the GaN-on-Si HEMTs have been tested at high channel temperature (> 300°C) and under high electric field (VDS = 50 V). The results demonstrate for the first time the possibility to combine extremely high RF output power density at VDS = 50 V with high reliability using a cost-effective technology.
{"title":"Preliminary reliability at 50 V of state-of-the-art RF power GaN-on-Si HEMTs","authors":"F. Medjdoub, D. Marcon, J. Das, J. Derluyn, K. Cheng, S. Degroote, M. Germain, S. Decoutere","doi":"10.1109/DRC.2010.5551904","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551904","url":null,"abstract":"In this paper, state-of-the-art 1 mm RF power GaN-on-Si HEMTs using thick in-situ grown SiN cap layer are presented. Output power density POUT exceeding 10 W/mm is reproducibly achieved above 50 V drain voltage while still limited by thermal issues. In order to assess the device stability, the GaN-on-Si HEMTs have been tested at high channel temperature (> 300°C) and under high electric field (VDS = 50 V). The results demonstrate for the first time the possibility to combine extremely high RF output power density at VDS = 50 V with high reliability using a cost-effective technology.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129914412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551907
B. Lu, E. Piner, T. Palacios
AlGaN/GaN high electron mobility transistors (HEMTs) grown on Si substrates have attracted a great interest for power electronics applications. Despite the low cost of the Si substrate, the breakdown voltage (Vbk) of AlGaN/GaN HEMTs grown on Si (less than 600 V for 2 µm total nitride epilayer [1, 4]) is much lower than that grown on SiC (1.9 kV for 2 µm total epi-layer [2]). Although several approaches have been reported to improve Vbk [1, 3 and 4], the breakdown mechanism in these transistors is still not well understood. This paper studies for the first time the breakdown mechanism in AlGaN/GaN HEMTs on Si substrates. In addition, by transferring the AlGaN/GaN HEMTs grown on Si to a glass wafer, we have achieved devices with Vbk in excess of 1.45 kV and specific on-resistance of 5.3 mΩ.cm2.
{"title":"Breakdown mechanism in AlGaN/GaN HEMTs on Si substrate","authors":"B. Lu, E. Piner, T. Palacios","doi":"10.1109/DRC.2010.5551907","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551907","url":null,"abstract":"AlGaN/GaN high electron mobility transistors (HEMTs) grown on Si substrates have attracted a great interest for power electronics applications. Despite the low cost of the Si substrate, the breakdown voltage (Vbk) of AlGaN/GaN HEMTs grown on Si (less than 600 V for 2 µm total nitride epilayer [1, 4]) is much lower than that grown on SiC (1.9 kV for 2 µm total epi-layer [2]). Although several approaches have been reported to improve Vbk [1, 3 and 4], the breakdown mechanism in these transistors is still not well understood. This paper studies for the first time the breakdown mechanism in AlGaN/GaN HEMTs on Si substrates. In addition, by transferring the AlGaN/GaN HEMTs grown on Si to a glass wafer, we have achieved devices with Vbk in excess of 1.45 kV and specific on-resistance of 5.3 mΩ.cm2.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124513763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551910
J. Moon, D. Curtis, M. Hu, S. Bui, D. Wheeler, T. Marshall, H. Sharifi, D. Wong, D. Gaskill, P. Campbell, P. Asbeck, G. Jernigan, J. Tedesco, B. Vanmil, R. Myers-Ward, C. Eddy, X. Weng, J. Robinson, M. Fanton
Graphene has shown the highest carrier Hall mobility of >100,000 cm2/Vs with theoretical saturation velocity (Vsat) and source-injection velocity converging at ∼5E7 cm/sec [1] and ∼6E7 cm/sec, respectively. A potential combination of high current-carrying density, transconductance, and low access resistance could make graphene an attractive candidate for high-performance RF applications. So far, epitaxial graphene MOSFETs [2] in the early stages of development have revealed technical challenges: the current-voltage characteristics are quasi-linear with weak saturation behaviors and low transconductance per gate capacitance (<100 mS/mm). In addition, the Ion/Ioff ratio has been <10. While epitaxial graphene RF FETs with Fmax of 14 GHz per 2 µm gate length were demonstrated in a self-aligned top-gated layout with the highest ever on-state current density of 3 A/mm at Vds = 5 V, field-effect mobility was limited below 200 cm2/Vs. There are only a few reports of a graphene-on-Si platform with on-stage current <0.02 mA/mm. [3]
{"title":"Self-aligned graphene-on-SiC and graphene-on-Si MOSFETs on 75 mm wafers","authors":"J. Moon, D. Curtis, M. Hu, S. Bui, D. Wheeler, T. Marshall, H. Sharifi, D. Wong, D. Gaskill, P. Campbell, P. Asbeck, G. Jernigan, J. Tedesco, B. Vanmil, R. Myers-Ward, C. Eddy, X. Weng, J. Robinson, M. Fanton","doi":"10.1109/DRC.2010.5551910","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551910","url":null,"abstract":"Graphene has shown the highest carrier Hall mobility of >100,000 cm2/Vs with theoretical saturation velocity (Vsat) and source-injection velocity converging at ∼5E7 cm/sec [1] and ∼6E7 cm/sec, respectively. A potential combination of high current-carrying density, transconductance, and low access resistance could make graphene an attractive candidate for high-performance RF applications. So far, epitaxial graphene MOSFETs [2] in the early stages of development have revealed technical challenges: the current-voltage characteristics are quasi-linear with weak saturation behaviors and low transconductance per gate capacitance (<100 mS/mm). In addition, the Ion/Ioff ratio has been <10. While epitaxial graphene RF FETs with Fmax of 14 GHz per 2 µm gate length were demonstrated in a self-aligned top-gated layout with the highest ever on-state current density of 3 A/mm at Vds = 5 V, field-effect mobility was limited below 200 cm2/Vs. There are only a few reports of a graphene-on-Si platform with on-stage current <0.02 mA/mm. [3]","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551965
J. Sleight, S. Bangsaruntip, A. Majumdar, G. Cohen, Y. Zhang, S. Engelmann, N. Fuller, L. Gignac, S. Mittal, J. Newbury, M. Frank, J. Chang, M. Guillorn
We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.
{"title":"Gate-all-around silicon nanowire MOSFETs and circuits","authors":"J. Sleight, S. Bangsaruntip, A. Majumdar, G. Cohen, Y. Zhang, S. Engelmann, N. Fuller, L. Gignac, S. Mittal, J. Newbury, M. Frank, J. Chang, M. Guillorn","doi":"10.1109/DRC.2010.5551965","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551965","url":null,"abstract":"We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115521758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551970
G. Thareja, S. Chopra, B. Adams, N. Patil, Y. Ta, P. Porshnev, Y. Kim, S. Moffatt, D. Loftis, R. Brennan, G. Goodman, I. Abdelrehim, K. Saraswat, Y. Nishi
For the first time, ultra shallow junctions (xj < 10nm) are demonstrated using Plasma Immersion Ion Implantation for both n-type and p-type dopants in Ge. High electrical activation (>1×1020 cm−3) is achieved for all dopant atoms (P/As/Sb/B) using Laser Thermal Processing. We also show ultrathin (0.6nm), high quality GeO2 interfacial layer for gate dielectric, which provides substrate orientation independent Dit and mobility enhancement for Ge high-k N/P MOSFETs.
{"title":"Ultra shallow junctions with high dopant activation and GeO2 interfacial layer for gate dielectric in germanium MOSFETs","authors":"G. Thareja, S. Chopra, B. Adams, N. Patil, Y. Ta, P. Porshnev, Y. Kim, S. Moffatt, D. Loftis, R. Brennan, G. Goodman, I. Abdelrehim, K. Saraswat, Y. Nishi","doi":"10.1109/DRC.2010.5551970","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551970","url":null,"abstract":"For the first time, ultra shallow junctions (x<inf>j</inf> < 10nm) are demonstrated using Plasma Immersion Ion Implantation for both n-type and p-type dopants in Ge. High electrical activation (>1×10<sup>20</sup> cm<sup>−3</sup>) is achieved for all dopant atoms (P/As/Sb/B) using Laser Thermal Processing. We also show ultrathin (0.6nm), high quality GeO<inf>2</inf> interfacial layer for gate dielectric, which provides substrate orientation independent D<inf>it</inf> and mobility enhancement for Ge high-k N/P MOSFETs.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115680211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551954
A. Ali, H. Madan, A. Kirk, R. Wallace, D. Zhao, D. Mourey, M. Hudait, T. Jackson, B. R. Bennett, J. B. Boos, S. Datta
This paper discusses arsenic-antimonide based MOS-HEMTs which have great potential to enable complementary logic operation at low supply voltage. The effects of various surface passivation approaches on the capacitance-voltage characteristics (C-V) and the surface chemistry of n-type and p-type GaSb(100) MOS capacitors made with ALD and Plasma Enhanced ALD (PEALD) Al2O3 dielectrics studied in this paper. This paper also proposed for the first time unpinned Fermi level in GaSb MOS system with high-κ PEALD Al2O3 dielectric using admittance spectroscopy and XPS analysis.
{"title":"Fermi level unpinning of GaSb(100) using Plasma Enhanced ALD Al2O3 dielectric","authors":"A. Ali, H. Madan, A. Kirk, R. Wallace, D. Zhao, D. Mourey, M. Hudait, T. Jackson, B. R. Bennett, J. B. Boos, S. Datta","doi":"10.1109/DRC.2010.5551954","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551954","url":null,"abstract":"This paper discusses arsenic-antimonide based MOS-HEMTs which have great potential to enable complementary logic operation at low supply voltage. The effects of various surface passivation approaches on the capacitance-voltage characteristics (C-V) and the surface chemistry of n-type and p-type GaSb(100) MOS capacitors made with ALD and Plasma Enhanced ALD (PEALD) Al2O3 dielectrics studied in this paper. This paper also proposed for the first time unpinned Fermi level in GaSb MOS system with high-κ PEALD Al2O3 dielectric using admittance spectroscopy and XPS analysis.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132483270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551968
Jaegoo Lee, J. Cha, T. Naoi, D. Muller, R. V. van Dover, J. Shaw, E. Kan
As the scaling of conventional bulk Si flash memory cells approaches its fundamental limits, innovative 3D stacking and new materials must be considered. Ge is one of the promising candidates due to its attractive properties including higher mobility [1], smaller bandgap for supply voltage scaling, and lower processing temperature for compatibility with high-k dielectric [2] and 3D stack technology. Hence, a study the Ge UTB (ultra thin body) structure is pertinent for understanding its prospect as a viable solution [3]. Unlike silicon, however, the lack of a sufficiently stable native oxide hinders the passivation of Ge surfaces. The native germanium oxide is hygroscopic and water-soluble. Several gate dielectric materials with thick EOT on Ge have been reported [4] in early 1990s. Al2O3 has emerged as one of the most promising high-k gate dielectrics for Ge MOSFET and TFT [5] to cope with the issue of the native Ge oxide [6]. In this study, we demonstrate the material and electrical characteristics of stackable Ge TFT flash memory cell with Al2O3 high-k tunnel dielectric, metal NCs and (Ti,Dy)xOy control dielectric. Our proposed planar thin-film process is a simple batch process, and can therefore be used with relatively small cost increase.
{"title":"Ultra-thin-body PECVD Ge TFT low-voltage flash memory cell with high-k dielectrics for three-dimensional integration","authors":"Jaegoo Lee, J. Cha, T. Naoi, D. Muller, R. V. van Dover, J. Shaw, E. Kan","doi":"10.1109/DRC.2010.5551968","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551968","url":null,"abstract":"As the scaling of conventional bulk Si flash memory cells approaches its fundamental limits, innovative 3D stacking and new materials must be considered. Ge is one of the promising candidates due to its attractive properties including higher mobility [1], smaller bandgap for supply voltage scaling, and lower processing temperature for compatibility with high-k dielectric [2] and 3D stack technology. Hence, a study the Ge UTB (ultra thin body) structure is pertinent for understanding its prospect as a viable solution [3]. Unlike silicon, however, the lack of a sufficiently stable native oxide hinders the passivation of Ge surfaces. The native germanium oxide is hygroscopic and water-soluble. Several gate dielectric materials with thick EOT on Ge have been reported [4] in early 1990s. Al2O3 has emerged as one of the most promising high-k gate dielectrics for Ge MOSFET and TFT [5] to cope with the issue of the native Ge oxide [6]. In this study, we demonstrate the material and electrical characteristics of stackable Ge TFT flash memory cell with Al2O3 high-k tunnel dielectric, metal NCs and (Ti,Dy)xOy control dielectric. Our proposed planar thin-film process is a simple batch process, and can therefore be used with relatively small cost increase.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132070940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551856
D. Mohata, D. Pawlik, L. Liu, S. Mookerjea, V. Saripalli, S. Rommel, S. Datta
Inter-band tunnel field effect transistors (TFETs) have recently gained a lot of interest because of their ability to eliminate the 60mV/dec sub-threshold slope (STS) limitation in MOSFET. This can result in higher ION-IOFF ratio over a reduced gate voltage range, thus predicting TFETs superior for low supply voltage (VDD ≤ 0.5V) operation. Unlike Si and Ge, III-V semiconductors like In0.53Ga0.47As have smaller tunneling barrier and tunnelling mass, thus making them a design choice to eliminate drive current (ION) limitations in TFETs [1–2]. In this work, (i) we present the experimental demonstration of record peak current density (JPEAK) In0.53Ga0.47As Esaki tunnel diode, formed using MBE grown in-situ doped epitaxial layers [4]. (ii) Using a non-local tunneling model in Sentaurus device simulator [3], the measured current-voltage characteristics (J-V) is modeled and the model parameters are calibrated. (iii) Novel In0.53Ga0.47As ultra thin body (7nm)-double gate-TFET (UTB-DG-TFET) design to boost I{ON} is discussed using the calibrated non-local tunneling model. (iv) Pulse transient response of the novel In0.53Ga0.47As TFET inverter is presented and compared with Si based MOSFET inverters at a supply voltage of 0.5V.
带间隧道场效应晶体管(tfet)由于能够消除MOSFET中60mV/dec的亚阈值斜率(STS)限制，最近获得了很多兴趣。这可以在降低的栅极电压范围内产生更高的离子- ioff比，从而预测tfet更适合低电源电压(VDD≤0.5V)工作。与Si和Ge不同，In0.53Ga0.47As等III-V半导体具有更小的隧穿势垒和隧穿质量，因此使其成为消除tfet中驱动电流(ION)限制的设计选择[1-2]。在这项工作中，(i)我们展示了使用MBE生长原位掺杂外延层形成的0.53 ga0.47 as Esaki隧道二极管的创纪录峰值电流密度(JPEAK)的实验演示[4]。(ii)使用Sentaurus器件模拟器[3]中的非局部隧道模型，对测量的电流-电压特性(J-V)进行建模，并对模型参数进行校准。(iii)采用校准的非局部隧道模型，讨论了新型的In0.53Ga0.47As超薄体(7nm)-双栅极tfet (UTB-DG-TFET)设计，以增强I{ON}。(iv)给出了新型In0.53Ga0.47As TFET逆变器在0.5V电源电压下的脉冲瞬态响应，并与Si基MOSFET逆变器进行了比较。
{"title":"Implications of record peak current density In0.53Ga0.47As Esaki tunnel diode on Tunnel FET logic applications","authors":"D. Mohata, D. Pawlik, L. Liu, S. Mookerjea, V. Saripalli, S. Rommel, S. Datta","doi":"10.1109/DRC.2010.5551856","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551856","url":null,"abstract":"Inter-band tunnel field effect transistors (TFETs) have recently gained a lot of interest because of their ability to eliminate the 60mV/dec sub-threshold slope (STS) limitation in MOSFET. This can result in higher I<inf>ON</inf>-I<inf>OFF</inf> ratio over a reduced gate voltage range, thus predicting TFETs superior for low supply voltage (V<inf>DD</inf> ≤ 0.5V) operation. Unlike Si and Ge, III-V semiconductors like In<inf>0.53</inf>Ga<inf>0.47</inf>As have smaller tunneling barrier and tunnelling mass, thus making them a design choice to eliminate drive current (I<inf>ON</inf>) limitations in TFETs [1–2]. In this work, (i) we present the experimental demonstration of record peak current density (J<inf>PEAK</inf>) In<inf>0.53</inf>Ga<inf>0.47</inf>As Esaki tunnel diode, formed using MBE grown in-situ doped epitaxial layers [4]. (ii) Using a non-local tunneling model in Sentaurus device simulator [3], the measured current-voltage characteristics (J-V) is modeled and the model parameters are calibrated. (iii) Novel In<inf>0.53</inf>Ga<inf>0.47</inf>As ultra thin body (7nm)-double gate-TFET (UTB-DG-TFET) design to boost I{ON} is discussed using the calibrated non-local tunneling model. (iv) Pulse transient response of the novel In<inf>0.53</inf>Ga<inf>0.47</inf>As TFET inverter is presented and compared with Si based MOSFET inverters at a supply voltage of 0.5V.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126882080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551932
V. Dorgan, M. Bae, E. Pop
Graphene holds great promise for applications in future integrated-circuit technology. Despite studies at low fields and low temperatures, surprisingly little data exists on the properties of graphene at practical temperatures and high electric fields required by modern transistors. In this study, we characterized graphene mobility as a function of carrier density at temperatures from 300–500 K. In addition, we obtained electron drift velocity at high-fields up to 2 V/µm, at both 300 K and 80 K.
{"title":"Mobility and velocity-field relationship in graphene","authors":"V. Dorgan, M. Bae, E. Pop","doi":"10.1109/DRC.2010.5551932","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551932","url":null,"abstract":"Graphene holds great promise for applications in future integrated-circuit technology. Despite studies at low fields and low temperatures, surprisingly little data exists on the properties of graphene at practical temperatures and high electric fields required by modern transistors. In this study, we characterized graphene mobility as a function of carrier density at temperatures from 300–500 K. In addition, we obtained electron drift velocity at high-fields up to 2 V/µm, at both 300 K and 80 K.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126761087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/DRC.2010.5551902
U. Singisetti, M. Wong, S. Dasgupta, Nidhi, B. Swenson, B. Thibeault, J. Speck, U. Mishra
E-mode GaN FETs fabricated on N-polar GaN have several unique scaling advantages such as vertical scaling of channel with back barrier for better electron confinement and regrowth of the n+ source/drain regions for reduced access resistance. They can also be integrated with recently demonstrated high performance N-polar D-mode [1] devices enabling novel circuit functionalities. Ga-polar E-mode devices with good performance have been demonstrated [2]; however in these devices source/drain contacts are invariably made to wideband gap AlxGa1−xN barriers leading to higher contact resistances which considerably limit the aggressive scaling of the device. Here we report E-mode N-polar GaN FETs fabricated with a scalable gate first process with self-aligned regrown source/drain regions and non-alloyed ohmic contacts for low access resistances. These devices show a peak drive current (Id) of 0.74 A/mm and peak transconductance (gm) of 250 mS/mm at Lg = 0.55 µm with a threshold voltage (Vth) of 0.8 V.
在n极氮化镓上制备的e型氮化镓场效应管具有几个独特的缩放优势，例如具有后势垒的沟道垂直缩放以获得更好的电子约束和n+源/漏区再生以降低通路电阻。它们还可以与最近展示的高性能n极d模式[1]器件集成，从而实现新颖的电路功能。已证明具有良好性能的ga极e模器件[2];然而，在这些器件中，源极/漏极触点总是被制作成宽带间隙AlxGa1−xN障碍，导致更高的接触电阻，这大大限制了器件的积极缩放。在这里，我们报告了用可扩展的栅极优先工艺制造的e型n极氮化镓场效应管，具有自对准再生源/漏极区域和非合金欧姆触点，具有低接入电阻。这些器件在Lg = 0.55µm时的峰值驱动电流(Id)为0.74 a /mm，峰值跨导(gm)为250 mS/mm，阈值电压(Vth)为0.8 V。
{"title":"Scalable E-mode N-polar GaN MISFET devices and process with self-aligned source/drain regrowth","authors":"U. Singisetti, M. Wong, S. Dasgupta, Nidhi, B. Swenson, B. Thibeault, J. Speck, U. Mishra","doi":"10.1109/DRC.2010.5551902","DOIUrl":"https://doi.org/10.1109/DRC.2010.5551902","url":null,"abstract":"E-mode GaN FETs fabricated on N-polar GaN have several unique scaling advantages such as vertical scaling of channel with back barrier for better electron confinement and regrowth of the n+ source/drain regions for reduced access resistance. They can also be integrated with recently demonstrated high performance N-polar D-mode [1] devices enabling novel circuit functionalities. Ga-polar E-mode devices with good performance have been demonstrated [2]; however in these devices source/drain contacts are invariably made to wideband gap AlxGa1−xN barriers leading to higher contact resistances which considerably limit the aggressive scaling of the device. Here we report E-mode N-polar GaN FETs fabricated with a scalable gate first process with self-aligned regrown source/drain regions and non-alloyed ohmic contacts for low access resistances. These devices show a peak drive current (Id) of 0.74 A/mm and peak transconductance (gm) of 250 mS/mm at Lg = 0.55 µm with a threshold voltage (Vth) of 0.8 V.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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