Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584564
Kuo-Hsing Cheng, Y. Liow
This work describes a CMOS 8*8-bit parallel multiplier for 1.2 V supply voltage. The low-power current-sensing complementary pass-transistor logic (LCSCPTL) is applied to the design of the parallel multiplier. The LCSCPTL have certain advantages in both speed and power dissipation over the CPL circuit. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V low-voltage 8*8-bit parallel multiplier can be designed and fabricated without changing the conventional 5 V 0.8 m CMOS process. Based upon the HSPICE simulation results, the operation speed of the parallel multiplier is 54 ns for 1.2 V supply voltage.
本文描述了一种用于1.2 V电源电压的CMOS 8*8位并行乘法器。将低功耗电流传感互补通管逻辑(LCSCPTL)应用于并联乘法器的设计。与CPL电路相比，LCSCPTL在速度和功耗方面都具有一定的优势。本设计采用4-2压缩机和条件进位选择方案，实现布局规整，提高运行速度。此外，在不改变传统的5 V 0.8 m CMOS工艺的情况下，可以设计和制造1.2 V低压8*8位并行倍增器。基于HSPICE仿真结果，在1.2 V电源电压下，并联倍增器的工作速度为54 ns。
{"title":"A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic","authors":"Kuo-Hsing Cheng, Y. Liow","doi":"10.1109/ICECS.1996.584564","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584564","url":null,"abstract":"This work describes a CMOS 8*8-bit parallel multiplier for 1.2 V supply voltage. The low-power current-sensing complementary pass-transistor logic (LCSCPTL) is applied to the design of the parallel multiplier. The LCSCPTL have certain advantages in both speed and power dissipation over the CPL circuit. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V low-voltage 8*8-bit parallel multiplier can be designed and fabricated without changing the conventional 5 V 0.8 m CMOS process. Based upon the HSPICE simulation results, the operation speed of the parallel multiplier is 54 ns for 1.2 V supply voltage.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134259418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584485
T. Maayah, M. Khasawneh, L. Khadra
A statistical approach for chaos identification in a time series is described and applied to numerical data generated from Chua's circuit. This method compares the short-term predictability for a given time series to an ensemble of random data which has the same Fourier spectrum as the original time series. The forecasting error is computed as a statistic for performing statistical hypothesis testing. The forcasting technique is modified by introducing a moving predictor. The results show that this will give more accurate predictions, hence, better capability of distinguishing chaos from random noise in time series.
{"title":"A novel statistical approach for chaos detection in Chua's circuit","authors":"T. Maayah, M. Khasawneh, L. Khadra","doi":"10.1109/ICECS.1996.584485","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584485","url":null,"abstract":"A statistical approach for chaos identification in a time series is described and applied to numerical data generated from Chua's circuit. This method compares the short-term predictability for a given time series to an ensemble of random data which has the same Fourier spectrum as the original time series. The forecasting error is computed as a statistic for performing statistical hypothesis testing. The forcasting technique is modified by introducing a moving predictor. The results show that this will give more accurate predictions, hence, better capability of distinguishing chaos from random noise in time series.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131614807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582909
I. Demongodin, N. Koussoulas
A new extension of Petri nets, called differential Petri nets, that allows the representation of mixed continuous and discrete-event (so-called hybrid) systems, is presented. Applications range from supervisory control of industrial processes to high-level coordination of hybrid systems.
{"title":"Modeling of mixed continuous/discrete-event systems via differential Petri nets","authors":"I. Demongodin, N. Koussoulas","doi":"10.1109/ICECS.1996.582909","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582909","url":null,"abstract":"A new extension of Petri nets, called differential Petri nets, that allows the representation of mixed continuous and discrete-event (so-called hybrid) systems, is presented. Applications range from supervisory control of industrial processes to high-level coordination of hybrid systems.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127568920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584626
K. Herrmann, K. Gaedke, J. Hilgenstock, P. Pirsch
A development system for investigations on video signal processing in multimedia applications has been developed. This system is based on the single chip multiprocessor array MAXPE9 which integrates 9 programmable video signal processing elements AxPe on a silicon area of 16 cm/sup 2/. Each AxPe has a peak arithmetic performance of 1 GOPS. In order to demonstrate the computational power of the MAXPE9 for video coding schemes in multimedia applications, an universal hardware platform based on a personal computer and software tools have been developed. It allows an efficient programming of the MAXPE9 including an immediate verification on hardware. Examples of video coding schemes to be investigated are hybrid coding according to ITU-T H.261, H.263 or ISO MPEG 1/2.
{"title":"Design of a development system for multimedia applications based on a single chip multiprocessor array","authors":"K. Herrmann, K. Gaedke, J. Hilgenstock, P. Pirsch","doi":"10.1109/ICECS.1996.584626","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584626","url":null,"abstract":"A development system for investigations on video signal processing in multimedia applications has been developed. This system is based on the single chip multiprocessor array MAXPE9 which integrates 9 programmable video signal processing elements AxPe on a silicon area of 16 cm/sup 2/. Each AxPe has a peak arithmetic performance of 1 GOPS. In order to demonstrate the computational power of the MAXPE9 for video coding schemes in multimedia applications, an universal hardware platform based on a personal computer and software tools have been developed. It allows an efficient programming of the MAXPE9 including an immediate verification on hardware. Examples of video coding schemes to be investigated are hybrid coding according to ITU-T H.261, H.263 or ISO MPEG 1/2.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130706309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584543
B. Oelmann, H. Tenhunen
In this paper we present how an asynchronous system, using micropipelines, can be modelled in a system level performance model. We have introduced structures for pipeline stages and feedback structures. The model has been used in order to find out at what complexity a micropipeline implementation can out-perform a synchronous one. We have also used it for examining if micropipelines can be used as an alternative to clock-gating as a method for saving power. Results from these simulations are presented and compared to measurements on a complex asynchronous circuit.
{"title":"A system level performance model for asynchronous micropipeline circuits","authors":"B. Oelmann, H. Tenhunen","doi":"10.1109/ICECS.1996.584543","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584543","url":null,"abstract":"In this paper we present how an asynchronous system, using micropipelines, can be modelled in a system level performance model. We have introduced structures for pipeline stages and feedback structures. The model has been used in order to find out at what complexity a micropipeline implementation can out-perform a synchronous one. We have also used it for examining if micropipelines can be used as an alternative to clock-gating as a method for saving power. Results from these simulations are presented and compared to measurements on a complex asynchronous circuit.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117325227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582779
J. Ngarmnil, A. Thanachayanont, C. Toumazou, S. Pookaiyaudom
A novel current-mode micropower active resonator and oscillator employing MOSFETs operating in weak inversion are proposed. The approach is an extension of the recently proposed current-mode bipolar log domain synthesis methodology. Simulation results using HSPICE demonstrate that a very high-Q active resonator tunable over several kHz and a very low distortion oscillator can be synthesised using simple processing building blocks, with net power consumption of less than a microwatt.
{"title":"On the design of micropower active resonators and oscillators using log-domain processing","authors":"J. Ngarmnil, A. Thanachayanont, C. Toumazou, S. Pookaiyaudom","doi":"10.1109/ICECS.1996.582779","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582779","url":null,"abstract":"A novel current-mode micropower active resonator and oscillator employing MOSFETs operating in weak inversion are proposed. The approach is an extension of the recently proposed current-mode bipolar log domain synthesis methodology. Simulation results using HSPICE demonstrate that a very high-Q active resonator tunable over several kHz and a very low distortion oscillator can be synthesised using simple processing building blocks, with net power consumption of less than a microwatt.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131077317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582842
Takayuki Watanabe, H. Asai
This paper describes a waveform relaxation-based coupled lossy transmission line circuit simulator DESIRE3T+. First, the generalized method of characteristics (GMC) is reviewed, which replaces a lossy transmission line with an equivalent disjoint network. Next, the generalized line delay window (GLDW) partitioning technique is proposed, which accelerates the transient analysis of the circuits including transmission lines replaced by GMC model. Finally, GMC model and GLDW technique are implemented in the relaxation-based circuit simulator DESIRE3T+ which can analyze bipolar transistor circuits by using the dynamic decomposition technique, and the performance is estimated.
{"title":"DESIRE3T+: waveform relaxation-based simulator for coupled lossy transmission lines circuits","authors":"Takayuki Watanabe, H. Asai","doi":"10.1109/ICECS.1996.582842","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582842","url":null,"abstract":"This paper describes a waveform relaxation-based coupled lossy transmission line circuit simulator DESIRE3T+. First, the generalized method of characteristics (GMC) is reviewed, which replaces a lossy transmission line with an equivalent disjoint network. Next, the generalized line delay window (GLDW) partitioning technique is proposed, which accelerates the transient analysis of the circuits including transmission lines replaced by GMC model. Finally, GMC model and GLDW technique are implemented in the relaxation-based circuit simulator DESIRE3T+ which can analyze bipolar transistor circuits by using the dynamic decomposition technique, and the performance is estimated.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584657
K. Hadidi, A. Khoei
Traditionally CMOS technology lacks a simple open-loop buffer like emitter-follower of bipolar technology. The simple source-follower buffer suffers from channel-length modulation of the driver device as the main source of harmonic distortion. In this article we present a novel source-follower buffer that its driver device is cascoded. Thus, the circuit can improve harmonic distortion up to 20 dB relative to conventional one.
{"title":"A highly linear cascode-driver CMOS source-follower buffer","authors":"K. Hadidi, A. Khoei","doi":"10.1109/ICECS.1996.584657","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584657","url":null,"abstract":"Traditionally CMOS technology lacks a simple open-loop buffer like emitter-follower of bipolar technology. The simple source-follower buffer suffers from channel-length modulation of the driver device as the main source of harmonic distortion. In this article we present a novel source-follower buffer that its driver device is cascoded. Thus, the circuit can improve harmonic distortion up to 20 dB relative to conventional one.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132574713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584656
K. Ralev, P. Bauer
This paper establishes register length requirements for floating point state space digital filters so that the zero-input response of the filter converges to underflow. Considered are different quantization formats and order of operation. Examples which illustrate the conservatism of the results are also provided.
{"title":"Asymptotic errors of floating point digital filters","authors":"K. Ralev, P. Bauer","doi":"10.1109/ICECS.1996.584656","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584656","url":null,"abstract":"This paper establishes register length requirements for floating point state space digital filters so that the zero-input response of the filter converges to underflow. Considered are different quantization formats and order of operation. Examples which illustrate the conservatism of the results are also provided.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132589246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584632
Chung-Yu Wu, Yuh-Kuang Tseng
A new full-swing BiCMOS logic circuits called the bootstrapped multi-emitter BiCMOS (B/sup 2/M-BiCMOS) logic is proposed and analyzed. HSPICE simulations have been performed to compare speed performance of the new BiCMOS logic circuit with those of CMOS, conventional BiCMOS, and Bootstrapped BiCMOS (BS-BiCMOS) logic circuits, in 1 /spl mu/m technology. It has been shown that as compared to BS-BiCMOS (CMOS) logic gate, the new B/sup 2/M-BiCMOS 3-input NAND gate with 2 V supply voltage and 0.5 pF output loading has about 36% (72%) improvement in the propagation delay time whereas the B/sup 2/M-BiCMOS 5- and 7-input NAND gates have 1.84 (2.4) and 2.16 (3.1) times of improvement, respectively. This advantageous performance makes the B/sup 2/M-BiCMOS feasible in many low-voltage BiCMOS applications.
{"title":"Bipolar bootstrapped multi-emitter BiCMOS (B/sup 2/M-BiCMOS) logic for low-voltage applications","authors":"Chung-Yu Wu, Yuh-Kuang Tseng","doi":"10.1109/ICECS.1996.584632","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584632","url":null,"abstract":"A new full-swing BiCMOS logic circuits called the bootstrapped multi-emitter BiCMOS (B/sup 2/M-BiCMOS) logic is proposed and analyzed. HSPICE simulations have been performed to compare speed performance of the new BiCMOS logic circuit with those of CMOS, conventional BiCMOS, and Bootstrapped BiCMOS (BS-BiCMOS) logic circuits, in 1 /spl mu/m technology. It has been shown that as compared to BS-BiCMOS (CMOS) logic gate, the new B/sup 2/M-BiCMOS 3-input NAND gate with 2 V supply voltage and 0.5 pF output loading has about 36% (72%) improvement in the propagation delay time whereas the B/sup 2/M-BiCMOS 5- and 7-input NAND gates have 1.84 (2.4) and 2.16 (3.1) times of improvement, respectively. This advantageous performance makes the B/sup 2/M-BiCMOS feasible in many low-voltage BiCMOS applications.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133194575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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