Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582812
Konstantínos D. Katsibas, C. Balanis, Panayiotis A. Tirkas, C. Birtcher
The printed folded loop antenna and the rectangular loop antenna are analyzed as possible candidate antennas for existing and future mobile systems, respectively. FDTD is used to calculate radiation patterns and input impedance. The calculated results are in good agreement with measurements. The proposed antennas meet the design requirements for mobile networks.
{"title":"Print loop antennas for mobile communications","authors":"Konstantínos D. Katsibas, C. Balanis, Panayiotis A. Tirkas, C. Birtcher","doi":"10.1109/ICECS.1996.582812","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582812","url":null,"abstract":"The printed folded loop antenna and the rectangular loop antenna are analyzed as possible candidate antennas for existing and future mobile systems, respectively. FDTD is used to calculate radiation patterns and input impedance. The calculated results are in good agreement with measurements. The proposed antennas meet the design requirements for mobile networks.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128846624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582782
Chung-Yu Wu, Heng-Shou Hsu
In this paper, a new design technique to implement VHF current-mode bandpass ladder filters directly by using the VHF current-mode bandpass biquads is proposed and analyzed. The VHF current-mode bandpass biquads are implemented by the transresistance (Rm) amplifier-capacitor structure. Moreover, the special Q-enhancement technique is applied to the biquad to obtain the tunable and high-quality factor Q. Starting from the prototype of LC ladder bandpass filter and assigning the proper state variables, the state equations of the LC ladder bandpass filter are rewritten in terms of the current-mode state variables and current-mode high-Q bandpass biquadratic functions. Thus, the current-mode ladder filter can be constructed by directly using the current-mode high-Q bandpass biquads as basic cells. A 6th order current-mode bandpass ladder filter with the center frequency up to 50 MHz has been successfully designed by using the current-mode high-Q biquadratic bandpass filters. It has the advantageous features of low component sensitivity and simple structure. It is also free from DC instability problems.
{"title":"A new design technique of CMOS continuous-time VHF current-mode bandpass ladder filters using VHF bandpass biquads","authors":"Chung-Yu Wu, Heng-Shou Hsu","doi":"10.1109/ICECS.1996.582782","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582782","url":null,"abstract":"In this paper, a new design technique to implement VHF current-mode bandpass ladder filters directly by using the VHF current-mode bandpass biquads is proposed and analyzed. The VHF current-mode bandpass biquads are implemented by the transresistance (Rm) amplifier-capacitor structure. Moreover, the special Q-enhancement technique is applied to the biquad to obtain the tunable and high-quality factor Q. Starting from the prototype of LC ladder bandpass filter and assigning the proper state variables, the state equations of the LC ladder bandpass filter are rewritten in terms of the current-mode state variables and current-mode high-Q bandpass biquadratic functions. Thus, the current-mode ladder filter can be constructed by directly using the current-mode high-Q bandpass biquads as basic cells. A 6th order current-mode bandpass ladder filter with the center frequency up to 50 MHz has been successfully designed by using the current-mode high-Q biquadratic bandpass filters. It has the advantageous features of low component sensitivity and simple structure. It is also free from DC instability problems.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"403 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126680021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584522
J. Song, J. Yuan, F. Schwierz, D. Schipanski
Effects of the shape of Ge profiles in the base of the SiGe bipolar transistor have been evaluated. Analytical equations of base transit time and base resistance taking into account built-in field from nonuniform base doping and Ge bandgap grading are derived. Comparisons of base transit time and base sheet resistance for different Ge profiles are presented.
{"title":"Effects of Ge profiles on base transit time and base resistance of SiGe HBT's","authors":"J. Song, J. Yuan, F. Schwierz, D. Schipanski","doi":"10.1109/ICECS.1996.584522","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584522","url":null,"abstract":"Effects of the shape of Ge profiles in the base of the SiGe bipolar transistor have been evaluated. Analytical equations of base transit time and base resistance taking into account built-in field from nonuniform base doping and Ge bandgap grading are derived. Comparisons of base transit time and base sheet resistance for different Ge profiles are presented.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123236832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584520
Y. Dai, J. Yuan, A. Phanse, C. Yeh, K. Kwang
A Gummel-Poon like bipolar transistor model including effects of quasi-saturation is derived. The model includes multi-dimensional effects such as sidewall injection, emitter current crowding, and collector current spreading. A current-dependent epilayer collector resistance is proposed to model collector conductivity modulation in quasi-saturation. The model has been compared with measurement and implemented in bipolar and BiCMOS circuits.
{"title":"Scalable bipolar model for BiCMOS and bipolar circuits","authors":"Y. Dai, J. Yuan, A. Phanse, C. Yeh, K. Kwang","doi":"10.1109/ICECS.1996.584520","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584520","url":null,"abstract":"A Gummel-Poon like bipolar transistor model including effects of quasi-saturation is derived. The model includes multi-dimensional effects such as sidewall injection, emitter current crowding, and collector current spreading. A current-dependent epilayer collector resistance is proposed to model collector conductivity modulation in quasi-saturation. The model has been compared with measurement and implemented in bipolar and BiCMOS circuits.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123287289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582845
L. T. Walczowski, W. Waller, D. Nalbantis, K. Shi
A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, a design rule correct layout is generated. The complete system has been tested by synthesizing op amps in the CMOS and bipolar domains. Comparison of the specification with results of simulating the circuit extracted from the synthesized layout, show that the system is accurate to within a few per cent for most parameters.
{"title":"Rapid layout synthesis for analog VLSI","authors":"L. T. Walczowski, W. Waller, D. Nalbantis, K. Shi","doi":"10.1109/ICECS.1996.582845","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582845","url":null,"abstract":"A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, a design rule correct layout is generated. The complete system has been tested by synthesizing op amps in the CMOS and bipolar domains. Comparison of the specification with results of simulating the circuit extracted from the synthesized layout, show that the system is accurate to within a few per cent for most parameters.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126245483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584646
S. Siskos, T. Laopoulos, A. Hatzopoulos, M. Bafleur
Quiescent current monitoring is considered as an interesting and efficient technique for mixed-signal testing, where fault detection of analog parts requires the precise measure of the I/sub ddq/. This paper presents a very simple current sensor for on-chip current monitoring giving an accurate analog output proportional to the quiescent current. The proposed circuit is based on a second generation current conveyor. Experimental results show the functionality of the proposed configuration and its linear output characteristic.
{"title":"A current conveyor based BIC sensor for current monitoring in mixed-signal circuits","authors":"S. Siskos, T. Laopoulos, A. Hatzopoulos, M. Bafleur","doi":"10.1109/ICECS.1996.584646","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584646","url":null,"abstract":"Quiescent current monitoring is considered as an interesting and efficient technique for mixed-signal testing, where fault detection of analog parts requires the precise measure of the I/sub ddq/. This paper presents a very simple current sensor for on-chip current monitoring giving an accurate analog output proportional to the quiescent current. The proposed circuit is based on a second generation current conveyor. Experimental results show the functionality of the proposed configuration and its linear output characteristic.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122951616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582705
M. Topa, E. Simion
Symbolic network analysis is a formal technique, complementary to numerical analysis, to calculate the behaviour or a characteristic of a circuit with independent variable frequency, dependent variables voltages and currents and some or all of the circuit elements represented by symbols. The evaluation of the symbolic functions is much easier and faster than working repeatedly with a numerical simulator. A program for symbolic network analysis, of lumped linear or linearised time invariant circuits is presented. The network functions and their sensitivities with respect to the element values are computed with a matrix-based method, using symbolic manipulation of algebraic expressions. An interesting application of the symbolic network analysis is noise computation, one of the most difficult tasks that an analog engineer must perform. Symbolic expressions for the system noise measures are obtained.
{"title":"Applications of symbolic network analysis","authors":"M. Topa, E. Simion","doi":"10.1109/ICECS.1996.582705","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582705","url":null,"abstract":"Symbolic network analysis is a formal technique, complementary to numerical analysis, to calculate the behaviour or a characteristic of a circuit with independent variable frequency, dependent variables voltages and currents and some or all of the circuit elements represented by symbols. The evaluation of the symbolic functions is much easier and faster than working repeatedly with a numerical simulator. A program for symbolic network analysis, of lumped linear or linearised time invariant circuits is presented. The network functions and their sensitivities with respect to the element values are computed with a matrix-based method, using symbolic manipulation of algebraic expressions. An interesting application of the symbolic network analysis is noise computation, one of the most difficult tasks that an analog engineer must perform. Symbolic expressions for the system noise measures are obtained.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122289222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584475
Marcel J. M. Pelgrom, M. Vertregt
Economic and technical constraints force digital CMOS technology in a direction which is not always beneficial for analog design. The development of some analog parameters as a function of CMOS process generation is analysed. The role for BiCMOS in future generations mixed-signal ICs is likely to grow.
{"title":"BiCMOS and CMOS: a long term relation","authors":"Marcel J. M. Pelgrom, M. Vertregt","doi":"10.1109/ICECS.1996.584475","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584475","url":null,"abstract":"Economic and technical constraints force digital CMOS technology in a direction which is not always beneficial for analog design. The development of some analog parameters as a function of CMOS process generation is analysed. The role for BiCMOS in future generations mixed-signal ICs is likely to grow.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121177984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584516
Y. Yang, N. Cho, Sang Uk Lee
In this paper, a novel adaptive IIR filter employing subband decomposition is presented, To derive the subband IIR adaptive filter, the subband ARMA model is introduced. Then the subband IIR adaptive filter is proposed. The proposed subband IIR filter employs reduced order adaptive IIR filter in each subband, which can approximate high order adaptive ARMA system. The computer simulations reveal that the convergence performance of the proposed subband IIR filter outperforms the conventional parallel form adaptive IIR filter.
{"title":"Adaptive IIR filtering employing subband decomposition","authors":"Y. Yang, N. Cho, Sang Uk Lee","doi":"10.1109/ICECS.1996.584516","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584516","url":null,"abstract":"In this paper, a novel adaptive IIR filter employing subband decomposition is presented, To derive the subband IIR adaptive filter, the subband ARMA model is introduced. Then the subband IIR adaptive filter is proposed. The proposed subband IIR filter employs reduced order adaptive IIR filter in each subband, which can approximate high order adaptive ARMA system. The computer simulations reveal that the convergence performance of the proposed subband IIR filter outperforms the conventional parallel form adaptive IIR filter.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116537755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584608
M. Burke, A. Boilson
A circuit has been designed which measures the beat-to-beat heart-rate in humans, accepting as input a digital signal representing the subject's pulse. The range of heart-rate covered is 30-255 beats/min. The design is based on an inverse-time counter implemented using a pair of 8-bit down-counters and the associated state determining combinational logic. It also incorporates the logic for a latched 3-digit LCD decoder/driver interface in addition to an 8-bit binary output. The IC has been designed for full testability with bidirectional access to key timing and control points being provided and a scan path strategy applied to the main blocks of the chip. Various test and access modes are controlled using a decoding/multiplexing principle. The IC was designed using the 2.4 /spl mu/m CMOS Mietec cell library and Cadence EDGE software. It contains 13,000 transistors and occupies a silicon area of 25 mm/sup 2/.
{"title":"A digital cardiotachometer ASIC","authors":"M. Burke, A. Boilson","doi":"10.1109/ICECS.1996.584608","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584608","url":null,"abstract":"A circuit has been designed which measures the beat-to-beat heart-rate in humans, accepting as input a digital signal representing the subject's pulse. The range of heart-rate covered is 30-255 beats/min. The design is based on an inverse-time counter implemented using a pair of 8-bit down-counters and the associated state determining combinational logic. It also incorporates the logic for a latched 3-digit LCD decoder/driver interface in addition to an 8-bit binary output. The IC has been designed for full testability with bidirectional access to key timing and control points being provided and a scan path strategy applied to the main blocks of the chip. Various test and access modes are controlled using a decoding/multiplexing principle. The IC was designed using the 2.4 /spl mu/m CMOS Mietec cell library and Cadence EDGE software. It contains 13,000 transistors and occupies a silicon area of 25 mm/sup 2/.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116541940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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