RRAM-based memory is a promising emerging technology for both on-chip and stand-alone non-volatile data storage in advanced technologies. In addition to its small dimensions, the RRAM device has many technological advantages including its low-programming voltages, high speed, low power, CMOS-compatible fabrication process, and potentially monolithic 3D integration. However, one of the critical challenges for RRAM technology is the reliability concerns due to retention and endurance failures. In this paper, we propose a novel Refresh circuit for 1T1R RRAM array which detects and distinguishes soft and hard errors from retention and endurance failures, as well as corrects the soft errors through refreshing. Using the HfO2/ Hf RRAM array, our simulation results show that the proposed solution increases the resilience to soft-error of an 8Gb RRAM-based memory by 80% with a small penalty on the energy and delay of the Read operations (6% and 0.4% respectively). The proposed methodology can be used for other RRAM arrays with minor modifications to the design parameters depending on the characteristics of RRAM cell.
{"title":"RRAM refresh circuit: A proposed solution to resolve the soft-error failures for HfO2/Hf 1T1R RRAM memory cell","authors":"Amr M. S. Tosson, M. Anis, Lan Wei","doi":"10.1145/2902961.2903017","DOIUrl":"https://doi.org/10.1145/2902961.2903017","url":null,"abstract":"RRAM-based memory is a promising emerging technology for both on-chip and stand-alone non-volatile data storage in advanced technologies. In addition to its small dimensions, the RRAM device has many technological advantages including its low-programming voltages, high speed, low power, CMOS-compatible fabrication process, and potentially monolithic 3D integration. However, one of the critical challenges for RRAM technology is the reliability concerns due to retention and endurance failures. In this paper, we propose a novel Refresh circuit for 1T1R RRAM array which detects and distinguishes soft and hard errors from retention and endurance failures, as well as corrects the soft errors through refreshing. Using the HfO2/ Hf RRAM array, our simulation results show that the proposed solution increases the resilience to soft-error of an 8Gb RRAM-based memory by 80% with a small penalty on the energy and delay of the Read operations (6% and 0.4% respectively). The proposed methodology can be used for other RRAM arrays with minor modifications to the design parameters depending on the characteristics of RRAM cell.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125341649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present the design of stochastic computing systems based on sequential logic to implement arbitrary polynomial functions. Stochastic computing is an emerging alternative computing paradigm that performs arithmetic operations on real-valued data represented as random bitstreams using digital logic gates. Stochastic computing systems are capable of realizing complex mathematical operations using a small number of hardware resources by expressing the computation in terms of probabilities. Moreover, the stochastic representation of data using random bitstreams is extremely robust against bit errors. We present a systematic approach to implement arbitrary polynomial functions in stochastic computing using sequential logic, and compare our approach against prior conventional and stochastic implementations.
{"title":"Polynomial arithmetic using sequential stochastic logic","authors":"N. Saraf, K. Bazargan","doi":"10.1145/2902961.2902981","DOIUrl":"https://doi.org/10.1145/2902961.2902981","url":null,"abstract":"We present the design of stochastic computing systems based on sequential logic to implement arbitrary polynomial functions. Stochastic computing is an emerging alternative computing paradigm that performs arithmetic operations on real-valued data represented as random bitstreams using digital logic gates. Stochastic computing systems are capable of realizing complex mathematical operations using a small number of hardware resources by expressing the computation in terms of probabilities. Moreover, the stochastic representation of data using random bitstreams is extremely robust against bit errors. We present a systematic approach to implement arbitrary polynomial functions in stochastic computing using sequential logic, and compare our approach against prior conventional and stochastic implementations.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126676483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nidhi Batra, Pawan Sehgal, S. Kaushik, M. Hashmi, Sudesh Bhalla, Anuj Grover
In advanced technology nodes, the process variations deteriorate SRAM performance and greatly affect yield. It is necessary to formulate yield estimation models to optimize SRAMs and effectively trade-off area, performance and robustness. We propose models that in addition to enabling yield estimates also enable evaluation of lowering minimum operational voltage (VDDMIN). We present a quantitative analysis for SNM limited SRAM yield using Design of Experiments (DOE) method. The proposed framework for yield based design can also utilize recovery techniques like Error Correcting Codes (ECC) and redundancy and quantifies yield, area, and VDDmin improvements. We also present a case study that trades-off ECC recovery budget, VDDmin and area gain. We show 25% improvement in area and VDDmin lowering by 300mV at constant yield levels by using 50% of ECC recovery budget.
{"title":"Static noise margin based yield modelling of 6T SRAM for area and minimum operating voltage improvement using recovery techniques","authors":"Nidhi Batra, Pawan Sehgal, S. Kaushik, M. Hashmi, Sudesh Bhalla, Anuj Grover","doi":"10.1145/2902961.2903005","DOIUrl":"https://doi.org/10.1145/2902961.2903005","url":null,"abstract":"In advanced technology nodes, the process variations deteriorate SRAM performance and greatly affect yield. It is necessary to formulate yield estimation models to optimize SRAMs and effectively trade-off area, performance and robustness. We propose models that in addition to enabling yield estimates also enable evaluation of lowering minimum operational voltage (VDDMIN). We present a quantitative analysis for SNM limited SRAM yield using Design of Experiments (DOE) method. The proposed framework for yield based design can also utilize recovery techniques like Error Correcting Codes (ECC) and redundancy and quantifies yield, area, and VDDmin improvements. We also present a case study that trades-off ECC recovery budget, VDDmin and area gain. We show 25% improvement in area and VDDmin lowering by 300mV at constant yield levels by using 50% of ECC recovery budget.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127876084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In today's competitive market, a company's success is strongly dependent on delivering sophisticated and state-of-the-art IPs prior to their competitors. To take a short cut, a company may resort to reverse engineering or pirating their competitor's IP. In this paper, we examine the feasibility of extracting the design of a secure IP from one technology and using it in another. In particular, we start by extracting the IP from an FPGA vendor tool flow and map the IP blocks to an ASIC technology. We show that there is not a significant degradation in quality compared to starting with the original source, thus showing that taking a pirated IP from an FPGA and using it in another technology is viable, and therefore worth doing. This demonstrates a clear motivation for patching a vulnerability in FPGA CAD tools. Note that the intent of this work is not to promote the piracy of IPs. Instead, the goal is to demonstrate a mechanism for extracting a design as a means towards understanding what methods of pirating are possible, and whether they can be prevented.
{"title":"Extracting designs of secure IPs using FPGA CAD tools","authors":"Vincent Mirian, P. Chow","doi":"10.1145/2902961.2903033","DOIUrl":"https://doi.org/10.1145/2902961.2903033","url":null,"abstract":"In today's competitive market, a company's success is strongly dependent on delivering sophisticated and state-of-the-art IPs prior to their competitors. To take a short cut, a company may resort to reverse engineering or pirating their competitor's IP. In this paper, we examine the feasibility of extracting the design of a secure IP from one technology and using it in another. In particular, we start by extracting the IP from an FPGA vendor tool flow and map the IP blocks to an ASIC technology. We show that there is not a significant degradation in quality compared to starting with the original source, thus showing that taking a pirated IP from an FPGA and using it in another technology is viable, and therefore worth doing. This demonstrates a clear motivation for patching a vulnerability in FPGA CAD tools. Note that the intent of this work is not to promote the piracy of IPs. Instead, the goal is to demonstrate a mechanism for extracting a design as a means towards understanding what methods of pirating are possible, and whether they can be prevented.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114974162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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