An all-digital self-adaptive clock generation system capable of autonomously adapt the clock frequency to compensate the effects of static spatially heterogeneous (SSHet) PVTA variations is presented. The design uses time-to-digital converters (TDCs) as delay sensors and a variable length ring oscillator (VLRO) as clock generator. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to allocate them. The proposed system has been implemented in a silicon chip using a 65nm process. The fabricated chip has been used to test the system adaptive capabilities under SSHet voltage variations. Measurement results show that it effectively adapts the VLRO length, and hence the clock frequency, to the supply voltage variations.
{"title":"ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system","authors":"J. Perez-Puigdemont, F. Moll","doi":"10.1145/2902961.2903006","DOIUrl":"https://doi.org/10.1145/2902961.2903006","url":null,"abstract":"An all-digital self-adaptive clock generation system capable of autonomously adapt the clock frequency to compensate the effects of static spatially heterogeneous (SSHet) PVTA variations is presented. The design uses time-to-digital converters (TDCs) as delay sensors and a variable length ring oscillator (VLRO) as clock generator. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to allocate them. The proposed system has been implemented in a silicon chip using a 65nm process. The fabricated chip has been used to test the system adaptive capabilities under SSHet voltage variations. Measurement results show that it effectively adapts the VLRO length, and hence the clock frequency, to the supply voltage variations.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper deals with obtaining the minimum operating voltage of memory arrays based on TFET SRAM cells. First, we compare the I-V characteristics of two TFETs and one FDSOI using SPICE simulations. The results reveal that TFET devices exhibit high ON/OFF current ratios at different power supply voltage levels. This observation suggests a higher stability for SRAM cells based on these devices. Next, the characteristics of 6T SRAM cells implemented using minimum sized transistors based on these three device structures are compared. The comparison, which considers two TFET cell structures, i.e., inward and outward SRAMs, is performed at different supply voltages. The results for the hold static noise margin show that at low supply voltages (i.e., below 300mV), the FDSOI SRAM cell cannot hold data whereas both the inward and outward structures of TFET have acceptable noise margins at all supply voltages. Among the two TFET structures, the outward cell is selected because of higher speed especially for the write operation. TFET SRAMs suffer from long read access latency at ultra-low supply voltages (e.g., 150mV). The problem, however, may be overcome by using the negative GND read-assist technique. The results show that for a 32×32 TFET outward SRAM array, the minimum energy consumption (energy-delay product) may be achieved at the supply voltage of 200mV (300mV) with 1.32GHz (4.55GHz) as the read access frequency.
{"title":"Optimizing the operating voltage of tunnel FET-based SRAM arrays equipped with read/write assist circuitry","authors":"H. Afzali-Kusha, A. Shafaei, Massoud Pedram","doi":"10.1145/2902961.2903031","DOIUrl":"https://doi.org/10.1145/2902961.2903031","url":null,"abstract":"This paper deals with obtaining the minimum operating voltage of memory arrays based on TFET SRAM cells. First, we compare the I-V characteristics of two TFETs and one FDSOI using SPICE simulations. The results reveal that TFET devices exhibit high ON/OFF current ratios at different power supply voltage levels. This observation suggests a higher stability for SRAM cells based on these devices. Next, the characteristics of 6T SRAM cells implemented using minimum sized transistors based on these three device structures are compared. The comparison, which considers two TFET cell structures, i.e., inward and outward SRAMs, is performed at different supply voltages. The results for the hold static noise margin show that at low supply voltages (i.e., below 300mV), the FDSOI SRAM cell cannot hold data whereas both the inward and outward structures of TFET have acceptable noise margins at all supply voltages. Among the two TFET structures, the outward cell is selected because of higher speed especially for the write operation. TFET SRAMs suffer from long read access latency at ultra-low supply voltages (e.g., 150mV). The problem, however, may be overcome by using the negative GND read-assist technique. The results show that for a 32×32 TFET outward SRAM array, the minimum energy consumption (energy-delay product) may be achieved at the supply voltage of 200mV (300mV) with 1.32GHz (4.55GHz) as the read access frequency.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130335606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Chakraborty, Santanu Kundu, D. Agrawal, Sanjay Shinde, Jacob Mathews, R. K. James
Leakage power minimization is one of the key aspects of modern multi-million low power system-on-chip (SoC) design. In post timing-closure phase, leakage-in-place-optimization (LIPO) is generally adopted to reduce leakage power by swapping high-leaky cells in the timing-data-paths by low-leaky ones of the same footprint. The traditional LIPO does not touch the clock network for leakage recovery. This paper investigates the opportunity to reduce leakage power further of an already leakage-power-minimized (by LIPO), timing closed design by minimally altering the balanced clock tree. The proposed method, Opportunistic LIPO, intends to borrow unused positive-slack from downstream (and/or upstream) paths, may or may not be at immediate neighborhood, and provide a “positive skew” (and/or “negative skew”) at the capture (and/or launch) clock edge of the current path. In this way, the proposed scheme creates an opportunity in the current path to increase the low-leaky cells distribution. Experimental results, computed over some practical duration (less than 48 hours), on some industry-standard design based on 28nm technology, of having around 50 million gates, shows that the proposed algorithm, “Opportunistic LIPO”, achieves 10-30% better leakage power as compared to traditional LIPO without increasing the number of timing violations and having no significant impact on overall area.
{"title":"Leakage power minimization in deep sub-micron technology by exploiting positive slacks of dependent paths","authors":"T. Chakraborty, Santanu Kundu, D. Agrawal, Sanjay Shinde, Jacob Mathews, R. K. James","doi":"10.1145/2902961.2902991","DOIUrl":"https://doi.org/10.1145/2902961.2902991","url":null,"abstract":"Leakage power minimization is one of the key aspects of modern multi-million low power system-on-chip (SoC) design. In post timing-closure phase, leakage-in-place-optimization (LIPO) is generally adopted to reduce leakage power by swapping high-leaky cells in the timing-data-paths by low-leaky ones of the same footprint. The traditional LIPO does not touch the clock network for leakage recovery. This paper investigates the opportunity to reduce leakage power further of an already leakage-power-minimized (by LIPO), timing closed design by minimally altering the balanced clock tree. The proposed method, Opportunistic LIPO, intends to borrow unused positive-slack from downstream (and/or upstream) paths, may or may not be at immediate neighborhood, and provide a “positive skew” (and/or “negative skew”) at the capture (and/or launch) clock edge of the current path. In this way, the proposed scheme creates an opportunity in the current path to increase the low-leaky cells distribution. Experimental results, computed over some practical duration (less than 48 hours), on some industry-standard design based on 28nm technology, of having around 50 million gates, shows that the proposed algorithm, “Opportunistic LIPO”, achieves 10-30% better leakage power as compared to traditional LIPO without increasing the number of timing violations and having no significant impact on overall area.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130998392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a novel on-chip impedance calibration methodology for a LPDDR4 (low power double data rate) application is proposed. The background calibration operates to compensate mismatches and variations of the output NMOS drivers from process and temperature variations. The impedance matching concept uses process sensor and temperature monitoring sensors closely located to DQ pins as a means to detect output driver transistor mismatches due to process and temperature variations. In addition, digitized sensor outputs from ADCs are used as inputs of look-up tables, which control calibration codes of the transmitter driver. The proposed circuitry is designed with DRAM bidirectional transceiver and implemented using a standard 180nm CMOS technology, and the impedance calibration technique is demonstrated with external termination resistance of 40/48/60/80/120/240 ohm, respectively. In the receiver end, a PMOS input sense amplifier is designed considering the required common mode range for the LVSTL (low voltage swing termination logic) signal interface, and an adaptive gain control scheme is also applied on the receiver design. The process sensor is utilized to control the gain factor of the receiver. The active area including power-ring of the transmitter is 14.4mm2 with only 0.48mm2 of the proposed calibration circuit overhead.
{"title":"A novel on-chip impedance calibration method for LPDDR4 interface between DRAM and AP/SoC","authors":"Yongsuk Choi, Yong-Bin Kim","doi":"10.1145/2902961.2902982","DOIUrl":"https://doi.org/10.1145/2902961.2902982","url":null,"abstract":"In this paper, a novel on-chip impedance calibration methodology for a LPDDR4 (low power double data rate) application is proposed. The background calibration operates to compensate mismatches and variations of the output NMOS drivers from process and temperature variations. The impedance matching concept uses process sensor and temperature monitoring sensors closely located to DQ pins as a means to detect output driver transistor mismatches due to process and temperature variations. In addition, digitized sensor outputs from ADCs are used as inputs of look-up tables, which control calibration codes of the transmitter driver. The proposed circuitry is designed with DRAM bidirectional transceiver and implemented using a standard 180nm CMOS technology, and the impedance calibration technique is demonstrated with external termination resistance of 40/48/60/80/120/240 ohm, respectively. In the receiver end, a PMOS input sense amplifier is designed considering the required common mode range for the LVSTL (low voltage swing termination logic) signal interface, and an adaptive gain control scheme is also applied on the receiver design. The process sensor is utilized to control the gain factor of the receiver. The active area including power-ring of the transmitter is 14.4mm2 with only 0.48mm2 of the proposed calibration circuit overhead.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114686119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses computing complex functions using unipolar stochastic logic. Stochastic computing requires simple logic gates and is inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. Implementations of complex functions cost extremely low hardware complexity compared to traditional two's complement implementation. In this paper an approach based on polynomial factorization is proposed to compute functions in unipolar stochastic logic. In this approach, functions are expressed using polynomials, which are derived from Taylor expansion or Lagrange interpolation. Polynomials are implemented in stochastic logic by using factorization. Experimental results in terms of accuracy and hardware complexity are presented to compare the proposed designs of complex functions with previous implementations using Bernstein polynomials.
{"title":"Computing complex functions using factorization in unipolar stochastic logic","authors":"Yin Liu, K. Parhi","doi":"10.1145/2902961.2902999","DOIUrl":"https://doi.org/10.1145/2902961.2902999","url":null,"abstract":"This paper addresses computing complex functions using unipolar stochastic logic. Stochastic computing requires simple logic gates and is inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. Implementations of complex functions cost extremely low hardware complexity compared to traditional two's complement implementation. In this paper an approach based on polynomial factorization is proposed to compute functions in unipolar stochastic logic. In this approach, functions are expressed using polynomials, which are derived from Taylor expansion or Lagrange interpolation. Polynomials are implemented in stochastic logic by using factorization. Experimental results in terms of accuracy and hardware complexity are presented to compare the proposed designs of complex functions with previous implementations using Bernstein polynomials.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114853314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many lattice-based cryptosystems are based on the security of the Ring learning with errors (Ring-LWE) problem. The most critical and computationally intensive operation of these Ring-LWE based cryptosystems is polynomial multiplication. In this paper, we exploit the number theoretic transform to build a high-speed polynomial multiplier for the Ring-LWE based public key cryptosystems. We present a versatile pipelined polynomial multiplication architecture to calculate the product of two η-degree polynomials in about ((n lg n)/4+n/2) clock cycles. In addition, we introduce several optimization techniques to reduce the required ROM storage. The experimental results on a Spartan-6 FPGA show that the proposed hardware architecture can achieve a speedup of on average 2.25 than the state of the art of high-speed design. Meanwhile, our design is able to save up to 47.06% memory blocks.
{"title":"High-speed polynomial multiplier architecture for ring-LWE based public key cryptosystems","authors":"Chaohui Du, Guoqiang Bai, Xingjun Wu","doi":"10.1145/2902961.2902969","DOIUrl":"https://doi.org/10.1145/2902961.2902969","url":null,"abstract":"Many lattice-based cryptosystems are based on the security of the Ring learning with errors (Ring-LWE) problem. The most critical and computationally intensive operation of these Ring-LWE based cryptosystems is polynomial multiplication. In this paper, we exploit the number theoretic transform to build a high-speed polynomial multiplier for the Ring-LWE based public key cryptosystems. We present a versatile pipelined polynomial multiplication architecture to calculate the product of two η-degree polynomials in about ((n lg n)/4+n/2) clock cycles. In addition, we introduce several optimization techniques to reduce the required ROM storage. The experimental results on a Spartan-6 FPGA show that the proposed hardware architecture can achieve a speedup of on average 2.25 than the state of the art of high-speed design. Meanwhile, our design is able to save up to 47.06% memory blocks.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128804310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Intelligent things, medical devices, vehicles and factories, all part of cyberphysical systems, will only be secure if we can build devices that can perform the mathematically demanding cryptographic operations in an efficient way. Unfortunately, many of devices operate under extremely limited power, energy and area constraints. Yet we expect that they can execute, often in real-time, the symmetric key, public key and/or hash functions needed for the application. At the same time, we request that the implementations are also secure against a wide range of physical attacks. This presentation will focus on the design methods to realize cryptographic operations on resource constrained devices. To reach the extremely low power, low energy and area budgets, we need to consider in an integrated way the protocols, the algorithms, the architectures and the circuit aspects of the application. These concepts will be illustrated with the design of several cryptographic co-processors suitable for implementation in embedded context.
{"title":"VLSI design methods for low power embedded encryption","authors":"I. Verbauwhede","doi":"10.1145/2902961.2902963","DOIUrl":"https://doi.org/10.1145/2902961.2902963","url":null,"abstract":"Intelligent things, medical devices, vehicles and factories, all part of cyberphysical systems, will only be secure if we can build devices that can perform the mathematically demanding cryptographic operations in an efficient way. Unfortunately, many of devices operate under extremely limited power, energy and area constraints. Yet we expect that they can execute, often in real-time, the symmetric key, public key and/or hash functions needed for the application. At the same time, we request that the implementations are also secure against a wide range of physical attacks. This presentation will focus on the design methods to realize cryptographic operations on resource constrained devices. To reach the extremely low power, low energy and area budgets, we need to consider in an integrated way the protocols, the algorithms, the architectures and the circuit aspects of the application. These concepts will be illustrated with the design of several cryptographic co-processors suitable for implementation in embedded context.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128861664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Marthi, Sheikh Rufsan Reza, N. Hossain, J. Millithaler, M. Margala, I. Íñiguez-de-la-Torre, J. Mateos, T. González
In this paper, study of different digital logic circuits developed using two-BDT ballistic nanostructure is presented. New D flipflop (DFF) based on the same nanostructure is also proposed. The logic structure comprises two ballistic deflection transistors (BDTs) that are experimentally proven to operate at Terahertz frequencies. The non-linear behavior of the BDT's transfer characteristic has been perfectly reproduced by means of Monte Carlo simulations, where a specific attention has been devoted to surface charges. An analytical model built on the results of advanced MC simulations has been integrated into a behavioral Verilog AMS module to confirm the functionality of the circuit design. The module is used to analyze operating conditions of different combinational circuits and to investigate the feasibility of DFF design using BDT nanostructure. The simulation results indicate successful operation of both combinational and sequential circuits developed using two-BDT logic structure under proper biasing of gate and source terminals. The operating voltages of the proposed DFF are estimated to be ± 225mV.
{"title":"Modeling and study of two-BDT-nanostructure based sequential logic circuits","authors":"P. Marthi, Sheikh Rufsan Reza, N. Hossain, J. Millithaler, M. Margala, I. Íñiguez-de-la-Torre, J. Mateos, T. González","doi":"10.1145/2902961.2903001","DOIUrl":"https://doi.org/10.1145/2902961.2903001","url":null,"abstract":"In this paper, study of different digital logic circuits developed using two-BDT ballistic nanostructure is presented. New D flipflop (DFF) based on the same nanostructure is also proposed. The logic structure comprises two ballistic deflection transistors (BDTs) that are experimentally proven to operate at Terahertz frequencies. The non-linear behavior of the BDT's transfer characteristic has been perfectly reproduced by means of Monte Carlo simulations, where a specific attention has been devoted to surface charges. An analytical model built on the results of advanced MC simulations has been integrated into a behavioral Verilog AMS module to confirm the functionality of the circuit design. The module is used to analyze operating conditions of different combinational circuits and to investigate the feasibility of DFF design using BDT nanostructure. The simulation results indicate successful operation of both combinational and sequential circuits developed using two-BDT logic structure under proper biasing of gate and source terminals. The operating voltages of the proposed DFF are estimated to be ± 225mV.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125305251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Physical unclonable functions (PUFs) leverage minute silicon process variations to produce device-tied secret keys. The energy and area costs of creating keys from PUFs can far exceed the costs of the basic PUF circuits alone. Minimizing the end-to-end cost of reliable key generation is critical to enable broader adoption of PUFs. In this work, we introduce a new style of PUF that employs autonomous majority voting to improve reliability. The novelty of this design, and the source of its efficiency, is that the inherently sequential majority voting procedure is carried out by a self-timed circuit without orchestration by a global clock. We use circuit simulation to evaluate the energy versus reliability tradeoffs achieved by different parameterizations of the design, to show that the design performs well across a range of supply voltages, and to quantify the robustness of the design across a broad range of operating temperatures.
{"title":"A clockless sequential PUF with autonomous majority voting","authors":"Xiaolin Xu, Daniel E. Holcomb","doi":"10.1145/2902961.2903029","DOIUrl":"https://doi.org/10.1145/2902961.2903029","url":null,"abstract":"Physical unclonable functions (PUFs) leverage minute silicon process variations to produce device-tied secret keys. The energy and area costs of creating keys from PUFs can far exceed the costs of the basic PUF circuits alone. Minimizing the end-to-end cost of reliable key generation is critical to enable broader adoption of PUFs. In this work, we introduce a new style of PUF that employs autonomous majority voting to improve reliability. The novelty of this design, and the source of its efficiency, is that the inherently sequential majority voting procedure is carried out by a self-timed circuit without orchestration by a global clock. We use circuit simulation to evaluate the energy versus reliability tradeoffs achieved by different parameterizations of the design, to show that the design performs well across a range of supply voltages, and to quantify the robustness of the design across a broad range of operating temperatures.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122221573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, S. Bhunia
Inherent stochastic physical mechanisms in emerging nonvolatile memories (NVMs), such as resistive random-access-memory (RRAM), have recently been explored for hardware security applications. Unlike the conventional silicon Physical Unclonable Functions (PUFs) that are solely based on manufacturing process variation, RRAM has some intrinsic randomness in its physical mechanisms that can be utilized as entropy sources; for instance, resistance variation, random telegraph noise, and probabilistic switching behaviors. This paper reviews the challenges and opportunities in building security primitives with emerging devices. In particular, it presents research progress of RRAM-based hardware security primitives, including PUF and True Random Number Generator (TRNG).
{"title":"Security primitive design with nanoscale devices: A case study with resistive RAM","authors":"Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, S. Bhunia","doi":"10.1145/2902961.2903042","DOIUrl":"https://doi.org/10.1145/2902961.2903042","url":null,"abstract":"Inherent stochastic physical mechanisms in emerging nonvolatile memories (NVMs), such as resistive random-access-memory (RRAM), have recently been explored for hardware security applications. Unlike the conventional silicon Physical Unclonable Functions (PUFs) that are solely based on manufacturing process variation, RRAM has some intrinsic randomness in its physical mechanisms that can be utilized as entropy sources; for instance, resistance variation, random telegraph noise, and probabilistic switching behaviors. This paper reviews the challenges and opportunities in building security primitives with emerging devices. In particular, it presents research progress of RRAM-based hardware security primitives, including PUF and True Random Number Generator (TRNG).","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"5 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123438302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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