Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this work, we use a new technique based on association rule mining to plan and place noise sensors. This new methodology can consider the miss rate (the probability of any node occurring voltage emergency without any detection by placed sensors) and simultaneously minimize the number of sensors utilized. The results show that our approach is very effective in converging the miss rate to zero by the least number of sensors. Compared with the state-of-the-art, we can reduce the number of sensors by half in benchmarks while the miss rate is comparable or even smaller than the prior work.
{"title":"A new methodology for noise sensor placement based on association rule mining","authors":"Yu-Hsiang Hung, Sheng-Hsin Fang, Hung-Ming Chen, Shen-Min Chen, Chang-Tzu Lin, Chia-Hsin Lee","doi":"10.1145/2902961.2902973","DOIUrl":"https://doi.org/10.1145/2902961.2902973","url":null,"abstract":"Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this work, we use a new technique based on association rule mining to plan and place noise sensors. This new methodology can consider the miss rate (the probability of any node occurring voltage emergency without any detection by placed sensors) and simultaneously minimize the number of sensors utilized. The results show that our approach is very effective in converging the miss rate to zero by the least number of sensors. Compared with the state-of-the-art, we can reduce the number of sensors by half in benchmarks while the miss rate is comparable or even smaller than the prior work.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126498683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma
Novel device with multiple FPGAs on-chip based on interposer interconnection has emerged to resolve the IOs limit and improve the inter-FPGA communication delay. However, new challenges arise for the placement on such architecture. Firstly, existing work does not consider the detailed models for the path wirelength and delay estimation for interposer, which may significantly affect the placement quality. Secondly, previous work is mostly based on traditional tile-based placement which is slow for the placement of large design on multiple FPGAs. In this paper, we propose a new fast two-stage modular placement flow for interposer based multiple FPGAs aiming for delay optimization with the incorporation of a detailed interposer routing model for wirelength and delay estimation. Firstly, we adopt the force-directed method for its global property to get an efficient solution as a start point of the placement. Secondly, we adopt the simulated annealing (SA) for its efficiency and effectiveness in searching the refinement solution. In order to speed up the refinement, the hierarchical B*-tree (HB*-tree) is employed to enable a fast search and convergence. The experiments demonstrate that our flow can achieve an efficient solution in a comparable time. The proposed approach is scalable to different design size.
{"title":"Modular placement for interposer based multi-FPGA systems","authors":"Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma","doi":"10.1145/2902961.2903025","DOIUrl":"https://doi.org/10.1145/2902961.2903025","url":null,"abstract":"Novel device with multiple FPGAs on-chip based on interposer interconnection has emerged to resolve the IOs limit and improve the inter-FPGA communication delay. However, new challenges arise for the placement on such architecture. Firstly, existing work does not consider the detailed models for the path wirelength and delay estimation for interposer, which may significantly affect the placement quality. Secondly, previous work is mostly based on traditional tile-based placement which is slow for the placement of large design on multiple FPGAs. In this paper, we propose a new fast two-stage modular placement flow for interposer based multiple FPGAs aiming for delay optimization with the incorporation of a detailed interposer routing model for wirelength and delay estimation. Firstly, we adopt the force-directed method for its global property to get an efficient solution as a start point of the placement. Secondly, we adopt the simulated annealing (SA) for its efficiency and effectiveness in searching the refinement solution. In order to speed up the refinement, the hierarchical B*-tree (HB*-tree) is employed to enable a fast search and convergence. The experiments demonstrate that our flow can achieve an efficient solution in a comparable time. The proposed approach is scalable to different design size.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"3 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132707896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Today, it would be difficult to find medical device technology that does not critically depend on computer software. Network connectivity and wireless communication has transformed the delivery of patient care. The technology often enables patients to lead more normal and healthy lives. However, medical devices that rely on software (e.g., drug infusion pumps, linear accelerators, pacemakers) also inherit the pesky cybersecurity risks endemic to computing. What's special about medical devices and cybersecurity? What's hype and what's real? What can history teach us? How are international standards bodies and regulatory cybersecurity requirements changing the global manufacture of medical devices? This talk will provide a glimpse into the risks, benefits, and regulatory issues for medical device cybersecurity and innovation of trustworthy medical device software.
{"title":"Medical device security: The first 165 years","authors":"Kevin Fu","doi":"10.1145/2902961.2902964","DOIUrl":"https://doi.org/10.1145/2902961.2902964","url":null,"abstract":"Today, it would be difficult to find medical device technology that does not critically depend on computer software. Network connectivity and wireless communication has transformed the delivery of patient care. The technology often enables patients to lead more normal and healthy lives. However, medical devices that rely on software (e.g., drug infusion pumps, linear accelerators, pacemakers) also inherit the pesky cybersecurity risks endemic to computing. What's special about medical devices and cybersecurity? What's hype and what's real? What can history teach us? How are international standards bodies and regulatory cybersecurity requirements changing the global manufacture of medical devices? This talk will provide a glimpse into the risks, benefits, and regulatory issues for medical device cybersecurity and innovation of trustworthy medical device software.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128059188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Despite many attractive advantages, Null Convention Logic (NCL) remains to be a niche largely due to its high implementation costs. Using emerging spintronic devices, this paper proposes a Domain-Wall-Motion-based NCL circuit design methodology that achieves approximately 30× and 8× improvements in energy efficiency and chip layout area, respectively, over its equivalent CMOS design, while maintaining similar delay performance for a 32-bit full adder. These advantages are made possible mostly by exploiting the domain wall motion physics to natively realize the hysteresis critically needed in NCL. More Interestingly, this design choice achieves ultra-high robustness by allowing spintronic device parameters to vary within a predetermined range while still achieving correct operations.
{"title":"Ultra-robust null convention logic circuit with emerging domain wall devices","authors":"Yu Bai, Bo Hu, W. Kuang, Mingjie Lin","doi":"10.1145/2902961.2903019","DOIUrl":"https://doi.org/10.1145/2902961.2903019","url":null,"abstract":"Despite many attractive advantages, Null Convention Logic (NCL) remains to be a niche largely due to its high implementation costs. Using emerging spintronic devices, this paper proposes a Domain-Wall-Motion-based NCL circuit design methodology that achieves approximately 30× and 8× improvements in energy efficiency and chip layout area, respectively, over its equivalent CMOS design, while maintaining similar delay performance for a 32-bit full adder. These advantages are made possible mostly by exploiting the domain wall motion physics to natively realize the hysteresis critically needed in NCL. More Interestingly, this design choice achieves ultra-high robustness by allowing spintronic device parameters to vary within a predetermined range while still achieving correct operations.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122504156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
New hardware security threats are identified in emerging three-dimensional (3D) integrated circuits (ICs) and potential counter-measures are introduced. Trigger and payload mechanisms for future 3D hardware Trojans are predicted. Furthermore, a novel, network-on-chip based 3D obfuscation method is proposed to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. Simulation results demonstrate that the proposed method effectively obfuscates the cross-plane communication by increasing the reverse engineering time by approximately 5× as compared to using direct through silicon via (TSV) connections. The proposed method consumes approximately one fifth the area and power of a typical network-on-chip designed in a 65 nm technology, exhibiting limited overhead.
{"title":"Hardware security threats and potential countermeasures in emerging 3D ICs","authors":"Jaya Dofe, Qiaoyan Yu, Hailang Wang, E. Salman","doi":"10.1145/2902961.2903014","DOIUrl":"https://doi.org/10.1145/2902961.2903014","url":null,"abstract":"New hardware security threats are identified in emerging three-dimensional (3D) integrated circuits (ICs) and potential counter-measures are introduced. Trigger and payload mechanisms for future 3D hardware Trojans are predicted. Furthermore, a novel, network-on-chip based 3D obfuscation method is proposed to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. Simulation results demonstrate that the proposed method effectively obfuscates the cross-plane communication by increasing the reverse engineering time by approximately 5× as compared to using direct through silicon via (TSV) connections. The proposed method consumes approximately one fifth the area and power of a typical network-on-chip designed in a 65 nm technology, exhibiting limited overhead.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116623218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Large-scale MPSoCs requires a scalable and dynamic real-time (RT) task scheduler, able to handle non-deterministic computational behaviors. Current proposals for MPSoCs have limitations, as lack of scalability, complex static steps, validation with abstract models, or are not flexible to enable changes at runtime of the RT constraints. This work proposes a hierarchical task scheduler with monitoring features. The scheduler is dynamic, supporting changes in RT constraints at runtime. An API enables these features allowing to the application developer to reconfigure the tasks' period, deadline, and execution time by annotating the task code. At runtime, according to the task execution, the scheduler handles the API calls and adjust itself to ensure RT guarantees according to the new constraints. Scalability is ensured by dividing the scheduler into two hierarchical levels: LS (Local Schedulers), and CS (Cluster Schedulers). The LS runs at the processor level, using the LST (Least Slack-Time) algorithm. The CS runs at the cluster level, i.e., a group of processors controlled by a manager processor. The CS receives messages from the LSs, informing the processor slack-time, deadline violations, and RT changes. The CS implements an RT adaptation heuristic, triggering task migrations according to RT reconfiguration or deadline misses. Results show a negligible overhead in the applications' execution time and the fulfillment of the applications' RT constraints even with a high degree of resources sharing, in both processors and NoC.
{"title":"Dynamic real-time scheduler for large-scale MPSoCs","authors":"Marcelo Ruaro, F. Moraes","doi":"10.1145/2902961.2903027","DOIUrl":"https://doi.org/10.1145/2902961.2903027","url":null,"abstract":"Large-scale MPSoCs requires a scalable and dynamic real-time (RT) task scheduler, able to handle non-deterministic computational behaviors. Current proposals for MPSoCs have limitations, as lack of scalability, complex static steps, validation with abstract models, or are not flexible to enable changes at runtime of the RT constraints. This work proposes a hierarchical task scheduler with monitoring features. The scheduler is dynamic, supporting changes in RT constraints at runtime. An API enables these features allowing to the application developer to reconfigure the tasks' period, deadline, and execution time by annotating the task code. At runtime, according to the task execution, the scheduler handles the API calls and adjust itself to ensure RT guarantees according to the new constraints. Scalability is ensured by dividing the scheduler into two hierarchical levels: LS (Local Schedulers), and CS (Cluster Schedulers). The LS runs at the processor level, using the LST (Least Slack-Time) algorithm. The CS runs at the cluster level, i.e., a group of processors controlled by a manager processor. The CS receives messages from the LSs, informing the processor slack-time, deadline violations, and RT changes. The CS implements an RT adaptation heuristic, triggering task migrations according to RT reconfiguration or deadline misses. Results show a negligible overhead in the applications' execution time and the fulfillment of the applications' RT constraints even with a high degree of resources sharing, in both processors and NoC.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115942787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Monte-Carlo method is the method of choice for accurate yield estimation. Standard Monte-Carlo methods suffer from a huge computational burden even though they are very accurate. Recently a Monte-Carlo method was proposed for the parametric yield estimation of digital integrated circuits [13] that achieves significant computational savings at no loss of accuracy by focusing on those statistical variables that have a significant impact on yield. We adapt this technique to the context of analog circuit yield estimation. The inputs to the proposed method are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The technique of [13] operates on a linear model of circuit variations. In our work we first convexify the nonlinear design constraints to obtain a convex feasible region. We then consider an accurate polytope-approximation of the convex feasible region by taking tangent hyperplanes at various points on the surface of the convex region. The hyperplanes give rise to a matrix of design variable sensitivities, which is then used to glean information about the importance of design variables for yield estimation. Finally the knowledge of which design variables are very important for yield estimation is used to allow the Monte-Carlo technique achieve a lower error compared to standard Monte-Carlo in the same amount of simulation time.
{"title":"Parameter-importance based Monte-Carlo technique for variation-aware analog yield optimization","authors":"Sita Kondamadugula, S. Naidu","doi":"10.1145/2902961.2903018","DOIUrl":"https://doi.org/10.1145/2902961.2903018","url":null,"abstract":"The Monte-Carlo method is the method of choice for accurate yield estimation. Standard Monte-Carlo methods suffer from a huge computational burden even though they are very accurate. Recently a Monte-Carlo method was proposed for the parametric yield estimation of digital integrated circuits [13] that achieves significant computational savings at no loss of accuracy by focusing on those statistical variables that have a significant impact on yield. We adapt this technique to the context of analog circuit yield estimation. The inputs to the proposed method are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The technique of [13] operates on a linear model of circuit variations. In our work we first convexify the nonlinear design constraints to obtain a convex feasible region. We then consider an accurate polytope-approximation of the convex feasible region by taking tangent hyperplanes at various points on the surface of the convex region. The hyperplanes give rise to a matrix of design variable sensitivities, which is then used to glean information about the importance of design variables for yield estimation. Finally the knowledge of which design variables are very important for yield estimation is used to allow the Monte-Carlo technique achieve a lower error compared to standard Monte-Carlo in the same amount of simulation time.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115203966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The internet of things (IoT) is quickly emerging as the next major domain for embedded computer systems. Although the term IoT could be defined in a variety of different ways, IoT always encompasses typically ordinary devices (e.g., thermostats and kitchen appliances) augmented with computational power that allows regular communication via the internet. Given the simplicity of typical IoT devices, their on-board computer systems must also be simple in the sense that they be small and consume minimal power. However, the IoT itself presents new privacy and security concerns that must be considered when designing IoT devices. In order to provide robust security with minimal area and power overhead, it is the premise of this paper that IoT security be implemented using nanoelectronic security primitives and nano-enabled security protocols. Such nanoscale security primitives are expected to utilize a very small amount of area and consume a negligible amount of power, all while providing the required levels of security. This paper presents some examples of nanoelectronic security primitives and discusses how such circuits and systems can be of use for inclusion in emerging IoT devices.
{"title":"Security meets nanoelectronics for Internet of things applications","authors":"G. Rose","doi":"10.1145/2902961.2903045","DOIUrl":"https://doi.org/10.1145/2902961.2903045","url":null,"abstract":"The internet of things (IoT) is quickly emerging as the next major domain for embedded computer systems. Although the term IoT could be defined in a variety of different ways, IoT always encompasses typically ordinary devices (e.g., thermostats and kitchen appliances) augmented with computational power that allows regular communication via the internet. Given the simplicity of typical IoT devices, their on-board computer systems must also be simple in the sense that they be small and consume minimal power. However, the IoT itself presents new privacy and security concerns that must be considered when designing IoT devices. In order to provide robust security with minimal area and power overhead, it is the premise of this paper that IoT security be implemented using nanoelectronic security primitives and nano-enabled security protocols. Such nanoscale security primitives are expected to utilize a very small amount of area and consume a negligible amount of power, all while providing the required levels of security. This paper presents some examples of nanoelectronic security primitives and discusses how such circuits and systems can be of use for inclusion in emerging IoT devices.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Out of the many options available for thermal simulation of digital electronic systems, those based on solving an RC equivalent circuit of the thermal network are the most popular choice in the EDA community, as they provide a reasonable tradeoff between accuracy and complexity. HotSpot, in particular, has become the de-facto standard in these communities, although other simulators are also popular. These tools have many benefits, but they are relatively inefficient when performing thermal analysis for long simulation times, due to the occurrence of a large number of redundant computations intrinsic in the underlying models. This work shows how a standard description language, namely SystemC and its analog and mixed-signal (AMS) extension, can be used to successfully simulate the equivalent thermal network, by achieving accuracy comparable to existing simulators, yet with much better performance. Results show that SystemC-AMS thermal simulation can outpace HotSpot simulation by 10X to 90X, with speedup improving as the size of the thermal network increases, and negligible estimation error. As a further advantage, the adoption of the same language to describe functionality and temperature allows the simultaneous simulation of both dimensions with no co-simulation overhead, thus enhancing the overall design flow.
{"title":"Fast thermal simulation using SystemC-AMS","authors":"Yukai Chen, S. Vinco, E. Macii, M. Poncino","doi":"10.1145/2902961.2902975","DOIUrl":"https://doi.org/10.1145/2902961.2902975","url":null,"abstract":"Out of the many options available for thermal simulation of digital electronic systems, those based on solving an RC equivalent circuit of the thermal network are the most popular choice in the EDA community, as they provide a reasonable tradeoff between accuracy and complexity. HotSpot, in particular, has become the de-facto standard in these communities, although other simulators are also popular. These tools have many benefits, but they are relatively inefficient when performing thermal analysis for long simulation times, due to the occurrence of a large number of redundant computations intrinsic in the underlying models. This work shows how a standard description language, namely SystemC and its analog and mixed-signal (AMS) extension, can be used to successfully simulate the equivalent thermal network, by achieving accuracy comparable to existing simulators, yet with much better performance. Results show that SystemC-AMS thermal simulation can outpace HotSpot simulation by 10X to 90X, with speedup improving as the size of the thermal network increases, and negligible estimation error. As a further advantage, the adoption of the same language to describe functionality and temperature allows the simultaneous simulation of both dimensions with no co-simulation overhead, thus enhancing the overall design flow.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126171268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we explore the power/quality trade-off for streaming applications with a shift from the computation to the communication aspects of the design. The paper proposes a systematic exploration methodology to formulate and traverse power/quality trade-off for the class of adaptive streaming applications. The formalization enables to procedurally transition from a set of design requirements to architecture goals. The architecture goals can then be realized through design choices yielding system designs that meet the initial requirements. The reported results are based on an actual implementation of Mixture of Gaussian (MoG) background subtraction on Xilinx Zynq platform.
{"title":"Guiding power/quality exploration for communication-intense stream processing","authors":"H. Tabkhi, Majid Sabbagh, G. Schirner","doi":"10.1145/2902961.2903004","DOIUrl":"https://doi.org/10.1145/2902961.2903004","url":null,"abstract":"In this paper, we explore the power/quality trade-off for streaming applications with a shift from the computation to the communication aspects of the design. The paper proposes a systematic exploration methodology to formulate and traverse power/quality trade-off for the class of adaptive streaming applications. The formalization enables to procedurally transition from a set of design requirements to architecture goals. The architecture goals can then be realized through design choices yielding system designs that meet the initial requirements. The reported results are based on an actual implementation of Mixture of Gaussian (MoG) background subtraction on Xilinx Zynq platform.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128916622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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