Chip security has long been the domain of smart cards. These microcontrollers are specifically designed to thwart many different attacks in order to deliver typical security functions as payment cards, electronic passports, and access cards. With the advent of IoT everything is changing. Billions of devices will need security. We need access to our information sources and property. We expect our privacy to be respected and rely on the confidentiality of our sensitive information. We trust that our assets are well protected and cannot be manipulated by criminals. Can chip technology actually deliver on these demands? In this presentation we start by looking at the security architecture of electronic devices and mechanisms to restrict access and protect information. Then we explain the threat landscape and explain different types of attacks. Next we zoom in to security properties of the chips, which are at the core of all electronic devices. Finally we show how attack resistance can be tested and how chip vendors can gain assurance about the security of their products.
{"title":"Why is it so hard to make secure chips?","authors":"M. Witteman","doi":"10.1145/2902961.2902962","DOIUrl":"https://doi.org/10.1145/2902961.2902962","url":null,"abstract":"Chip security has long been the domain of smart cards. These microcontrollers are specifically designed to thwart many different attacks in order to deliver typical security functions as payment cards, electronic passports, and access cards. With the advent of IoT everything is changing. Billions of devices will need security. We need access to our information sources and property. We expect our privacy to be respected and rely on the confidentiality of our sensitive information. We trust that our assets are well protected and cannot be manipulated by criminals. Can chip technology actually deliver on these demands? In this presentation we start by looking at the security architecture of electronic devices and mechanisms to restrict access and protect information. Then we explain the threat landscape and explain different types of attacks. Next we zoom in to security properties of the chips, which are at the core of all electronic devices. Finally we show how attack resistance can be tested and how chip vendors can gain assurance about the security of their products.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multi-port memories are widely used as shared memory, such as register files, in a microprocessor system, and its number of ports and capacities are significantly increasing with every product generation. However, with technology advancements, multi-port memories are facing severe challenges due to their bit-cell leakage and scalability, as well as reliability issues due to increase in design complexity. In this paper, we design a novel multi-port memory architecture in which we employ emerging Spin Orbit Torque (SOT) magnetic devices as a storing component because of its several beneficial attributes such as non-volatility, scalability, zero-leakage, almost infinite endurance, low access latency, low area and immunity to soft-errors. Moreover, due to separate read and write current paths in these devices, simultaneous read and write operations can be performed on the same cell while maintaining data integrity. In our proposed architecture, we have demonstrated that with this characteristic of SOT, the read-write contention can be resolved inherently at the device-level, which can simplify the overall multi-port design. Experimental results show that our proposed multi-port design has low access latency, and high energy efficiency with negligible area overhead.
{"title":"Low-power multi-port memory architecture based on Spin Orbit Torque magnetic devices","authors":"R. Bishnoi, Fabian Oboril, M. Tahoori","doi":"10.1145/2902961.2903022","DOIUrl":"https://doi.org/10.1145/2902961.2903022","url":null,"abstract":"Multi-port memories are widely used as shared memory, such as register files, in a microprocessor system, and its number of ports and capacities are significantly increasing with every product generation. However, with technology advancements, multi-port memories are facing severe challenges due to their bit-cell leakage and scalability, as well as reliability issues due to increase in design complexity. In this paper, we design a novel multi-port memory architecture in which we employ emerging Spin Orbit Torque (SOT) magnetic devices as a storing component because of its several beneficial attributes such as non-volatility, scalability, zero-leakage, almost infinite endurance, low access latency, low area and immunity to soft-errors. Moreover, due to separate read and write current paths in these devices, simultaneous read and write operations can be performed on the same cell while maintaining data integrity. In our proposed architecture, we have demonstrated that with this characteristic of SOT, the read-write contention can be resolved inherently at the device-level, which can simplify the overall multi-port design. Experimental results show that our proposed multi-port design has low access latency, and high energy efficiency with negligible area overhead.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123385418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to size, longevity, safety, and recharging concerns, energy harvesting is becoming a better choice for many wearable embedded systems than batteries. However, harvested energy is intrinsically unstable. In order to overcome this drawback, non-volatile processors (NVPs) have been proposed to bridge intermittent program execution. However, even with NVPs, frequent power interruptions will severely degrade system performance. Hence, in this paper we adopt a multi-source in-door energy harvesting architecture to compensate the shortcoming of single energy source. We further investigate power harvesting prediction techniques, which are critical for NVP systems since they can coordinate with task scheduler in the NVP system to compensate the intermittent ambient energy harvesting. We investigate prediction methods both for single energy harvesting source and for multiple energy harvesting sources, the total output power of which is more stable compared with the single source case. A comprehensive evaluation framework has been developed using actually measured harvesting traces on the proposed neural network-based power harvesting prediction methods. It turns out that the most favorable prediction methods are directly predicting the total output power of DC-DC converters (connecting between energy sources and NVP), or predicting the total input power of DC-DC converters first and then inferring the total output power using a learned mapping function, for multi-source power harvesting predictions.
{"title":"Neural network-based prediction algorithms for in-door multi-source energy harvesting system for non-volatile processors","authors":"Ning Liu, Caiwen Ding, Yanzhi Wang, J. Hu","doi":"10.1145/2902961.2903037","DOIUrl":"https://doi.org/10.1145/2902961.2903037","url":null,"abstract":"Due to size, longevity, safety, and recharging concerns, energy harvesting is becoming a better choice for many wearable embedded systems than batteries. However, harvested energy is intrinsically unstable. In order to overcome this drawback, non-volatile processors (NVPs) have been proposed to bridge intermittent program execution. However, even with NVPs, frequent power interruptions will severely degrade system performance. Hence, in this paper we adopt a multi-source in-door energy harvesting architecture to compensate the shortcoming of single energy source. We further investigate power harvesting prediction techniques, which are critical for NVP systems since they can coordinate with task scheduler in the NVP system to compensate the intermittent ambient energy harvesting. We investigate prediction methods both for single energy harvesting source and for multiple energy harvesting sources, the total output power of which is more stable compared with the single source case. A comprehensive evaluation framework has been developed using actually measured harvesting traces on the proposed neural network-based power harvesting prediction methods. It turns out that the most favorable prediction methods are directly predicting the total output power of DC-DC converters (connecting between energy sources and NVP), or predicting the total input power of DC-DC converters first and then inferring the total output power using a learned mapping function, for multi-source power harvesting predictions.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121606134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To meet energy and quality of service (QoS) constraints in consumer/user-based embedded devices (CEDs), configurable caches can be tuned to a best configuration that consumes the least amount of energy while adhering to QoS expectations. However, due to disparate consumer QoS expectations and a myriad of unknown, third-party CED applications, tuning caches in CEDs is very challenging. In this paper, we propose a quality of service-aware, scalable tuning algorithm for configurable caches, which requires no a priori knowledge of applications or design-time efforts.
{"title":"Quality of service-aware, scalable cache tuning algorithm in consumer-based embedded devices","authors":"Mohamad Hammam Alsafrjalani, A. Gordon-Ross","doi":"10.1145/2902961.2902987","DOIUrl":"https://doi.org/10.1145/2902961.2902987","url":null,"abstract":"To meet energy and quality of service (QoS) constraints in consumer/user-based embedded devices (CEDs), configurable caches can be tuned to a best configuration that consumes the least amount of energy while adhering to QoS expectations. However, due to disparate consumer QoS expectations and a myriad of unknown, third-party CED applications, tuning caches in CEDs is very challenging. In this paper, we propose a quality of service-aware, scalable tuning algorithm for configurable caches, which requires no a priori knowledge of applications or design-time efforts.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124978514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to perform the required store and restore functions. Among various types of NVMs, memristors (a.k.a. RRAM) have several advantages including their small device size, low voltage operation, high speed, and CMOS-compatible fabrication process. In this article, we propose a new 8T1R RRAM-based non-volatile SRAM (NV-SRAM) which adds non-volatility to the SRAM with minimum impact on the Write and Read operations. Simulation at cell-level and array-level have confirmed that the new design performs Read and Write operations at a compatible delay, energy and noise margin as the conventional 6T SRAM, and it is among the best of all reported RRAM-based NV-SRAM designs to our knowledge. In addition, since our 8T1R design uses only one RRAM device per cell, the energy required for storing/restoring the SRAM data to/from the RRAM is significantly reduced by 60%/70% compared to the lowest storing/restoring energy of the previously proposed RRAM-based NV-SRAM designs.
{"title":"8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design","authors":"A. Abdelwahed, A. Neale, M. Anis, Lan Wei","doi":"10.1145/2902961.2903016","DOIUrl":"https://doi.org/10.1145/2902961.2903016","url":null,"abstract":"With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to perform the required store and restore functions. Among various types of NVMs, memristors (a.k.a. RRAM) have several advantages including their small device size, low voltage operation, high speed, and CMOS-compatible fabrication process. In this article, we propose a new 8T1R RRAM-based non-volatile SRAM (NV-SRAM) which adds non-volatility to the SRAM with minimum impact on the Write and Read operations. Simulation at cell-level and array-level have confirmed that the new design performs Read and Write operations at a compatible delay, energy and noise margin as the conventional 6T SRAM, and it is among the best of all reported RRAM-based NV-SRAM designs to our knowledge. In addition, since our 8T1R design uses only one RRAM device per cell, the energy required for storing/restoring the SRAM data to/from the RRAM is significantly reduced by 60%/70% compared to the lowest storing/restoring energy of the previously proposed RRAM-based NV-SRAM designs.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131617362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, H. Homayoun, I. Savidis
A dynamic power management system for homogeneous chip multi-processors (CMP) is proposed. Each core of the CMP includes on chip DC-DC switching buck converters that are interconnected through a switch network. The peak current rating of the buck converter is selected to meet only the average current demand of the load circuit. A real-time load balancing algorithm is developed which reconfigures the power delivery network by combining the output of multiple buck converters when the workload demand exceeds the peak current rating. Simulation results for the proposed power delivery method indicate up to a 44% reduction in the energy consumption of the CMP system. In addition, the on-chip footprint of the power delivery network, including the on-chip voltage regulators and the switching network, is reduced by at least 23%.
{"title":"Load balanced on-chip power delivery for average current demand","authors":"Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, H. Homayoun, I. Savidis","doi":"10.1145/2902961.2903030","DOIUrl":"https://doi.org/10.1145/2902961.2903030","url":null,"abstract":"A dynamic power management system for homogeneous chip multi-processors (CMP) is proposed. Each core of the CMP includes on chip DC-DC switching buck converters that are interconnected through a switch network. The peak current rating of the buck converter is selected to meet only the average current demand of the load circuit. A real-time load balancing algorithm is developed which reconfigures the power delivery network by combining the output of multiple buck converters when the workload demand exceeds the peak current rating. Simulation results for the proposed power delivery method indicate up to a 44% reduction in the energy consumption of the CMP system. In addition, the on-chip footprint of the power delivery network, including the on-chip voltage regulators and the switching network, is reduced by at least 23%.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130583545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thao Le, J. Di, M. Tehranipoor, Domenic Forte, Lei Wang
The rapid growth of Internet-of-things and other electronic devices make a huge impact on how and where data travel. The confidential data (e.g., personal data, financial information) that travel through unreliable channels can be exposed to attackers. In hardware, the confidential data such as secret cipher keys are facing the same issue. This problem is even more serious when the IP is from a 3rd party and contains scan-chains. Thus, data flow tracking is important to analyze possible leakage channels in fighting against such hardware security threats. This paper introduces a method for tracking data flow and detecting potential hardware Trojans in gate-level soft IPs using assets and Structural Checking tool.
{"title":"Tracking data flow at gate-level through structural","authors":"Thao Le, J. Di, M. Tehranipoor, Domenic Forte, Lei Wang","doi":"10.1145/2902961.2903040","DOIUrl":"https://doi.org/10.1145/2902961.2903040","url":null,"abstract":"The rapid growth of Internet-of-things and other electronic devices make a huge impact on how and where data travel. The confidential data (e.g., personal data, financial information) that travel through unreliable channels can be exposed to attackers. In hardware, the confidential data such as secret cipher keys are facing the same issue. This problem is even more serious when the IP is from a 3rd party and contains scan-chains. Thus, data flow tracking is important to analyze possible leakage channels in fighting against such hardware security threats. This paper introduces a method for tracking data flow and detecting potential hardware Trojans in gate-level soft IPs using assets and Structural Checking tool.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Models of power sources are essential elements in the simulation of systems that generate, store and manage energy. In spite of the huge difference in power scale, they perform a common function: converting a primary environmental quantity into power. This paper proposes a unified model of a power source that is applicable to any power scale, and that can be derived solely from data contained in the specification or the datasheet of a device. The key feature of our model is the normalization of the energy generation characteristic of the power source by means of a reduction to a function expressing extracted power vs. the "scavenged" quantity. The proposed model proved to apply to two kinds of power sources, i.e., a wind turbine and a photovoltaic panel, and to provide a good level of accuracy and simulation performance w.r.t. widely adopted models.
{"title":"A unified model of power sources for the simulation of electrical energy systems","authors":"S. Vinco, Yukai Chen, E. Macii, M. Poncino","doi":"10.1145/2902961.2903024","DOIUrl":"https://doi.org/10.1145/2902961.2903024","url":null,"abstract":"Models of power sources are essential elements in the simulation of systems that generate, store and manage energy. In spite of the huge difference in power scale, they perform a common function: converting a primary environmental quantity into power. This paper proposes a unified model of a power source that is applicable to any power scale, and that can be derived solely from data contained in the specification or the datasheet of a device. The key feature of our model is the normalization of the energy generation characteristic of the power source by means of a reduction to a function expressing extracted power vs. the \"scavenged\" quantity. The proposed model proved to apply to two kinds of power sources, i.e., a wind turbine and a photovoltaic panel, and to provide a good level of accuracy and simulation performance w.r.t. widely adopted models.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133559647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Page, Nasrin Attaran, Colin Shea, H. Homayoun, T. Mohsenin
Wearable personal health monitoring systems can offer a cost effective solution for human healthcare. These systems must provide both highly accurate, secured and quick processing and delivery of vast amount of data. In addition, wearable biomedical devices are used in inpatient, outpatient, and at home e-Patient care that must constantly monitor the patient's biomedical and physiological signals 24/7. These biomedical applications require sampling and processing multiple streams of physiological signals with strict power and area footprint. The processing typically consists of feature extraction, data fusion, and classification stages that require a large number of digital signal processing and machine learning kernels. In response to these requirements, in this paper, a low-power, domain-specific manycore accelerator named Power Efficient Nano Clusters (PENC) is proposed to map and execute the kernels of these applications. Experimental results show that the manycore is able to reduce energy consumption by up to 80% and 14% for DSP and machine learning kernels, respectively, when optimally parallelized. The performance of the proposed PENC manycore when acting as a coprocessor to an Intel Atom processor is compared with existing commercial off-the-shelf embedded processing platforms including Intel Atom, Xilinx Artix-7 FPGA, and NVIDIA TK1 ARM-A15 with GPU SoC. The results show that the PENC manycore architecture reduces the energy by as much as 10X while outperforming all off-the-shelf embedded processing platforms across all studied machine learning classifiers.
{"title":"Low-power manycore accelerator for personalized biomedical applications","authors":"A. Page, Nasrin Attaran, Colin Shea, H. Homayoun, T. Mohsenin","doi":"10.1145/2902961.2902986","DOIUrl":"https://doi.org/10.1145/2902961.2902986","url":null,"abstract":"Wearable personal health monitoring systems can offer a cost effective solution for human healthcare. These systems must provide both highly accurate, secured and quick processing and delivery of vast amount of data. In addition, wearable biomedical devices are used in inpatient, outpatient, and at home e-Patient care that must constantly monitor the patient's biomedical and physiological signals 24/7. These biomedical applications require sampling and processing multiple streams of physiological signals with strict power and area footprint. The processing typically consists of feature extraction, data fusion, and classification stages that require a large number of digital signal processing and machine learning kernels. In response to these requirements, in this paper, a low-power, domain-specific manycore accelerator named Power Efficient Nano Clusters (PENC) is proposed to map and execute the kernels of these applications. Experimental results show that the manycore is able to reduce energy consumption by up to 80% and 14% for DSP and machine learning kernels, respectively, when optimally parallelized. The performance of the proposed PENC manycore when acting as a coprocessor to an Intel Atom processor is compared with existing commercial off-the-shelf embedded processing platforms including Intel Atom, Xilinx Artix-7 FPGA, and NVIDIA TK1 ARM-A15 with GPU SoC. The results show that the PENC manycore architecture reduces the energy by as much as 10X while outperforming all off-the-shelf embedded processing platforms across all studied machine learning classifiers.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134481994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pietro Mercati, Francesco Paterna, Andrea Bartolini, M. Imani, L. Benini, T. Simunic
Variability is the real big challenge for integrated circuits. Today, simulators help to estimate the effect of variability, but fail to capture real workload dynamics and user interactions, which are fundamental to mobile devices. This paper presents VarDroid, a low-overhead tool to emulate power and performance variability on real platforms, running on top of the Android operating system. VarDroid enables analyzing the effect of variability in power and performance while capturing the complex interactions characteristic of mobile workloads, thus relating to user's quality of experience. The paper presents use cases to show the utility of VarDroid to test applications, device and OS robustness under the effects of variability. Our results show that a variability-agnostic OS can incur in a performance penalty of up to 60% and a power penalty of up to 20%.
{"title":"VarDroid: Online variability emulation in Android/Linux platforms","authors":"Pietro Mercati, Francesco Paterna, Andrea Bartolini, M. Imani, L. Benini, T. Simunic","doi":"10.1145/2902961.2902971","DOIUrl":"https://doi.org/10.1145/2902961.2902971","url":null,"abstract":"Variability is the real big challenge for integrated circuits. Today, simulators help to estimate the effect of variability, but fail to capture real workload dynamics and user interactions, which are fundamental to mobile devices. This paper presents VarDroid, a low-overhead tool to emulate power and performance variability on real platforms, running on top of the Android operating system. VarDroid enables analyzing the effect of variability in power and performance while capturing the complex interactions characteristic of mobile workloads, thus relating to user's quality of experience. The paper presents use cases to show the utility of VarDroid to test applications, device and OS robustness under the effects of variability. Our results show that a variability-agnostic OS can incur in a performance penalty of up to 60% and a power penalty of up to 20%.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134029648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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