With ongoing chip miniaturization and voltage scaling, particle strike-induced soft errors present increasingly severe threat to the reliability of on-chip caches. In this paper, we present a technique to reduce the vulnerability of caches to soft-errors. Our technique uses data compression to reduce the number of vulnerable data bits in the cache and performs selective duplication of more critical data-bits to provide extra protection to them. Microarchitectural simulations have shown that our technique is effective in reducing cache vulnerability and outperforms another technique. For single and dual-core system configuration, the average reduction in cache vulnerability is 5.59× and 8.44×, respectively. Also, the implementation and performance overheads of our technique are minimal and it is useful for a broad range of workloads.
{"title":"Reducing soft-error vulnerability of caches using data compression","authors":"Sparsh Mittal, J. Vetter","doi":"10.1145/2902961.2902977","DOIUrl":"https://doi.org/10.1145/2902961.2902977","url":null,"abstract":"With ongoing chip miniaturization and voltage scaling, particle strike-induced soft errors present increasingly severe threat to the reliability of on-chip caches. In this paper, we present a technique to reduce the vulnerability of caches to soft-errors. Our technique uses data compression to reduce the number of vulnerable data bits in the cache and performs selective duplication of more critical data-bits to provide extra protection to them. Microarchitectural simulations have shown that our technique is effective in reducing cache vulnerability and outperforms another technique. For single and dual-core system configuration, the average reduction in cache vulnerability is 5.59× and 8.44×, respectively. Also, the implementation and performance overheads of our technique are minimal and it is useful for a broad range of workloads.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129367316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, two timing error masking flip-flops have been proposed, which are immune to metastability. The proposed flipflops exploit the concept of either delayed data or pulse based approach to detect timing errors. The timing violations are masked by passing direct data instead of master latch output to slave latch. Simulation results show that the proposed flip-flops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops [14]. The proposed flip-flops can be used in dynamic voltage and frequency scaling (DVFS) applications. A 16-bit adder is implemented to evaluate the functionality of the proposed flip-flops in DVFS frame work and the simulation results show that the adder using the proposed flipflop can reduce up to 48% power consumption or improve the performance up to 50% in typical process corners compared to conventional worst case design.
{"title":"A metastability immune timing error masking flip-flop for dynamic variation tolerance","authors":"Govinda Sannena, B. P. Das","doi":"10.1145/2902961.2902976","DOIUrl":"https://doi.org/10.1145/2902961.2902976","url":null,"abstract":"In this paper, two timing error masking flip-flops have been proposed, which are immune to metastability. The proposed flipflops exploit the concept of either delayed data or pulse based approach to detect timing errors. The timing violations are masked by passing direct data instead of master latch output to slave latch. Simulation results show that the proposed flip-flops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops [14]. The proposed flip-flops can be used in dynamic voltage and frequency scaling (DVFS) applications. A 16-bit adder is implemented to evaluate the functionality of the proposed flip-flops in DVFS frame work and the simulation results show that the adder using the proposed flipflop can reduce up to 48% power consumption or improve the performance up to 50% in typical process corners compared to conventional worst case design.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125142842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Just as the Internet of Things (IoT) stands to revolutionize the way we sense, analyze, and apply data in civilian life, defense systems are also working to enhance future mission capabilities with IoT logic and devices. Recently, Gen. James Cartwright, former vice chairman of the Joint Chiefs of Staff, stated: "The ability to move from number of men per machine to the number of machines per man is the ultimate objective here in a command and control construct." In defense systems, IoT stands to dramatically affect cost, data, and response time advantages through distributed sensing, analysis, and action. This summarizes a key need of the defense community as it relates to IoT: the creation of an organizational construct that allows effective man-machine partnering and action that conforms to the command and culture of the US military (see Figure 1).
{"title":"Defense systems and IoT: Security issues in an era of distributed command and control","authors":"Doug Palmer, Saverio Fazzari, S. Wartenberg","doi":"10.1145/2902961.2903038","DOIUrl":"https://doi.org/10.1145/2902961.2903038","url":null,"abstract":"Just as the Internet of Things (IoT) stands to revolutionize the way we sense, analyze, and apply data in civilian life, defense systems are also working to enhance future mission capabilities with IoT logic and devices. Recently, Gen. James Cartwright, former vice chairman of the Joint Chiefs of Staff, stated: \"The ability to move from number of men per machine to the number of machines per man is the ultimate objective here in a command and control construct.\" In defense systems, IoT stands to dramatically affect cost, data, and response time advantages through distributed sensing, analysis, and action. This summarizes a key need of the defense community as it relates to IoT: the creation of an organizational construct that allows effective man-machine partnering and action that conforms to the command and culture of the US military (see Figure 1).","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129672797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power/energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultra-low power and energy-harvested systems. Aggressive voltage scaling and in particular Near-Threshold Computing (NTC) is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior at near threshold region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than 3X.
{"title":"Temperature-aware dynamic voltage scaling for near-threshold computing","authors":"S. Kiamehr, Mojtaba Ebrahimi, M. Tahoori","doi":"10.1145/2902961.2902997","DOIUrl":"https://doi.org/10.1145/2902961.2902997","url":null,"abstract":"Power/energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultra-low power and energy-harvested systems. Aggressive voltage scaling and in particular Near-Threshold Computing (NTC) is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior at near threshold region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than 3X.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117317972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cryptographic systems are vulnerable to random errors and injected faults. Soft errors can inadvertently happen in critical cryptographic modules and attackers can inject faults into systems to retrieve the embedded secret. Different schemes have been developed to improve the security and reliability of cryptographic systems. As the new SHA-3 standard, Keccak algorithm will be widely used in various cryptographic applications, and its implementation should b protected against random errors and injected faults. In this paper, we devise different parity checking methods to protect the operations of Keccak. Results show that our scheme can be easily implemented and can effectively protect Keccak system against random errors and fault attacks.
{"title":"Concurrent error detection for reliable SHA-3 design","authors":"Pei Luo, Cheng Li, Yunsi Fei","doi":"10.1145/2902961.2902985","DOIUrl":"https://doi.org/10.1145/2902961.2902985","url":null,"abstract":"Cryptographic systems are vulnerable to random errors and injected faults. Soft errors can inadvertently happen in critical cryptographic modules and attackers can inject faults into systems to retrieve the embedded secret. Different schemes have been developed to improve the security and reliability of cryptographic systems. As the new SHA-3 standard, Keccak algorithm will be widely used in various cryptographic applications, and its implementation should b protected against random errors and injected faults. In this paper, we devise different parity checking methods to protect the operations of Keccak. Results show that our scheme can be easily implemented and can effectively protect Keccak system against random errors and fault attacks.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114083950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this era of Internet of Things (IoT), connectivity exists everywhere, among everything (including people) at all times. Therefore, security, trust, and privacy become crucial to the design and implementation of IoT devices [12]. However, it is challenging to build security into IoT devices because most of them are constrained by extremely limited resources such as the battery, memory, and computation power etc. Inspired by the concept of visual cryptography [4] that requires the least amount of computation and a recent work on pure hardware-based single-user authentication [6], we present a novel solution to the secret sharing and multi-user authentication problem. Our solution is built on the observation that non-volatile resistive memories display nice monotonic and additive properties during resistive state transitions. We demonstrate how to design a hardware dependent multi-user authentication protocol using resistive random access memory (RRAM)-based hardware and provide the necessary circuits for the application. Finally, we simulate the proposed circuit to understand the nature of the operation and practical problems that these designs encounter during operation.
{"title":"Secret sharing and multi-user authentication: From visual cryptography to RRAM circuits","authors":"Md Tanvir Arafin, G. Qu","doi":"10.1145/2902961.2903039","DOIUrl":"https://doi.org/10.1145/2902961.2903039","url":null,"abstract":"In this era of Internet of Things (IoT), connectivity exists everywhere, among everything (including people) at all times. Therefore, security, trust, and privacy become crucial to the design and implementation of IoT devices [12]. However, it is challenging to build security into IoT devices because most of them are constrained by extremely limited resources such as the battery, memory, and computation power etc. Inspired by the concept of visual cryptography [4] that requires the least amount of computation and a recent work on pure hardware-based single-user authentication [6], we present a novel solution to the secret sharing and multi-user authentication problem. Our solution is built on the observation that non-volatile resistive memories display nice monotonic and additive properties during resistive state transitions. We demonstrate how to design a hardware dependent multi-user authentication protocol using resistive random access memory (RRAM)-based hardware and provide the necessary circuits for the application. Finally, we simulate the proposed circuit to understand the nature of the operation and practical problems that these designs encounter during operation.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"90 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122103315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The network delay upper-bound analysis problem is of fundamental importance to real-time applications in Network-on-Chip (NoC). In the paper, we revisit a state-of-the-art analysis model for real-time communication in wormhole NoC with priority-based preemptive arbitration and show that the model may provide pessimistic or even incorrect network delay upper-bound. We then propose a revised analysis model to correct the flaws in the previous model by further classifying indirect interference as upstream and downstream indirect interferences according to the relative positions of traffic flows and taking buffer influence into consideration. Simulated evaluations show that our model provides tighter and correct network delay upper-bound compared with the state-of-the-art model.
{"title":"Real-time analysis for wormhole NoC: Revisited and revised","authors":"Qin Xiong, Zhonghai Lu, Fei Wu, C. Xie","doi":"10.1145/2902961.2903023","DOIUrl":"https://doi.org/10.1145/2902961.2903023","url":null,"abstract":"The network delay upper-bound analysis problem is of fundamental importance to real-time applications in Network-on-Chip (NoC). In the paper, we revisit a state-of-the-art analysis model for real-time communication in wormhole NoC with priority-based preemptive arbitration and show that the model may provide pessimistic or even incorrect network delay upper-bound. We then propose a revised analysis model to correct the flaws in the previous model by further classifying indirect interference as upstream and downstream indirect interferences according to the relative positions of traffic flows and taking buffer influence into consideration. Simulated evaluations show that our model provides tighter and correct network delay upper-bound compared with the state-of-the-art model.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129161280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a centralized approach for connection allocation for TDM-based NoCs by making use of dedicated hardware unit called NoCManager that employs trellis-based search algorithm enabling dynamic parallel multi-path, multislot allocation. Be different to the previous unrolled trellis search algorithm, in this paper the folded architecture is employed to achieve efficiency. In comparison with previous TDM connection allocation methods, the proposed design has the following advantages: (1) hardware supported low-latency, high-throughput allocation mechanism, (2) improved success rate due to parallel multi-path search and (3) efficient NoCManager architecture. Compared to centralized software solutions the proposed design demonstrates two orders of magnitude improvement in allocation speed and ten times higher success rate. It can provide up to several times higher allocation speed and up to 18% higher success rate against recently proposed distributed solution.
{"title":"Trellis-search based dynamic multi-path connection allocation for TDM-NoCs","authors":"Yong Chen, E. Matús, G. Fettweis","doi":"10.1145/2902961.2902968","DOIUrl":"https://doi.org/10.1145/2902961.2902968","url":null,"abstract":"This paper proposes a centralized approach for connection allocation for TDM-based NoCs by making use of dedicated hardware unit called NoCManager that employs trellis-based search algorithm enabling dynamic parallel multi-path, multislot allocation. Be different to the previous unrolled trellis search algorithm, in this paper the folded architecture is employed to achieve efficiency. In comparison with previous TDM connection allocation methods, the proposed design has the following advantages: (1) hardware supported low-latency, high-throughput allocation mechanism, (2) improved success rate due to parallel multi-path search and (3) efficient NoCManager architecture. Compared to centralized software solutions the proposed design demonstrates two orders of magnitude improvement in allocation speed and ten times higher success rate. It can provide up to several times higher allocation speed and up to 18% higher success rate against recently proposed distributed solution.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126680615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Inductive links have been proposed as an inter-tier interconnect solution for three-dimensional (3-D) integrated systems. Combined with signal multiplexing, inductive links achieve high communication bandwidth comparable to that of through silicon vias. However, being a wireless medium, electromagnetic coupling between the inductive link and nearby on-chip interconnects can cause voltage fluctuations affecting interconnect performance. Although the interference of interconnects on the operation of inductive links has been investigated, the inverse problem has yet to be explored. Consequently, this paper performs an investigation on the effect of electromagnetic coupling on different topologies of power delivery networks (PDNs) in the vicinity of on-chip inductors. Results indicate that the interdigitated PDN topology suffers from the induced noise due to the inductive links of the neighbouring tiers exhibiting a minimum aggregate noise of 131.3 mV. Alternatively, the paired topologies exhibit a superior noise behaviour, achieving a 39.4% and 35.4% decrease in noise level for paired type I and paired type II topologies, respectively, compared to the interdigitated topology.
{"title":"Inter-tier crosstalk noise on power delivery networks for 3-D ICs with inductively-coupled interconnects","authors":"I. Papistas, V. Pavlidis","doi":"10.1145/2902961.2903020","DOIUrl":"https://doi.org/10.1145/2902961.2903020","url":null,"abstract":"Inductive links have been proposed as an inter-tier interconnect solution for three-dimensional (3-D) integrated systems. Combined with signal multiplexing, inductive links achieve high communication bandwidth comparable to that of through silicon vias. However, being a wireless medium, electromagnetic coupling between the inductive link and nearby on-chip interconnects can cause voltage fluctuations affecting interconnect performance. Although the interference of interconnects on the operation of inductive links has been investigated, the inverse problem has yet to be explored. Consequently, this paper performs an investigation on the effect of electromagnetic coupling on different topologies of power delivery networks (PDNs) in the vicinity of on-chip inductors. Results indicate that the interdigitated PDN topology suffers from the induced noise due to the inductive links of the neighbouring tiers exhibiting a minimum aggregate noise of 131.3 mV. Alternatively, the paired topologies exhibit a superior noise behaviour, achieving a 39.4% and 35.4% decrease in noise level for paired type I and paired type II topologies, respectively, compared to the interdigitated topology.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128179738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Jassi, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann
In recent years, the semiconductor industry has been witnessing an increasing reuse of hardware IPs for System-on-Chip (SoC) designs and embedded computing systems on FPGA platforms with hard-core processors. The IP-reuse comes with an increasing complexity at the hardware-software (HW-SW) interface. The efforts required to access the HW through the increasingly complex HW-SW interface diminishes the potential IP-reuse productivity gain. In our work, we are proposing hierarchical drivers for accessing IP-subsystems and its generation for enabling easier SW application adaptation to HW-changes and faster design space exploration (DSE) on a targeted HW-accelerated SW libraries. At the lowest level, closest to the HW, is the hardware abstraction layer (HAL), these are the platform-specific register-access drivers. At the next layer are the drivers to access the registers and bit-fields of each IP component of the IP-library. Next are the IP-subsystems drivers. At the top-layer, closest to the SW, is the simple scheduler with SW interface library that provides access functions to the SW application. The drivers generator uses the HW knowledge of IPs and IP-subsystems encoded in IP-XACT for generating the drivers for both operating system (OS) and non-OS based applications. For the OS-based applications, user-space drivers are generated, as well as device tree source (DTS) and drivers mapping in the kernel-space. In a case study, we have validated our methodology while performing DSE for a video processing application targeted to an IP-library, both as non-OS and with OS on Xilinx Zynq-based FPGA.
{"title":"Hardware-accelerated software library drivers generation for IP-centric SoC designs","authors":"M. Jassi, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann","doi":"10.1145/2902961.2903026","DOIUrl":"https://doi.org/10.1145/2902961.2903026","url":null,"abstract":"In recent years, the semiconductor industry has been witnessing an increasing reuse of hardware IPs for System-on-Chip (SoC) designs and embedded computing systems on FPGA platforms with hard-core processors. The IP-reuse comes with an increasing complexity at the hardware-software (HW-SW) interface. The efforts required to access the HW through the increasingly complex HW-SW interface diminishes the potential IP-reuse productivity gain. In our work, we are proposing hierarchical drivers for accessing IP-subsystems and its generation for enabling easier SW application adaptation to HW-changes and faster design space exploration (DSE) on a targeted HW-accelerated SW libraries. At the lowest level, closest to the HW, is the hardware abstraction layer (HAL), these are the platform-specific register-access drivers. At the next layer are the drivers to access the registers and bit-fields of each IP component of the IP-library. Next are the IP-subsystems drivers. At the top-layer, closest to the SW, is the simple scheduler with SW interface library that provides access functions to the SW application. The drivers generator uses the HW knowledge of IPs and IP-subsystems encoded in IP-XACT for generating the drivers for both operating system (OS) and non-OS based applications. For the OS-based applications, user-space drivers are generated, as well as device tree source (DTS) and drivers mapping in the kernel-space. In a case study, we have validated our methodology while performing DSE for a video processing application targeted to an IP-library, both as non-OS and with OS on Xilinx Zynq-based FPGA.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131673878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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