Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075886
Nilanjan Pal, A. Fish, W. McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, R. Pilawa-Podgurski, P. Hanumolu
This paper presents a new hybrid boost converter architecture for improving the efficiency of LED drivers used in mobile applications. By cascading a low-switching frequency time-interleaved series-parallel SC-stage with an inductive boost converter, we facilitate the use of lower voltage rated switches, thus greatly reducing the switching losses. Charge-sharing losses of the SC stage are minimized by soft-charging flying capacitors with the inductor of the boost stage. Fabricated in 180nm BCD process, the prototype converter generates 30V output voltage from a Li-ion battery source and can provide a load current in the range of 0 to 100mA with an excellent peak power efficiency of 91.15% at 30mA. Compared to state-of-the-art designs, the proposed converter achieves a 3 % improvement in peak power efficiency.
{"title":"A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS","authors":"Nilanjan Pal, A. Fish, W. McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, R. Pilawa-Podgurski, P. Hanumolu","doi":"10.1109/CICC48029.2020.9075886","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075886","url":null,"abstract":"This paper presents a new hybrid boost converter architecture for improving the efficiency of LED drivers used in mobile applications. By cascading a low-switching frequency time-interleaved series-parallel SC-stage with an inductive boost converter, we facilitate the use of lower voltage rated switches, thus greatly reducing the switching losses. Charge-sharing losses of the SC stage are minimized by soft-charging flying capacitors with the inductor of the boost stage. Fabricated in 180nm BCD process, the prototype converter generates 30V output voltage from a Li-ion battery source and can provide a load current in the range of 0 to 100mA with an excellent peak power efficiency of 91.15% at 30mA. Compared to state-of-the-art designs, the proposed converter achieves a 3 % improvement in peak power efficiency.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075953
Xiaochen Tang, Wei Tang
ECG delineation is crucial to Arrhythmia classification and future wearable heart monitoring sensors. This paper presents a second-order ternary delta modulator for ECG delineation. The proposed prototype measures slope variation of the ECG signals to detect the upward/downward-turning points without measuring the instantaneous amplitude. Then fiducial points of the PQRST waves can be located. The interval/segment timing information can be extracted for future on-chip arrhythmia classification. The experiment results show that the system is robust to baseline wandering. The chip can achieve 3.2 mV/ms2 sensitivity with 3 ms timing error. The proposed circuit consumes 151 nW with 1 V supply at a sampling rate of 1 kS/s, and fabricated in 180 nm CMOS process with 0.25 mm2 area occupied. Fiducial points localizing algorithm is realized on a Spartan-6 FPGA.
{"title":"A 151nW Second-Order Ternary Delta Modulator for ECG Slope Variation Measurement with Baseline Wandering Resilience","authors":"Xiaochen Tang, Wei Tang","doi":"10.1109/CICC48029.2020.9075953","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075953","url":null,"abstract":"ECG delineation is crucial to Arrhythmia classification and future wearable heart monitoring sensors. This paper presents a second-order ternary delta modulator for ECG delineation. The proposed prototype measures slope variation of the ECG signals to detect the upward/downward-turning points without measuring the instantaneous amplitude. Then fiducial points of the PQRST waves can be located. The interval/segment timing information can be extracted for future on-chip arrhythmia classification. The experiment results show that the system is robust to baseline wandering. The chip can achieve 3.2 mV/ms2 sensitivity with 3 ms timing error. The proposed circuit consumes 151 nW with 1 V supply at a sampling rate of 1 kS/s, and fabricated in 180 nm CMOS process with 0.25 mm2 area occupied. Fiducial points localizing algorithm is realized on a Spartan-6 FPGA.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121666193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075927
Dongyi Liao, F. Dai
In this paper, a fractional- N reference sampling PLL (RSPLL) is presented. To mitigate the frac-N induced quantization error, a capacitor digital-to-analog converter (CDAC) based canceller has been implemented at the reference sampling phase detector (RSPD) output. The RSPD is programmed to provide a detection range of one VCO cycle which is enough to cover the quantization error in frac-N mode. The CDAC is also reused as the sampling capacitor for RSPD. Additionally, a second order cancellation scheme is implemented with only one capacitor array and two reference voltages to compensate for the nonlinearity from RSPD. The prototype chip was fabricated in a 45 nm partially-depleted silicon-on-insulator (PDSOI) CMOS process. Measurement showed an output frequency range covering 7.7~10.3GHz with an integrated jitter (10kHz-10MHz) of 190fs and an in-band fractional spur level of-56dBc at an offset frequency of 625kHz. The entire PLL consumes 5.2mW and achieves a FoM of -247.3dB.
{"title":"A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS","authors":"Dongyi Liao, F. Dai","doi":"10.1109/CICC48029.2020.9075927","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075927","url":null,"abstract":"In this paper, a fractional- N reference sampling PLL (RSPLL) is presented. To mitigate the frac-N induced quantization error, a capacitor digital-to-analog converter (CDAC) based canceller has been implemented at the reference sampling phase detector (RSPD) output. The RSPD is programmed to provide a detection range of one VCO cycle which is enough to cover the quantization error in frac-N mode. The CDAC is also reused as the sampling capacitor for RSPD. Additionally, a second order cancellation scheme is implemented with only one capacitor array and two reference voltages to compensate for the nonlinearity from RSPD. The prototype chip was fabricated in a 45 nm partially-depleted silicon-on-insulator (PDSOI) CMOS process. Measurement showed an output frequency range covering 7.7~10.3GHz with an integrated jitter (10kHz-10MHz) of 190fs and an in-band fractional spur level of-56dBc at an offset frequency of 625kHz. The entire PLL consumes 5.2mW and achieves a FoM of -247.3dB.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125972052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075951
Jinyong Kim, Hyunkyu Ouh, M. Johnston
This paper presents a fully-integrated biopotential readout system using frequency division multiplexing (FDM) for general purpose, multi-channel biopotential signal acquisition. FDM reduces the number of required cables between active electrode and back-end readout, and frequency translation prior to transmission mitigates low-frequency motion artifacts and mains interference in the cable. The 4-channel EMG/ECG architecture carries all channels over a 3-wire interface and attenuates low-frequency cable motion artifacts by 15X and 60 Hz mains noise coupled into the cable by 62X. The IC is fabricated in 180 nm CMOS, including both front-end active electrode and back-end demodulation architectures; each 1 Hz-150 Hz, differential active electrode channel occupies 0.75 mm2 and consumes 43.8 $mu mathrm{W}$.
{"title":"A $43.8mu mathrm{W}$ per Channel Biopotential Readout System using Frequency Division Multiplexing with Cable Motion Artifact Suppression","authors":"Jinyong Kim, Hyunkyu Ouh, M. Johnston","doi":"10.1109/CICC48029.2020.9075951","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075951","url":null,"abstract":"This paper presents a fully-integrated biopotential readout system using frequency division multiplexing (FDM) for general purpose, multi-channel biopotential signal acquisition. FDM reduces the number of required cables between active electrode and back-end readout, and frequency translation prior to transmission mitigates low-frequency motion artifacts and mains interference in the cable. The 4-channel EMG/ECG architecture carries all channels over a 3-wire interface and attenuates low-frequency cable motion artifacts by 15X and 60 Hz mains noise coupled into the cable by 62X. The IC is fabricated in 180 nm CMOS, including both front-end active electrode and back-end demodulation architectures; each 1 Hz-150 Hz, differential active electrode channel occupies 0.75 mm2 and consumes 43.8 $mu mathrm{W}$.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132638430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075930
Shovan Maity, Nirmoy Modak, David Yang, Shitij Avlani, Mayukh Nath, Josef Danial, D. Das, Parikha Mehrotra, Shreyas Sen
Applications such as secure authentication, remote health monitoring require secure, low power communication between devices around the body. Radio wave communication protocols, such as Bluetooth, suffer from the problem of signal leakage and high power requirement. Electro QuasiStatic Human Body Communication (EQS-UBC) is the ideal alternative as it confines the signal within the body and also operates at order of magnitude lower power. In this paper, we design a secure HBC SoC node, which uses EQS-UBC for physical security and an AES-256 core for mathematical security. The SoC consumes 415nW power with an active power of 108nW for a data rate of 1kbps, sufficient for authentication and remote monitoring applications. This translates to 100x improvement in power consumption compared to state-of-the-art HBC implementations while providing physical security for the first time.
{"title":"A 415 nW Physically and Mathematically Secure Electro-Quasistatic HBC Node in 65nm CMOS for Authentication and Medical Applications","authors":"Shovan Maity, Nirmoy Modak, David Yang, Shitij Avlani, Mayukh Nath, Josef Danial, D. Das, Parikha Mehrotra, Shreyas Sen","doi":"10.1109/CICC48029.2020.9075930","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075930","url":null,"abstract":"Applications such as secure authentication, remote health monitoring require secure, low power communication between devices around the body. Radio wave communication protocols, such as Bluetooth, suffer from the problem of signal leakage and high power requirement. Electro QuasiStatic Human Body Communication (EQS-UBC) is the ideal alternative as it confines the signal within the body and also operates at order of magnitude lower power. In this paper, we design a secure HBC SoC node, which uses EQS-UBC for physical security and an AES-256 core for mathematical security. The SoC consumes 415nW power with an active power of 108nW for a data rate of 1kbps, sufficient for authentication and remote monitoring applications. This translates to 100x improvement in power consumption compared to state-of-the-art HBC implementations while providing physical security for the first time.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130812279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075937
Maik Kaufmann, A. Seidel, B. Wicht
With fast switching GaN any parasitic gate loop inductance degrades the switching performance and may lead to false turn-on as well as gate voltage overshoot. Two approaches to overcome these challenges in driving GaN transistors are discussed in this paper. In a discrete silicon based driver, the gate loop inductance is actively utilized for a resonant gate drive approach. In a second implementation, the gate loop inductance is reduced close to zero by GaN-on-Si monolithic integration of the power transistor and the driver on one die. It includes an integrated supply voltage regulator circuit that generates the gate drive voltage out of the high-voltage switching node. The results show fast and robust switching behavior with minimal ringing.
{"title":"Long, Short, Monolithic - The Gate Loop Challenge for GaN Drivers: Invited Paper","authors":"Maik Kaufmann, A. Seidel, B. Wicht","doi":"10.1109/CICC48029.2020.9075937","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075937","url":null,"abstract":"With fast switching GaN any parasitic gate loop inductance degrades the switching performance and may lead to false turn-on as well as gate voltage overshoot. Two approaches to overcome these challenges in driving GaN transistors are discussed in this paper. In a discrete silicon based driver, the gate loop inductance is actively utilized for a resonant gate drive approach. In a second implementation, the gate loop inductance is reduced close to zero by GaN-on-Si monolithic integration of the power transistor and the driver on one die. It includes an integrated supply voltage regulator circuit that generates the gate drive voltage out of the high-voltage switching node. The results show fast and robust switching behavior with minimal ringing.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075920
A. Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, K. Gharibdoust, A. Gupta, A. Hassanin, Klaas L. Hofstra, Brian Holden, A. Hormati, J. Keay, A. Shokrollahi, David Stauffer, Richard Simpson, A. Stewart, G. Surace, O. Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
Correlated Non-Return-to-Zero (CNRZ) signaling exhibits better pin-efficiency compared to the conventional binary differential NRZ signaling, while it does not compromise the sensitivity to Inter-Symbol Interference (ISI). This article analyzes performance of CNRZ transceivers, and provides experimental data for an Ultra-Short Reach (USR) link at 20.83 Gb/s/wire, implemented in FinFET 16 nm technology, consuming 1.02 pJ/b, As CNRZ is based on an orthogonal transformation, both encoding and decoding can be performed in analog, without any cost in terms of latency.
{"title":"Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ","authors":"A. Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, K. Gharibdoust, A. Gupta, A. Hassanin, Klaas L. Hofstra, Brian Holden, A. Hormati, J. Keay, A. Shokrollahi, David Stauffer, Richard Simpson, A. Stewart, G. Surace, O. Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh","doi":"10.1109/CICC48029.2020.9075920","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075920","url":null,"abstract":"Correlated Non-Return-to-Zero (CNRZ) signaling exhibits better pin-efficiency compared to the conventional binary differential NRZ signaling, while it does not compromise the sensitivity to Inter-Symbol Interference (ISI). This article analyzes performance of CNRZ transceivers, and provides experimental data for an Ultra-Short Reach (USR) link at 20.83 Gb/s/wire, implemented in FinFET 16 nm technology, consuming 1.02 pJ/b, As CNRZ is based on an orthogonal transformation, both encoding and decoding can be performed in analog, without any cost in terms of latency.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122750645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075881
I. Costanzo, Devdip Sen, U. Guler
This paper presents an integrated readout dedicated to sensing transcutaneous oxygen, a first of its kind. The readout circuit employs a fluorescence-based method to sense the oxygen molecules diffusing through the skin. The system uses a platinum porphyrin thin film, a blue light-emitting diode (LED) that excites the thin film, and a photodiode (PD) that captures the red light emitted from the thin film. The presence of oxygen quenches the intensity and the lifetime of red light. The readout integrated circuit (IC), which is integrated in a 0.18 µm 5 V CMOS process, excites the thin film and senses the current flowing through the PD. The analog front-end converts the detected current to a voltage while providing a variable gain of $59 mathrm{k}Omega-0.94 mathrm{M}Omega$. The LED driver circuit generates current as high as 40 mA. To decrease the power consumption of the readout, the LED can be pulsed at 16 $umathrm{s}$ intervals (based on the $1.7 mathrm{k}Omega$ input impedance of the transimpedance amplifier and 20 pF PD capacitance). The readout IC consumes 631 $mu mathrm{W}$ power and occupies 1.04 mm2. This paper also shows ex vivo measurements.
{"title":"An Integrated Readout Circuit for a Transcutaneous Oxygen Sensing Wearable Device","authors":"I. Costanzo, Devdip Sen, U. Guler","doi":"10.1109/CICC48029.2020.9075881","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075881","url":null,"abstract":"This paper presents an integrated readout dedicated to sensing transcutaneous oxygen, a first of its kind. The readout circuit employs a fluorescence-based method to sense the oxygen molecules diffusing through the skin. The system uses a platinum porphyrin thin film, a blue light-emitting diode (LED) that excites the thin film, and a photodiode (PD) that captures the red light emitted from the thin film. The presence of oxygen quenches the intensity and the lifetime of red light. The readout integrated circuit (IC), which is integrated in a 0.18 µm 5 V CMOS process, excites the thin film and senses the current flowing through the PD. The analog front-end converts the detected current to a voltage while providing a variable gain of $59 mathrm{k}Omega-0.94 mathrm{M}Omega$. The LED driver circuit generates current as high as 40 mA. To decrease the power consumption of the readout, the LED can be pulsed at 16 $umathrm{s}$ intervals (based on the $1.7 mathrm{k}Omega$ input impedance of the transimpedance amplifier and 20 pF PD capacitance). The readout IC consumes 631 $mu mathrm{W}$ power and occupies 1.04 mm2. This paper also shows ex vivo measurements.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126214638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075926
Xu Yang, Haixiao Cao, W. Qu
A fast response active ramping voltage mode control scheme for a Buck converter design is presented. The scheme employs a zero assisted active ramp to accelerate the response of voltage mode control. The design presents an intuitive design guideline for optimal transient responses and the measurement shows superior performances. Fabricated in a 0.8 um BCD process, the prototype converts an input from 10 V and 60 V to an output of 5 V with 600 mA load capacity and 1 MHz switching frequency. Measurements show an under-/overshoot voltage of -12.7 mV and 9.3 mV, respectively, for load transition between 100 mA and 500 mA. The line transient is 5.2 mV and - 3.8 mV, respectively, for input between 12 V and 15 V. The measured voltage scaling speed is 0.15 V/μs with 4.7 μF (x 3) output capacitors and the peak efficiency is 92.6%.
{"title":"A 9.3mV Load and 5.2mV Line transients Fast Response Buck Converter with Active Ramping Voltage Mode Control","authors":"Xu Yang, Haixiao Cao, W. Qu","doi":"10.1109/CICC48029.2020.9075926","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075926","url":null,"abstract":"A fast response active ramping voltage mode control scheme for a Buck converter design is presented. The scheme employs a zero assisted active ramp to accelerate the response of voltage mode control. The design presents an intuitive design guideline for optimal transient responses and the measurement shows superior performances. Fabricated in a 0.8 um BCD process, the prototype converts an input from 10 V and 60 V to an output of 5 V with 600 mA load capacity and 1 MHz switching frequency. Measurements show an under-/overshoot voltage of -12.7 mV and 9.3 mV, respectively, for load transition between 100 mA and 500 mA. The line transient is 5.2 mV and - 3.8 mV, respectively, for input between 12 V and 15 V. The measured voltage scaling speed is 0.15 V/μs with 4.7 μF (x 3) output capacitors and the peak efficiency is 92.6%.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114761486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075935
Hamed Rahmani, A. Babakhani
This paper presents an integrated wirelessly powered radio with two on-chip antennas and a total volume of 2.4×2.2×0.3 mm3 achieving ×7 smaller footprint than state-of-the-art wirelessly powered transceivers. The system is fabricated in TSMC 180nm process and is designed to operate under stringent power budgets of medical implants. Power and downlink data are carried to the system via an AKS-modulated RF link with an energy efficiency of 1 pJ/b. This design can operate under various power budgets and utilizes a power management technique to adjust the effective data rate and power consumption. TX block is based on a power oscillator structure and utilizes an on-chip dipole antenna at the load. Reconfigurable TX block can transmit uplink data with OOK and UWB modulation schemes and supports a maximum data rate of 150 Mbps achieving an energy efficiency of 4.65 pJ/b at a 15cm distance. In UWB modes, the TX block operates continuously for data rates of up to 40 Mbps.
{"title":"A 1.6mm3 Wirelessly Powered Reconfigurable FDD Radio with On-Chip Antennas Achieving 4.7 pJ/b TX and 1 pJ/b RX Energy Efficiencies for Medical Implants","authors":"Hamed Rahmani, A. Babakhani","doi":"10.1109/CICC48029.2020.9075935","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075935","url":null,"abstract":"This paper presents an integrated wirelessly powered radio with two on-chip antennas and a total volume of 2.4×2.2×0.3 mm3 achieving ×7 smaller footprint than state-of-the-art wirelessly powered transceivers. The system is fabricated in TSMC 180nm process and is designed to operate under stringent power budgets of medical implants. Power and downlink data are carried to the system via an AKS-modulated RF link with an energy efficiency of 1 pJ/b. This design can operate under various power budgets and utilizes a power management technique to adjust the effective data rate and power consumption. TX block is based on a power oscillator structure and utilizes an on-chip dipole antenna at the load. Reconfigurable TX block can transmit uplink data with OOK and UWB modulation schemes and supports a maximum data rate of 150 Mbps achieving an energy efficiency of 4.65 pJ/b at a 15cm distance. In UWB modes, the TX block operates continuously for data rates of up to 40 Mbps.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121879692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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