Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075908
M. Fattori, C. D. Costa, Joost A. Fijn, E. Genco, P. Harpe, E. Cantatore, M. Charbonneau
This paper presents a printed smart temperature sensor on RFID manufactured with organic materials. The system-on-foil exploits printed resistors and a time-based printed OTFT interface to convert temperature to a PWM representation and enable wireless RF communication at 13.56 MHz. The system is also equipped with a dedicated harvesting circuit for wireless power transfer, allowing stand-alone operation. The smart sensor achieves 0.27 KRMS resolution for a 2 $s$ conversion time, a resolution FOM of 294 10-6·J· K2 and a 3 sigma inaccuracy of ±1.2° C over the food monitoring temperature range 3° C to 27° C, after systematic non linearity removal and 3-point calibration. These results demonstrate that inexpensive electronic devices suitable for fresh food monitoring applications can be developed with unipolar printed organic transistor technologies, allowing e.g. integration of smart sensors in food packaging material.
{"title":"A Fully-Printed Organic Smart Temperature Sensor for Cold Chain Monitoring Applications","authors":"M. Fattori, C. D. Costa, Joost A. Fijn, E. Genco, P. Harpe, E. Cantatore, M. Charbonneau","doi":"10.1109/CICC48029.2020.9075908","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075908","url":null,"abstract":"This paper presents a printed smart temperature sensor on RFID manufactured with organic materials. The system-on-foil exploits printed resistors and a time-based printed OTFT interface to convert temperature to a PWM representation and enable wireless RF communication at 13.56 MHz. The system is also equipped with a dedicated harvesting circuit for wireless power transfer, allowing stand-alone operation. The smart sensor achieves 0.27 KRMS resolution for a 2 $s$ conversion time, a resolution FOM of 294 10-6·J· K2 and a 3 sigma inaccuracy of ±1.2° C over the food monitoring temperature range 3° C to 27° C, after systematic non linearity removal and 3-point calibration. These results demonstrate that inexpensive electronic devices suitable for fresh food monitoring applications can be developed with unipolar printed organic transistor technologies, allowing e.g. integration of smart sensors in food packaging material.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125622915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075935
Hamed Rahmani, A. Babakhani
This paper presents an integrated wirelessly powered radio with two on-chip antennas and a total volume of 2.4×2.2×0.3 mm3 achieving ×7 smaller footprint than state-of-the-art wirelessly powered transceivers. The system is fabricated in TSMC 180nm process and is designed to operate under stringent power budgets of medical implants. Power and downlink data are carried to the system via an AKS-modulated RF link with an energy efficiency of 1 pJ/b. This design can operate under various power budgets and utilizes a power management technique to adjust the effective data rate and power consumption. TX block is based on a power oscillator structure and utilizes an on-chip dipole antenna at the load. Reconfigurable TX block can transmit uplink data with OOK and UWB modulation schemes and supports a maximum data rate of 150 Mbps achieving an energy efficiency of 4.65 pJ/b at a 15cm distance. In UWB modes, the TX block operates continuously for data rates of up to 40 Mbps.
{"title":"A 1.6mm3 Wirelessly Powered Reconfigurable FDD Radio with On-Chip Antennas Achieving 4.7 pJ/b TX and 1 pJ/b RX Energy Efficiencies for Medical Implants","authors":"Hamed Rahmani, A. Babakhani","doi":"10.1109/CICC48029.2020.9075935","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075935","url":null,"abstract":"This paper presents an integrated wirelessly powered radio with two on-chip antennas and a total volume of 2.4×2.2×0.3 mm3 achieving ×7 smaller footprint than state-of-the-art wirelessly powered transceivers. The system is fabricated in TSMC 180nm process and is designed to operate under stringent power budgets of medical implants. Power and downlink data are carried to the system via an AKS-modulated RF link with an energy efficiency of 1 pJ/b. This design can operate under various power budgets and utilizes a power management technique to adjust the effective data rate and power consumption. TX block is based on a power oscillator structure and utilizes an on-chip dipole antenna at the load. Reconfigurable TX block can transmit uplink data with OOK and UWB modulation schemes and supports a maximum data rate of 150 Mbps achieving an energy efficiency of 4.65 pJ/b at a 15cm distance. In UWB modes, the TX block operates continuously for data rates of up to 40 Mbps.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121879692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075872
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim
Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64% compared to previous precision-scalable accelerators.
{"title":"A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS","authors":"Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim","doi":"10.1109/CICC48029.2020.9075872","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075872","url":null,"abstract":"Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64% compared to previous precision-scalable accelerators.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"49 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134363059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075929
Sein Oh, Younggyun Oh, Juyoung Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
A pipelined NS-SAR ADC with 1–2 MASH structure is presented. Two-stage pipelined structure consisting of 5-bit NS-SAR and 4-bit NS-SAR ADCs shows 3rd-order noise-shaping. To maximize power efficiency, a single operational transconductance amplifier (OTA) is reused for both an integrator for noise shaping and a residue amplifier for pipelining. The measured DR is 80dB when the sampling rate is 83.3MS/s and bandwidth is 6MHz, and power consumption is 3.5mW showing FoMs,DR of 172.3dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer, and can achieve high resolution and wide bandwidth with good power efficiency.
{"title":"A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1–2 MASH structure","authors":"Sein Oh, Younggyun Oh, Juyoung Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae","doi":"10.1109/CICC48029.2020.9075929","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075929","url":null,"abstract":"A pipelined NS-SAR ADC with 1–2 MASH structure is presented. Two-stage pipelined structure consisting of 5-bit NS-SAR and 4-bit NS-SAR ADCs shows 3rd-order noise-shaping. To maximize power efficiency, a single operational transconductance amplifier (OTA) is reused for both an integrator for noise shaping and a residue amplifier for pipelining. The measured DR is 80dB when the sampling rate is 83.3MS/s and bandwidth is 6MHz, and power consumption is 3.5mW showing FoMs,DR of 172.3dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer, and can achieve high resolution and wide bandwidth with good power efficiency.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129830354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075878
Alexander S. Delke, A. Annema, M. S. O. Alink, Yanyu Jin, Jos Verlinden, B. Nauta
A single-trim, high accuracy frequency reference is presented. The Colpitts LC-oscillator topology reduces the temperature dependencies of the LC-tank quality factor on the oscillation frequency. With a fractional divider for frequency compensation it can serve as crystal-replacement. Measurements of the prototype (16 samples) in a $0.13mu mathrm{m}$ high-voltage CMOS SOI process show $pm 120mathrm{ppm}$ accuracy from -50 to 170°C. The oscillator dissipates 3.5mW from a 2.5V supply and has 220ppm/V supply-sensitivity without supply regulation.
{"title":"A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C","authors":"Alexander S. Delke, A. Annema, M. S. O. Alink, Yanyu Jin, Jos Verlinden, B. Nauta","doi":"10.1109/CICC48029.2020.9075878","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075878","url":null,"abstract":"A single-trim, high accuracy frequency reference is presented. The Colpitts LC-oscillator topology reduces the temperature dependencies of the LC-tank quality factor on the oscillation frequency. With a fractional divider for frequency compensation it can serve as crystal-replacement. Measurements of the prototype (16 samples) in a $0.13mu mathrm{m}$ high-voltage CMOS SOI process show $pm 120mathrm{ppm}$ accuracy from -50 to 170°C. The oscillator dissipates 3.5mW from a 2.5V supply and has 220ppm/V supply-sensitivity without supply regulation.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132723474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075954
M. Croce, Brian W. Friend, F. Nesta, L. Crespi, P. Malcovati, A. Baschirotto
This paper presents a fully analog, signal-to-noise ratio (SNR) based voice-activity detection circuit, which achieves 99.5 % classification accuracy in a domestic environment in the presence of loud ambient noise, consuming 760 nW from a 1.2 V supply. The circuit exploits an energy-efficient analog implementation with continuous-time non-linear operation and fully-passive switched-capacitor processing, to minimize both the power consumption and the chip area. The VAD circuit prototype, fabricated in a 180 nm CMOS technology, occupies 0.14mm2.
{"title":"A 760 nW, 180 nm CMOS Analog Voice Activity Detection System","authors":"M. Croce, Brian W. Friend, F. Nesta, L. Crespi, P. Malcovati, A. Baschirotto","doi":"10.1109/CICC48029.2020.9075954","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075954","url":null,"abstract":"This paper presents a fully analog, signal-to-noise ratio (SNR) based voice-activity detection circuit, which achieves 99.5 % classification accuracy in a domestic environment in the presence of loud ambient noise, consuming 760 nW from a 1.2 V supply. The circuit exploits an energy-efficient analog implementation with continuous-time non-linear operation and fully-passive switched-capacitor processing, to minimize both the power consumption and the chip area. The VAD circuit prototype, fabricated in a 180 nm CMOS technology, occupies 0.14mm2.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129243520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075896
Amr Ahmed, Min-Yu Huang, Hua Wang
This work presents an ultra-wideband mixer-first front-end that can cover mmWave communications bands in the frequency range 43–97 GHz. The front-end employs a mmWave 90°coupler as an input stage in order to achieve wideband matching and RF quadrature signal generation. Passive mixer and multi-gated gm3-cancellation IF amplifiers used to achieve and maintain high linearity across the frequency range. In addition, the frond-end implements a current mode image rejection using a transformer based IF 90°coupler. The receiver front-end is implemented in CMOS 22nm FD-SOI technology and achieves an ultra-wideband S11 matching while employing up to 32 dB image rejection and 1.6-5.2 dBm in-band IIP3. In addition, the front-end supports up to 6 Gbps 64QAM modulated data.
{"title":"Mixer-First Extremely Wideband 43–97 GHz RX Frontend with Broadband Quadrature Input Matching and Current Mode Transformer-Based Image Rejection for Massive MIMO Applications","authors":"Amr Ahmed, Min-Yu Huang, Hua Wang","doi":"10.1109/CICC48029.2020.9075896","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075896","url":null,"abstract":"This work presents an ultra-wideband mixer-first front-end that can cover mmWave communications bands in the frequency range 43–97 GHz. The front-end employs a mmWave 90°coupler as an input stage in order to achieve wideband matching and RF quadrature signal generation. Passive mixer and multi-gated gm3-cancellation IF amplifiers used to achieve and maintain high linearity across the frequency range. In addition, the frond-end implements a current mode image rejection using a transformer based IF 90°coupler. The receiver front-end is implemented in CMOS 22nm FD-SOI technology and achieves an ultra-wideband S11 matching while employing up to 32 dB image rejection and 1.6-5.2 dBm in-band IIP3. In addition, the front-end supports up to 6 Gbps 64QAM modulated data.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"129 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075931
Minkyu Kim, Jae-sun Seo
This paper presents an ASIC accelerator for deep convolutional neural networks (DCNNs) featuring a novel conditional computing scheme that synergistically combines precision-cascading with zero-skipping. To reduce many redundant convolution operations that are followed by max-pooling operations, we propose precision-cascading, where the input features are divided into a number of low-precision groups and approximate convolutions with only the most significant bits (MSBs) are performed first. Based on this approximate computation, the full-precision convolution is performed only on the maximum pooling output that is found. This way, the total number of bit-wise convolutions can be reduced by ~2× without affecting the output feature values and with <0.8% degradation in final ImageNet classification accuracy. Precision-cascading provides the added benefit of increased sparsity per low-precision group, which we exploit with zero-skipping to eliminate clock cycles as well as external memory access that involve zero inputs. By jointly optimizing the conditional computing scheme and hardware architecture, the 40nm prototype chip demonstrates a peak energy-efficiency of 8.85 TOPS/W at 0.9V supply and low external memory access of 55.31 MB (or 0.0018 access/MAC) for ImageNet classification with VGG-16 CNN.
{"title":"Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access","authors":"Minkyu Kim, Jae-sun Seo","doi":"10.1109/CICC48029.2020.9075931","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075931","url":null,"abstract":"This paper presents an ASIC accelerator for deep convolutional neural networks (DCNNs) featuring a novel conditional computing scheme that synergistically combines precision-cascading with zero-skipping. To reduce many redundant convolution operations that are followed by max-pooling operations, we propose precision-cascading, where the input features are divided into a number of low-precision groups and approximate convolutions with only the most significant bits (MSBs) are performed first. Based on this approximate computation, the full-precision convolution is performed only on the maximum pooling output that is found. This way, the total number of bit-wise convolutions can be reduced by ~2× without affecting the output feature values and with <0.8% degradation in final ImageNet classification accuracy. Precision-cascading provides the added benefit of increased sparsity per low-precision group, which we exploit with zero-skipping to eliminate clock cycles as well as external memory access that involve zero inputs. By jointly optimizing the conditional computing scheme and hardware architecture, the 40nm prototype chip demonstrates a peak energy-efficiency of 8.85 TOPS/W at 0.9V supply and low external memory access of 55.31 MB (or 0.0018 access/MAC) for ImageNet classification with VGG-16 CNN.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075899
Sukjin Kim, R. Sithanandam, Woojin Seo, Mijin Lee, Sangyoung Cho, Juho Park, Hyuk-Mim Kwon, Namho Kim, Chanhee Jeon
Continuous optimization of power, performance and area lead to the evolution of planar CMOS to the FinFET technology. With further scaling, the use of EUV lithography for 7nm and below technologies became a necessity. Extensive literature is available for the optimizing the digital and analog performances using FinFET technologies. However, there is a dearth of literature in analyzing the ESD performance and scaling trends across various FinFET technologies. This paper is an attempt to present the design choices, challenges and solutions available for the robust ESD protection. ESD devices of the general purpose I/O's (N+/Psub, NW/Psub, P+/NW diodes) and failsafe I/O's (GGNMOS) are analyzed in 14nm, 10nm and 7nm FinFET technologies. For the first time, a brief note on the new charge based CDM analysis strategy which ensures first time silicon success is also explained. The test structure development, fabrication, testing and results are performed at Samsung Foundry.
{"title":"Technology Scaling of ESD Devices in State of the Art FinFET Technologies","authors":"Sukjin Kim, R. Sithanandam, Woojin Seo, Mijin Lee, Sangyoung Cho, Juho Park, Hyuk-Mim Kwon, Namho Kim, Chanhee Jeon","doi":"10.1109/CICC48029.2020.9075899","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075899","url":null,"abstract":"Continuous optimization of power, performance and area lead to the evolution of planar CMOS to the FinFET technology. With further scaling, the use of EUV lithography for 7nm and below technologies became a necessity. Extensive literature is available for the optimizing the digital and analog performances using FinFET technologies. However, there is a dearth of literature in analyzing the ESD performance and scaling trends across various FinFET technologies. This paper is an attempt to present the design choices, challenges and solutions available for the robust ESD protection. ESD devices of the general purpose I/O's (N+/Psub, NW/Psub, P+/NW diodes) and failsafe I/O's (GGNMOS) are analyzed in 14nm, 10nm and 7nm FinFET technologies. For the first time, a brief note on the new charge based CDM analysis strategy which ensures first time silicon success is also explained. The test structure development, fabrication, testing and results are performed at Samsung Foundry.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123998693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075909
A. H. M. Shirazi, M. Mahani, H. M. Lavasani, S. Mirabbasi, S. Shekhar, R. Zavari, H. Djahanshahi
A compact dual-core, single-transformer, and low-power voltage-controlled oscillator (VCO) is presented. The single transformer provides resonance at both differential and common modes, eliminating the need for an explicit inductor for the common-mode resonance. It is implemented vertically using two top metal layers, resulting in significant area saving compared to the state-of-the-art. The LC-tank has common mode resonance at twice the VCO frequency, hence reducing the flicker noise corner frequency of the VCO to 450 kHz. A fully-balanced complementary coupled-Class-C design improves efficiency, maintains symmetric swings across the transformer, and improves reliability. A prototype 26.1-to-29.9 GHz VCO, suitable for 5G applications, is implemented in a 65-nm CMOS process occupying an area of 0.04 mm2. The VCO consumes 3.4 mW at 27.45 GHz and exhibits a phase noise of -127.5 dBc/Hz at 10 MHz offset resulting in an FoM of -191 dB/Hz.
{"title":"A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz","authors":"A. H. M. Shirazi, M. Mahani, H. M. Lavasani, S. Mirabbasi, S. Shekhar, R. Zavari, H. Djahanshahi","doi":"10.1109/CICC48029.2020.9075909","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075909","url":null,"abstract":"A compact dual-core, single-transformer, and low-power voltage-controlled oscillator (VCO) is presented. The single transformer provides resonance at both differential and common modes, eliminating the need for an explicit inductor for the common-mode resonance. It is implemented vertically using two top metal layers, resulting in significant area saving compared to the state-of-the-art. The LC-tank has common mode resonance at twice the VCO frequency, hence reducing the flicker noise corner frequency of the VCO to 450 kHz. A fully-balanced complementary coupled-Class-C design improves efficiency, maintains symmetric swings across the transformer, and improves reliability. A prototype 26.1-to-29.9 GHz VCO, suitable for 5G applications, is implemented in a 65-nm CMOS process occupying an area of 0.04 mm2. The VCO consumes 3.4 mW at 27.45 GHz and exhibits a phase noise of -127.5 dBc/Hz at 10 MHz offset resulting in an FoM of -191 dB/Hz.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125999374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：