Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075902
Jan S. Rentmeister, J. Stauth
This paper presents a highly-integrated, 5-level flying capacitor multilevel (FCML) dc-dc converter that uses augmented ripple-injection control to achieve self-startup, fast transient response, and flying capacitor voltage balance. The converter provides 5.5 V:0.4 V-1.2 V step down with robust load- and line-rejection, peak efficiency of 92.4 % and >80 % efficiency at a 13.8:1 conversion ratio with peak current up to 1.4 A. All power devices, bootstrap capacitors, and control functions are integrated on chip; flying and bypass capacitors are die-attached using a custom assembly process.
{"title":"A 92.4% Efficient, 5.5V:0.4-1.2V, FCML Converter with Modified Ripple Injection Control for Fast Transient Response and Capacitor Balancing","authors":"Jan S. Rentmeister, J. Stauth","doi":"10.1109/CICC48029.2020.9075902","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075902","url":null,"abstract":"This paper presents a highly-integrated, 5-level flying capacitor multilevel (FCML) dc-dc converter that uses augmented ripple-injection control to achieve self-startup, fast transient response, and flying capacitor voltage balance. The converter provides 5.5 V:0.4 V-1.2 V step down with robust load- and line-rejection, peak efficiency of 92.4 % and >80 % efficiency at a 13.8:1 conversion ratio with peak current up to 1.4 A. All power devices, bootstrap capacitors, and control functions are integrated on chip; flying and bypass capacitors are die-attached using a custom assembly process.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123121037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075908
M. Fattori, C. D. Costa, Joost A. Fijn, E. Genco, P. Harpe, E. Cantatore, M. Charbonneau
This paper presents a printed smart temperature sensor on RFID manufactured with organic materials. The system-on-foil exploits printed resistors and a time-based printed OTFT interface to convert temperature to a PWM representation and enable wireless RF communication at 13.56 MHz. The system is also equipped with a dedicated harvesting circuit for wireless power transfer, allowing stand-alone operation. The smart sensor achieves 0.27 KRMS resolution for a 2 $s$ conversion time, a resolution FOM of 294 10-6·J· K2 and a 3 sigma inaccuracy of ±1.2° C over the food monitoring temperature range 3° C to 27° C, after systematic non linearity removal and 3-point calibration. These results demonstrate that inexpensive electronic devices suitable for fresh food monitoring applications can be developed with unipolar printed organic transistor technologies, allowing e.g. integration of smart sensors in food packaging material.
{"title":"A Fully-Printed Organic Smart Temperature Sensor for Cold Chain Monitoring Applications","authors":"M. Fattori, C. D. Costa, Joost A. Fijn, E. Genco, P. Harpe, E. Cantatore, M. Charbonneau","doi":"10.1109/CICC48029.2020.9075908","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075908","url":null,"abstract":"This paper presents a printed smart temperature sensor on RFID manufactured with organic materials. The system-on-foil exploits printed resistors and a time-based printed OTFT interface to convert temperature to a PWM representation and enable wireless RF communication at 13.56 MHz. The system is also equipped with a dedicated harvesting circuit for wireless power transfer, allowing stand-alone operation. The smart sensor achieves 0.27 KRMS resolution for a 2 $s$ conversion time, a resolution FOM of 294 10-6·J· K2 and a 3 sigma inaccuracy of ±1.2° C over the food monitoring temperature range 3° C to 27° C, after systematic non linearity removal and 3-point calibration. These results demonstrate that inexpensive electronic devices suitable for fresh food monitoring applications can be developed with unipolar printed organic transistor technologies, allowing e.g. integration of smart sensors in food packaging material.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125622915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075878
Alexander S. Delke, A. Annema, M. S. O. Alink, Yanyu Jin, Jos Verlinden, B. Nauta
A single-trim, high accuracy frequency reference is presented. The Colpitts LC-oscillator topology reduces the temperature dependencies of the LC-tank quality factor on the oscillation frequency. With a fractional divider for frequency compensation it can serve as crystal-replacement. Measurements of the prototype (16 samples) in a $0.13mu mathrm{m}$ high-voltage CMOS SOI process show $pm 120mathrm{ppm}$ accuracy from -50 to 170°C. The oscillator dissipates 3.5mW from a 2.5V supply and has 220ppm/V supply-sensitivity without supply regulation.
{"title":"A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C","authors":"Alexander S. Delke, A. Annema, M. S. O. Alink, Yanyu Jin, Jos Verlinden, B. Nauta","doi":"10.1109/CICC48029.2020.9075878","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075878","url":null,"abstract":"A single-trim, high accuracy frequency reference is presented. The Colpitts LC-oscillator topology reduces the temperature dependencies of the LC-tank quality factor on the oscillation frequency. With a fractional divider for frequency compensation it can serve as crystal-replacement. Measurements of the prototype (16 samples) in a $0.13mu mathrm{m}$ high-voltage CMOS SOI process show $pm 120mathrm{ppm}$ accuracy from -50 to 170°C. The oscillator dissipates 3.5mW from a 2.5V supply and has 220ppm/V supply-sensitivity without supply regulation.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132723474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075872
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim
Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64% compared to previous precision-scalable accelerators.
{"title":"A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS","authors":"Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim","doi":"10.1109/CICC48029.2020.9075872","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075872","url":null,"abstract":"Supporting variable precision for computing quantized neural network in a hardware accelerator is an efficient way to reduce overall computation time and energy. However, in the previous precision-scalable hardware, bit-reconfiguration logic increases the chip area significantly. In this paper, we demonstrate a compact precision-scalable accelerator chip using bitwise summation and channel-wise aligning schemes. The measurement results show that the peak performance per compute area is improved by 5.1-7.7x and system-level energy-efficiency is improved by up to 64% compared to previous precision-scalable accelerators.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"49 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134363059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075929
Sein Oh, Younggyun Oh, Juyoung Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
A pipelined NS-SAR ADC with 1–2 MASH structure is presented. Two-stage pipelined structure consisting of 5-bit NS-SAR and 4-bit NS-SAR ADCs shows 3rd-order noise-shaping. To maximize power efficiency, a single operational transconductance amplifier (OTA) is reused for both an integrator for noise shaping and a residue amplifier for pipelining. The measured DR is 80dB when the sampling rate is 83.3MS/s and bandwidth is 6MHz, and power consumption is 3.5mW showing FoMs,DR of 172.3dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer, and can achieve high resolution and wide bandwidth with good power efficiency.
{"title":"A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1–2 MASH structure","authors":"Sein Oh, Younggyun Oh, Juyoung Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae","doi":"10.1109/CICC48029.2020.9075929","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075929","url":null,"abstract":"A pipelined NS-SAR ADC with 1–2 MASH structure is presented. Two-stage pipelined structure consisting of 5-bit NS-SAR and 4-bit NS-SAR ADCs shows 3rd-order noise-shaping. To maximize power efficiency, a single operational transconductance amplifier (OTA) is reused for both an integrator for noise shaping and a residue amplifier for pipelining. The measured DR is 80dB when the sampling rate is 83.3MS/s and bandwidth is 6MHz, and power consumption is 3.5mW showing FoMs,DR of 172.3dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer, and can achieve high resolution and wide bandwidth with good power efficiency.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129830354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075909
A. H. M. Shirazi, M. Mahani, H. M. Lavasani, S. Mirabbasi, S. Shekhar, R. Zavari, H. Djahanshahi
A compact dual-core, single-transformer, and low-power voltage-controlled oscillator (VCO) is presented. The single transformer provides resonance at both differential and common modes, eliminating the need for an explicit inductor for the common-mode resonance. It is implemented vertically using two top metal layers, resulting in significant area saving compared to the state-of-the-art. The LC-tank has common mode resonance at twice the VCO frequency, hence reducing the flicker noise corner frequency of the VCO to 450 kHz. A fully-balanced complementary coupled-Class-C design improves efficiency, maintains symmetric swings across the transformer, and improves reliability. A prototype 26.1-to-29.9 GHz VCO, suitable for 5G applications, is implemented in a 65-nm CMOS process occupying an area of 0.04 mm2. The VCO consumes 3.4 mW at 27.45 GHz and exhibits a phase noise of -127.5 dBc/Hz at 10 MHz offset resulting in an FoM of -191 dB/Hz.
{"title":"A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz","authors":"A. H. M. Shirazi, M. Mahani, H. M. Lavasani, S. Mirabbasi, S. Shekhar, R. Zavari, H. Djahanshahi","doi":"10.1109/CICC48029.2020.9075909","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075909","url":null,"abstract":"A compact dual-core, single-transformer, and low-power voltage-controlled oscillator (VCO) is presented. The single transformer provides resonance at both differential and common modes, eliminating the need for an explicit inductor for the common-mode resonance. It is implemented vertically using two top metal layers, resulting in significant area saving compared to the state-of-the-art. The LC-tank has common mode resonance at twice the VCO frequency, hence reducing the flicker noise corner frequency of the VCO to 450 kHz. A fully-balanced complementary coupled-Class-C design improves efficiency, maintains symmetric swings across the transformer, and improves reliability. A prototype 26.1-to-29.9 GHz VCO, suitable for 5G applications, is implemented in a 65-nm CMOS process occupying an area of 0.04 mm2. The VCO consumes 3.4 mW at 27.45 GHz and exhibits a phase noise of -127.5 dBc/Hz at 10 MHz offset resulting in an FoM of -191 dB/Hz.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125999374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075876
Liang Fang, P. Gui
This paper presents a 13n V /✓Hz Capacitively-coupled Chopper Instrumentation Amplifier (CCIA) implemented in 180nm CMOS. Two new techniques are proposed to address two known drawbacks of CCIAs, chopping ripple and limited input impedance. An improved dynamic offset zeroing (iDOZ) is proposed to suppress the chopping ripple to a mean value of 300μ V and a standard deviation of 500μV, with negligible power, area and noise overhead. A highly-linear three-terminal varactor is proposed in the positive feedback loop of the CCIA to boost the input impedance by 1000 times. This design consumes 4.5 μW power and achieves a noise efficiency factor of 1.3 and a power efficiency factor of 1.1.
提出了一种采用180nm CMOS实现的13n V /✓Hz电容耦合斩波仪表放大器(CCIA)。提出了两种新技术来解决ccia的两个已知缺点，斩波纹波和有限的输入阻抗。提出了一种改进的动态偏置调零(iDOZ)方法，可将斩波抑制到300μ V的平均值和500μV的标准差，且功率、面积和噪声开销可忽略。在CCIA的正反馈回路中提出了一种高线性三端变容器，将输入阻抗提高了1000倍。本设计功耗为4.5 μW，噪声效率系数为1.3，功率效率系数为1.1。
{"title":"A 13nV/✓Hz 4.5μW Chopper Instrumentation Amplifier with Robust Ripple Reduction and Input Impedance Boosting Techniques","authors":"Liang Fang, P. Gui","doi":"10.1109/CICC48029.2020.9075876","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075876","url":null,"abstract":"This paper presents a 13n V /✓Hz Capacitively-coupled Chopper Instrumentation Amplifier (CCIA) implemented in 180nm CMOS. Two new techniques are proposed to address two known drawbacks of CCIAs, chopping ripple and limited input impedance. An improved dynamic offset zeroing (iDOZ) is proposed to suppress the chopping ripple to a mean value of 300μ V and a standard deviation of 500μV, with negligible power, area and noise overhead. A highly-linear three-terminal varactor is proposed in the positive feedback loop of the CCIA to boost the input impedance by 1000 times. This design consumes 4.5 μW power and achieves a noise efficiency factor of 1.3 and a power efficiency factor of 1.1.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126090079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075931
Minkyu Kim, Jae-sun Seo
This paper presents an ASIC accelerator for deep convolutional neural networks (DCNNs) featuring a novel conditional computing scheme that synergistically combines precision-cascading with zero-skipping. To reduce many redundant convolution operations that are followed by max-pooling operations, we propose precision-cascading, where the input features are divided into a number of low-precision groups and approximate convolutions with only the most significant bits (MSBs) are performed first. Based on this approximate computation, the full-precision convolution is performed only on the maximum pooling output that is found. This way, the total number of bit-wise convolutions can be reduced by ~2× without affecting the output feature values and with <0.8% degradation in final ImageNet classification accuracy. Precision-cascading provides the added benefit of increased sparsity per low-precision group, which we exploit with zero-skipping to eliminate clock cycles as well as external memory access that involve zero inputs. By jointly optimizing the conditional computing scheme and hardware architecture, the 40nm prototype chip demonstrates a peak energy-efficiency of 8.85 TOPS/W at 0.9V supply and low external memory access of 55.31 MB (or 0.0018 access/MAC) for ImageNet classification with VGG-16 CNN.
{"title":"Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access","authors":"Minkyu Kim, Jae-sun Seo","doi":"10.1109/CICC48029.2020.9075931","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075931","url":null,"abstract":"This paper presents an ASIC accelerator for deep convolutional neural networks (DCNNs) featuring a novel conditional computing scheme that synergistically combines precision-cascading with zero-skipping. To reduce many redundant convolution operations that are followed by max-pooling operations, we propose precision-cascading, where the input features are divided into a number of low-precision groups and approximate convolutions with only the most significant bits (MSBs) are performed first. Based on this approximate computation, the full-precision convolution is performed only on the maximum pooling output that is found. This way, the total number of bit-wise convolutions can be reduced by ~2× without affecting the output feature values and with <0.8% degradation in final ImageNet classification accuracy. Precision-cascading provides the added benefit of increased sparsity per low-precision group, which we exploit with zero-skipping to eliminate clock cycles as well as external memory access that involve zero inputs. By jointly optimizing the conditional computing scheme and hardware architecture, the 40nm prototype chip demonstrates a peak energy-efficiency of 8.85 TOPS/W at 0.9V supply and low external memory access of 55.31 MB (or 0.0018 access/MAC) for ImageNet classification with VGG-16 CNN.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study proposes a 368 $times 184$ optical under-display fingerprint sensor designed and prototyped using $0.11-mu mathrm{m}$ CIS technology. The prototype sensor with global shutter operation and an ADC-embedded in an 8-pixel configuration features low noise, low-power consumption, fast response time, and a smaller signal processing circuit area. Two sets of memory (184 × 92 bytes) are also embedded in the pixel array to save external memory cost. A dynamic range of 126 dB is achieved with 8-segment auto exposure and dark level adjustment with programmable gain control. The prototype fingerprint sensor was successfully embedded in a mobile phone for functional verification, and the power consumption was only 25 mW with a 3.3 V supply voltage. The sensor has a chip size of 9.74 mm $times 4.6$ mm, a resolution of 1154 dpi, and a sensing area of 73%.
{"title":"A 368 × 184 Optical Under-Display Fingerprint Sensor With Global Shutter and High-Dynamic-Range Operation","authors":"Ping-Hung Yin, Chih-Wen Lu, Jia-Shyang Wang, Keng-Li Chang, Fu-Kuo Lin, Chia-Jung Chang, Gen-Chiuan Bai","doi":"10.1109/CICC48029.2020.9075898","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075898","url":null,"abstract":"This study proposes a 368 $times 184$ optical under-display fingerprint sensor designed and prototyped using $0.11-mu mathrm{m}$ CIS technology. The prototype sensor with global shutter operation and an ADC-embedded in an 8-pixel configuration features low noise, low-power consumption, fast response time, and a smaller signal processing circuit area. Two sets of memory (184 × 92 bytes) are also embedded in the pixel array to save external memory cost. A dynamic range of 126 dB is achieved with 8-segment auto exposure and dark level adjustment with programmable gain control. The prototype fingerprint sensor was successfully embedded in a mobile phone for functional verification, and the power consumption was only 25 mW with a 3.3 V supply voltage. The sensor has a chip size of 9.74 mm $times 4.6$ mm, a resolution of 1154 dpi, and a sensing area of 73%.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075899
Sukjin Kim, R. Sithanandam, Woojin Seo, Mijin Lee, Sangyoung Cho, Juho Park, Hyuk-Mim Kwon, Namho Kim, Chanhee Jeon
Continuous optimization of power, performance and area lead to the evolution of planar CMOS to the FinFET technology. With further scaling, the use of EUV lithography for 7nm and below technologies became a necessity. Extensive literature is available for the optimizing the digital and analog performances using FinFET technologies. However, there is a dearth of literature in analyzing the ESD performance and scaling trends across various FinFET technologies. This paper is an attempt to present the design choices, challenges and solutions available for the robust ESD protection. ESD devices of the general purpose I/O's (N+/Psub, NW/Psub, P+/NW diodes) and failsafe I/O's (GGNMOS) are analyzed in 14nm, 10nm and 7nm FinFET technologies. For the first time, a brief note on the new charge based CDM analysis strategy which ensures first time silicon success is also explained. The test structure development, fabrication, testing and results are performed at Samsung Foundry.
{"title":"Technology Scaling of ESD Devices in State of the Art FinFET Technologies","authors":"Sukjin Kim, R. Sithanandam, Woojin Seo, Mijin Lee, Sangyoung Cho, Juho Park, Hyuk-Mim Kwon, Namho Kim, Chanhee Jeon","doi":"10.1109/CICC48029.2020.9075899","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075899","url":null,"abstract":"Continuous optimization of power, performance and area lead to the evolution of planar CMOS to the FinFET technology. With further scaling, the use of EUV lithography for 7nm and below technologies became a necessity. Extensive literature is available for the optimizing the digital and analog performances using FinFET technologies. However, there is a dearth of literature in analyzing the ESD performance and scaling trends across various FinFET technologies. This paper is an attempt to present the design choices, challenges and solutions available for the robust ESD protection. ESD devices of the general purpose I/O's (N+/Psub, NW/Psub, P+/NW diodes) and failsafe I/O's (GGNMOS) are analyzed in 14nm, 10nm and 7nm FinFET technologies. For the first time, a brief note on the new charge based CDM analysis strategy which ensures first time silicon success is also explained. The test structure development, fabrication, testing and results are performed at Samsung Foundry.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123998693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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