Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075925
Haixin Song, W. Rhee, Zhihua Wang
This paper describes a communication/ranging pulse-based transceiver that enables physical-layer security against relay attack. A reconfigurable transceiver system with concatenation operation is designed by having PPM/PWM-based two-bit communication between the prover and the verifier, significantly reducing the processing latency of the prover. Multichannel transmission with enhanced spectral efficiency and link margin are realized with channel hopping and subband hopping methods. A prototype 6-8GHz UWB/VWB transceiver is implemented in 65nm CMOS. The transceiver achieves a processing latency of <3.5ns for the prover and an RMS ranging accuracy of 1.0cm for the verifier, consuming 8.3mW with -73dBm sensitivity at 5Mb/$s$.
{"title":"A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity","authors":"Haixin Song, W. Rhee, Zhihua Wang","doi":"10.1109/CICC48029.2020.9075925","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075925","url":null,"abstract":"This paper describes a communication/ranging pulse-based transceiver that enables physical-layer security against relay attack. A reconfigurable transceiver system with concatenation operation is designed by having PPM/PWM-based two-bit communication between the prover and the verifier, significantly reducing the processing latency of the prover. Multichannel transmission with enhanced spectral efficiency and link margin are realized with channel hopping and subband hopping methods. A prototype 6-8GHz UWB/VWB transceiver is implemented in 65nm CMOS. The transceiver achieves a processing latency of <3.5ns for the prover and an RMS ranging accuracy of 1.0cm for the verifier, consuming 8.3mW with -73dBm sensitivity at 5Mb/$s$.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132778541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075916
P. Payandehnia, Tao He, Yanchao Wang, G. Temes
In many data converter structures, an embedded digital-to-analog converter (DAC) is a key block, and its mismatch and dynamic errors limit the overall accuracy of the operation. Examples include multi-bit ΔΣ and incremental analog-to-digital converters (ADCs) and successive-approximation-register (SAR) ADCs. In this paper, an overview of existing methods for correcting or mitigating the effects of DAC imperfections is presented. Also, a new foreground digital correction method is described for the mitigation of static mismatch errors in the binary-weighted DAC of a multi-bit ΔΣ or incremental ADC. With minor modifications the correction processes can also be applied to the DAC of a SAR ADC, and the tuning of passive elements used in data converters.
{"title":"Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial","authors":"P. Payandehnia, Tao He, Yanchao Wang, G. Temes","doi":"10.1109/CICC48029.2020.9075916","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075916","url":null,"abstract":"In many data converter structures, an embedded digital-to-analog converter (DAC) is a key block, and its mismatch and dynamic errors limit the overall accuracy of the operation. Examples include multi-bit ΔΣ and incremental analog-to-digital converters (ADCs) and successive-approximation-register (SAR) ADCs. In this paper, an overview of existing methods for correcting or mitigating the effects of DAC imperfections is presented. Also, a new foreground digital correction method is described for the mitigation of static mismatch errors in the binary-weighted DAC of a multi-bit ΔΣ or incremental ADC. With minor modifications the correction processes can also be applied to the DAC of a SAR ADC, and the tuning of passive elements used in data converters.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132880480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075913
Paolo Mantovani, R. Margelli, Davide Giri, L. Carloni
The growing complexity of system-on-chip fuels the adoption of high-level synthesis (HLS) to reduce the design time of application-specific accelerators. General-purpose processors, however, are still designed using RTL and logic synthesis. Yet they are the most complex components of most systems-on-chip. We show that HLS can simplify the design of processors while enhancing their customization and reusability. We present HL5 as the first 32-bit RISC-V microprocessor designed with SystemC and optimized with a commercial HLS tool. We evalute HL5 through the execution of software programs on an experimental infrastructure that combines FPGA emulation with a standard RTL synthesis flow for a commercial 32 nm CMOS technology. By describing the challenges and opportunities of applying HLS to processor design, our paper aims also at sparking a renewed interest in HLS research.
{"title":"HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis","authors":"Paolo Mantovani, R. Margelli, Davide Giri, L. Carloni","doi":"10.1109/CICC48029.2020.9075913","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075913","url":null,"abstract":"The growing complexity of system-on-chip fuels the adoption of high-level synthesis (HLS) to reduce the design time of application-specific accelerators. General-purpose processors, however, are still designed using RTL and logic synthesis. Yet they are the most complex components of most systems-on-chip. We show that HLS can simplify the design of processors while enhancing their customization and reusability. We present HL5 as the first 32-bit RISC-V microprocessor designed with SystemC and optimized with a commercial HLS tool. We evalute HL5 through the execution of software programs on an experimental infrastructure that combines FPGA emulation with a standard RTL synthesis flow for a commercial 32 nm CMOS technology. By describing the challenges and opportunities of applying HLS to processor design, our paper aims also at sparking a renewed interest in HLS research.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075892
Zhiyuan Zhou, Nghia Tang, Bai Nguyen, Wookpyo Hong, P. Pande, D. Heo
To improve the power delivery in System-on-Chips (SoCs), this paper proposes a single-input-multi-output (SIMO) hybrid converter to obtain fast response time, low cross regulation, and 87% peak efficiency by using a multi-output hybrid power stage and dual-switching-frequency technique. The multiple-output hybrid power stage improves the conversion efficiency without sacrificing the output voltage range, and the dual-switching-frequency technique enhances the response time and cross-regulation performance. The proposed SIMO hybrid converter achieves 87.5% peak efficiency with an output voltage range from 0.4V to 1.6V for all outputs and a total maximum load current of 450mAAdditionally, it achieves less than 0.01mA/mV cross-regulation and less than 20mV overshoot at full-load step transient response.
{"title":"A Wide Output Voltage Range Single-Input-Multi-Output Hybrid DC-DC Converter Achieving 87.5% Peak Efficiency With a Fast Response Time and Low Cross Regulation for DVFS Applications","authors":"Zhiyuan Zhou, Nghia Tang, Bai Nguyen, Wookpyo Hong, P. Pande, D. Heo","doi":"10.1109/CICC48029.2020.9075892","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075892","url":null,"abstract":"To improve the power delivery in System-on-Chips (SoCs), this paper proposes a single-input-multi-output (SIMO) hybrid converter to obtain fast response time, low cross regulation, and 87% peak efficiency by using a multi-output hybrid power stage and dual-switching-frequency technique. The multiple-output hybrid power stage improves the conversion efficiency without sacrificing the output voltage range, and the dual-switching-frequency technique enhances the response time and cross-regulation performance. The proposed SIMO hybrid converter achieves 87.5% peak efficiency with an output voltage range from 0.4V to 1.6V for all outputs and a total maximum load current of 450mAAdditionally, it achieves less than 0.01mA/mV cross-regulation and less than 20mV overshoot at full-load step transient response.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123052020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This invited paper surveys the recent progresses of compute-in-memory (CIM) prototype chip designs with emerging nonvolatile memories (eNVMs) such as resistive random access memory (RRAM) technology. 8kb to 4Mb CIM mixed-signal macros (with analog computation within the memory array) have been demonstrated by academia and industry, showing promising energy efficiency and throughput for machine learning inference acceleration. However, grand challenges exist for large-scale system design including the following: 1) substantial analog-to-digital (ADC) overhead; 2) scalability to advanced logic node limited by high write voltage of eNVMs; 3) process variations (e.g. ADC offset) that degrade the inference accuracy. Mitigation strategies and possible future research directions are discussed.
{"title":"Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects","authors":"Shimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang","doi":"10.1109/CICC48029.2020.9075887","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075887","url":null,"abstract":"This invited paper surveys the recent progresses of compute-in-memory (CIM) prototype chip designs with emerging nonvolatile memories (eNVMs) such as resistive random access memory (RRAM) technology. 8kb to 4Mb CIM mixed-signal macros (with analog computation within the memory array) have been demonstrated by academia and industry, showing promising energy efficiency and throughput for machine learning inference acceleration. However, grand challenges exist for large-scale system design including the following: 1) substantial analog-to-digital (ADC) overhead; 2) scalability to advanced logic node limited by high write voltage of eNVMs; 3) process variations (e.g. ADC offset) that degrade the inference accuracy. Mitigation strategies and possible future research directions are discussed.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075874
Assim Boukhayma, Antonino Caizzone, Raffaele Capoccia, C. Enz
The current trend towards embedding more and more light sensors in portable and wearable devices is calling for higher integration and reuse of the sensor interface electronics. In many applications, the light needs to be generated locally, which becomes the dominant source of power consumption. Power can hence be saved by making the sensor more sensitive to lower light. At low light the noise is totally dominated by the noise coming from the electronic readout chain. This paper shows how this noise can be minimized all along the readout chain, from the pixel to the ADC. It also shows that many low-light applications actually share the same readout architecture. The latter is made of the pixel including a source follower, a shared amplifier and a correlated double sampling (CDS) or correlated multiple sampling (CMS) stage that is key for eliminating the low-frequency noise and reducing the white noise for CMS. It is shown how each of these building blocks can be optimized for reaching a minimum input-referred noise. The design methodology is then illustrated by three applications, including a 0.5 etectonrms., CMOS VGA imager, a 2.6 µW PPG sensor and a 10 µW 1D time-of-flight distance ranging device.
{"title":"Design and Optimization of Low Power and Low Light Sensor: (Invited)","authors":"Assim Boukhayma, Antonino Caizzone, Raffaele Capoccia, C. Enz","doi":"10.1109/CICC48029.2020.9075874","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075874","url":null,"abstract":"The current trend towards embedding more and more light sensors in portable and wearable devices is calling for higher integration and reuse of the sensor interface electronics. In many applications, the light needs to be generated locally, which becomes the dominant source of power consumption. Power can hence be saved by making the sensor more sensitive to lower light. At low light the noise is totally dominated by the noise coming from the electronic readout chain. This paper shows how this noise can be minimized all along the readout chain, from the pixel to the ADC. It also shows that many low-light applications actually share the same readout architecture. The latter is made of the pixel including a source follower, a shared amplifier and a correlated double sampling (CDS) or correlated multiple sampling (CMS) stage that is key for eliminating the low-frequency noise and reducing the white noise for CMS. It is shown how each of these building blocks can be optimized for reaching a minimum input-referred noise. The design methodology is then illustrated by three applications, including a 0.5 etectonrms., CMOS VGA imager, a 2.6 µW PPG sensor and a 10 µW 1D time-of-flight distance ranging device.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125284006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075893
Qing Li, Czang-Ho Lee, W. Wong, M. Sachdev
Realization of full-swing logic gates is a challenge using only one transistor type. Most such logic gates do not have full swing with excessive direct path leakage-current. Consequently, realization of multi-stage logic circuits becomes unrealistic. In this paper, we propose design of logic gates that do not suffer from these problems. As a proof of concept, we fabricated a 3-to-8 decoder with n-type only a-Si:H TFTs. Simulation and measurement results have demonstrated that the circuit could maintain unity stage-to-stage gain, while reduce more than 85% of static leakage current and 20% area when compared with other implementations.
{"title":"Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology","authors":"Qing Li, Czang-Ho Lee, W. Wong, M. Sachdev","doi":"10.1109/CICC48029.2020.9075893","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075893","url":null,"abstract":"Realization of full-swing logic gates is a challenge using only one transistor type. Most such logic gates do not have full swing with excessive direct path leakage-current. Consequently, realization of multi-stage logic circuits becomes unrealistic. In this paper, we propose design of logic gates that do not suffer from these problems. As a proof of concept, we fabricated a 3-to-8 decoder with n-type only a-Si:H TFTs. Simulation and measurement results have demonstrated that the circuit could maintain unity stage-to-stage gain, while reduce more than 85% of static leakage current and 20% area when compared with other implementations.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116102094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075875
Kunyang Liu, Hongliang Pu, H. Shinohara
This paper presents a bit-error free SRAM-based physically unclonable function (PUF) in 130-nm standard CMOS. The PUF has a compact bitcell, with a bitcell area of 497 F2. It switches from EE SRAM to CMOS SRAM mode during evaluation, achieving high native stability, low-voltage evaluation, and low-power operation. Its stability is reinforced to 100% through hot carrier injection (HCI) burn-in on the alternate-direction nMOS load, which causes no visible oxide damage and does not require additional fabrication processes or extra transistors in the bitcell. Experimental results show that the prototype chips achieved actual zero bit error across 0.5-0.7 V and -40°C to 120 °C, as well as zero error (<1E-7 BER) at the worst VT corner after accelerated aging test equivalent to ~21 years of operation. The PUF functions stably down to 0.5 V, with an energy of 2.07 fJ/b, which includes both the evaluation and read-out power. The secure, compact, low-power and 100% stable features of the PUF make it an excellent candidate for the resource-constrained Internet of Things security.
{"title":"A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in","authors":"Kunyang Liu, Hongliang Pu, H. Shinohara","doi":"10.1109/CICC48029.2020.9075875","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075875","url":null,"abstract":"This paper presents a bit-error free SRAM-based physically unclonable function (PUF) in 130-nm standard CMOS. The PUF has a compact bitcell, with a bitcell area of 497 F2. It switches from EE SRAM to CMOS SRAM mode during evaluation, achieving high native stability, low-voltage evaluation, and low-power operation. Its stability is reinforced to 100% through hot carrier injection (HCI) burn-in on the alternate-direction nMOS load, which causes no visible oxide damage and does not require additional fabrication processes or extra transistors in the bitcell. Experimental results show that the prototype chips achieved actual zero bit error across 0.5-0.7 V and -40°C to 120 °C, as well as zero error (<1E-7 BER) at the worst VT corner after accelerated aging test equivalent to ~21 years of operation. The PUF functions stably down to 0.5 V, with an energy of 2.07 fJ/b, which includes both the evaluation and read-out power. The secure, compact, low-power and 100% stable features of the PUF make it an excellent candidate for the resource-constrained Internet of Things security.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123237557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075879
Shuo Li, B. Calhoun
The power consumption of ultra-low-power (ULP) Internet-of-Things (IoT) SoCs and components has been scaling down from µW to pW levels over the past ten years. Designing energy harvesting and power management units (EH-PMUs) that consume sub-µA quiescent current to efficiently provide such low load current is challenging. This paper reviews the trends and techniques for sub-µA EH-PMUs with a specific focus on the choice between analog and digital implementations. We first discuss ULP EH-PMU design trends based on recent published results and then analyze three design examples. The first example reviews a popular multiple-input multiple-output (MIMO) EH-PMU architecture with ultra-low quiescent current and compares tradeoffs for analog vs. digital zero-current detectors. The second example discusses the design of analog and digital low-dropout regulators (LDOs) with a performance comparison from silicon measurement results. The digital LDO can achieve faster settling time for step response than the analog structure, but the analog LDO has no ripple, making it ideal for noise-sensitive blocks like RF. Finally, an analog power monitor for maximum-power-point tracking (MPPT) in a piezoelectric energy harvester utilizes subthreshold transistor characteristics to simply a complex algorithm and to maintain low power consumption.
{"title":"Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations","authors":"Shuo Li, B. Calhoun","doi":"10.1109/CICC48029.2020.9075879","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075879","url":null,"abstract":"The power consumption of ultra-low-power (ULP) Internet-of-Things (IoT) SoCs and components has been scaling down from µW to pW levels over the past ten years. Designing energy harvesting and power management units (EH-PMUs) that consume sub-µA quiescent current to efficiently provide such low load current is challenging. This paper reviews the trends and techniques for sub-µA EH-PMUs with a specific focus on the choice between analog and digital implementations. We first discuss ULP EH-PMU design trends based on recent published results and then analyze three design examples. The first example reviews a popular multiple-input multiple-output (MIMO) EH-PMU architecture with ultra-low quiescent current and compares tradeoffs for analog vs. digital zero-current detectors. The second example discusses the design of analog and digital low-dropout regulators (LDOs) with a performance comparison from silicon measurement results. The digital LDO can achieve faster settling time for step response than the analog structure, but the analog LDO has no ripple, making it ideal for noise-sensitive blocks like RF. Finally, an analog power monitor for maximum-power-point tracking (MPPT) in a piezoelectric energy harvester utilizes subthreshold transistor characteristics to simply a complex algorithm and to maintain low power consumption.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125509563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075905
Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, R. Xu, Abhishek Mukherjee, T. Andeen, Nan Sun
This paper presents an enhanced interstage gain error shaping technique that adopts a digital error feedback technique to extend the interstage gain error tolerance by 5 times. This paper also proposes a passive quantization error shaping technique that reduces the ratio of the two-input-pair comparator by 2.7 times. A prototype equipped with the proposed techniques is implemented in 40nm CMOS. It achieves a SNDR of 77.1 dB over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves 173.7 dB Schreier FoM.
本文提出了一种增强型级间增益误差整形技术，该技术采用数字误差反馈技术，将级间增益误差容忍度提高了5倍。本文还提出了一种被动量化误差整形技术，使双输入对比较器的比率降低了2.7倍。采用该技术的原型机在40nm CMOS上实现。它在6.25 mhz带宽上实现了77.1 dB的SNDR，工作速度为100 MS/s，功耗为1.38 mW。它达到173.7 dB Schreier FoM。
{"title":"A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping","authors":"Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, R. Xu, Abhishek Mukherjee, T. Andeen, Nan Sun","doi":"10.1109/CICC48029.2020.9075905","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075905","url":null,"abstract":"This paper presents an enhanced interstage gain error shaping technique that adopts a digital error feedback technique to extend the interstage gain error tolerance by 5 times. This paper also proposes a passive quantization error shaping technique that reduces the ratio of the two-input-pair comparator by 2.7 times. A prototype equipped with the proposed techniques is implemented in 40nm CMOS. It achieves a SNDR of 77.1 dB over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves 173.7 dB Schreier FoM.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128437247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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