Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075873
Sungsik Park, Yunhong Kim, Woojun Choi, Yongtae Lee, Sungbeen Kim, Youngmin Shin, Youngcheol Chae
This paper presents a compact temperature sensor that directly controls a temperature-dependent self-refresh period of a mobile DRAM in 28nm CMOS. It uses a dynamic threshold MOST (DTMOST) as a sensing device that periodically discharges a capacitor. The discharging voltage across the capacitor denotes a supply-independent behavior and the temperature-dependent discharging period of the DTMOST diode is detected by incorporating it into a relaxation oscillator. The sensor occupies only 0.017mm2 and achieves a 3σ inaccuracy of ±0.9°C from -10 to 90°C after 1-point trim. Operating from 0.85 to 1.15V, it shows a low supply sensitivity of 0.27°C/V at room temperature. It consumes 33.75µW and achieves a resolution of 10.2mK. This corresponds to a resolution FoM of 0.36pJ· K2.
{"title":"A DTMOST-based Temperature Sensor with 3σ Inaccuracy of ±0.9°C for Self-Refresh Control in 28nm Mobile DRAM","authors":"Sungsik Park, Yunhong Kim, Woojun Choi, Yongtae Lee, Sungbeen Kim, Youngmin Shin, Youngcheol Chae","doi":"10.1109/CICC48029.2020.9075873","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075873","url":null,"abstract":"This paper presents a compact temperature sensor that directly controls a temperature-dependent self-refresh period of a mobile DRAM in 28nm CMOS. It uses a dynamic threshold MOST (DTMOST) as a sensing device that periodically discharges a capacitor. The discharging voltage across the capacitor denotes a supply-independent behavior and the temperature-dependent discharging period of the DTMOST diode is detected by incorporating it into a relaxation oscillator. The sensor occupies only 0.017mm2 and achieves a 3σ inaccuracy of ±0.9°C from -10 to 90°C after 1-point trim. Operating from 0.85 to 1.15V, it shows a low supply sensitivity of 0.27°C/V at room temperature. It consumes 33.75µW and achieves a resolution of 10.2mK. This corresponds to a resolution FoM of 0.36pJ· K2.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126706704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075944
Hossein Rahmanian Kooshkaki, P. Mercier
This paper presents a sub-mW single supply fractional-NPLL for Narrowband IoT (NB-IoT) applications. The analog PLL meets the relatively strict spur requirement of NB-IoT while using a low power class-D oscillator with a resistive header, which improves phase noise by 3dB and reduces power consumption by 25% with negligible area overhead. The VCO, working at 729-960MHz, is powered by an on-chip DC-DC converter with 90% efficiency designed in a manner to not degrade the spur performance of the PLL, which is measured to be -67.5dBc for reference and -66.3dBc for fractional spurs.
{"title":"A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT","authors":"Hossein Rahmanian Kooshkaki, P. Mercier","doi":"10.1109/CICC48029.2020.9075944","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075944","url":null,"abstract":"This paper presents a sub-mW single supply fractional-NPLL for Narrowband IoT (NB-IoT) applications. The analog PLL meets the relatively strict spur requirement of NB-IoT while using a low power class-D oscillator with a resistive header, which improves phase noise by 3dB and reduces power consumption by 25% with negligible area overhead. The VCO, working at 729-960MHz, is powered by an on-chip DC-DC converter with 90% efficiency designed in a manner to not degrade the spur performance of the PLL, which is measured to be -67.5dBc for reference and -66.3dBc for fractional spurs.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127348533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075895
S. Amin, P. Mercier
This paper presents a miniaturized Li-ion-compatible 5-level hybrid single-inductor multi-output (H-SIMO) power management unit (PMU) in 28nm FD-SOI for powering IoT devices. Miniaturization is achieved by combining the benefits of SIMO converters with the benefits of hybrid multi-level converters. The PMU is implemented in 28nm FD-SOI in an arrangement that naturally exploits the required transistor stacking of a 5-level converter to enable full coverage of the 2.8-4.2V Li-ion battery voltage range using only 1V thin-oxide transistors. The 0.42mm2 die independently regulates three different outputs over 0.4-0.9V from 10µW to 40mW using a single 1.28mm3 inductor with 91.4% peak efficiency.
{"title":"H-SIMO: A Hybrid Single-Inductor Multi-Output 5-Level Thin-Oxide Power Management Unit Achieving 91.4% Efficiency from Li-ion Battery Voltages in 28nm FD-SOI","authors":"S. Amin, P. Mercier","doi":"10.1109/CICC48029.2020.9075895","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075895","url":null,"abstract":"This paper presents a miniaturized Li-ion-compatible 5-level hybrid single-inductor multi-output (H-SIMO) power management unit (PMU) in 28nm FD-SOI for powering IoT devices. Miniaturization is achieved by combining the benefits of SIMO converters with the benefits of hybrid multi-level converters. The PMU is implemented in 28nm FD-SOI in an arrangement that naturally exploits the required transistor stacking of a 5-level converter to enable full coverage of the 2.8-4.2V Li-ion battery voltage range using only 1V thin-oxide transistors. The 0.42mm2 die independently regulates three different outputs over 0.4-0.9V from 10µW to 40mW using a single 1.28mm3 inductor with 91.4% peak efficiency.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132529466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075891
Haoyu Zhuang, Jiaxin Liu, Nan Sun
This paper presents a fully-dynamic, low-power, and wide-band time-interleaved (TI) noise-shaping (NS) SAR ADC based on the cascade of integrators with feed-forward (CIFF) architecture. Its loop filter and interleaving operation are realized by fully-passive switched capacitor (SC) circuits. Its feedforward summation is implemented by using a multi-path comparator. Moreover, its overall noise transfer function (NTF) is set by device ratios and highly robust against process, voltage, and temperature (PVT) variations. It allows the loop filter poles to be placed close to the unit circle. Comparing to a recently published TI NS SAR ADC based on the error-feedback (EF) structure, this work obviates the need for amplifiers with static current, saving power. It also eliminates the dependence of NTF on the amplifier gain, which is PVT sensitive. A prototype ADC in 40nm process achieves 69.1dB SNDR over 50MHz BW while consuming only 8.5mW from a 1.1V supply, leading to a Walden FoM of 36.3fJ/conv.-step.
本文提出了一种基于前馈(CIFF)结构的级联积分器的全动态、低功耗、宽带时交织噪声整形(NS) SAR ADC。其环路滤波和交错运算由全无源开关电容(SC)电路实现。它的前馈求和是通过使用多路径比较器来实现的。此外，它的总体噪声传递函数(NTF)由器件比率设定，对工艺、电压和温度(PVT)变化具有高度鲁棒性。它允许回路滤波器极点被放置在单位圆附近。与最近发布的基于误差反馈(EF)结构的TI NS SAR ADC相比，该工作消除了对静态电流放大器的需求，节省了功耗。它还消除了NTF对放大器增益的依赖，放大器增益是PVT敏感的。40nm制程的原型ADC在50MHz BW下实现69.1dB SNDR，而在1.1V电源下仅消耗8.5mW, Walden FoM为36.3fJ/con .-step。
{"title":"A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture","authors":"Haoyu Zhuang, Jiaxin Liu, Nan Sun","doi":"10.1109/CICC48029.2020.9075891","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075891","url":null,"abstract":"This paper presents a fully-dynamic, low-power, and wide-band time-interleaved (TI) noise-shaping (NS) SAR ADC based on the cascade of integrators with feed-forward (CIFF) architecture. Its loop filter and interleaving operation are realized by fully-passive switched capacitor (SC) circuits. Its feedforward summation is implemented by using a multi-path comparator. Moreover, its overall noise transfer function (NTF) is set by device ratios and highly robust against process, voltage, and temperature (PVT) variations. It allows the loop filter poles to be placed close to the unit circle. Comparing to a recently published TI NS SAR ADC based on the error-feedback (EF) structure, this work obviates the need for amplifiers with static current, saving power. It also eliminates the dependence of NTF on the amplifier gain, which is PVT sensitive. A prototype ADC in 40nm process achieves 69.1dB SNDR over 50MHz BW while consuming only 8.5mW from a 1.1V supply, leading to a Walden FoM of 36.3fJ/conv.-step.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133072527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075880
Chen Chen, Jin Liu, Hoi Lee
This paper presents a 3-switch zero-voltage switching (ZVS) step-up /-down hybrid DC-DC converter for automotive applications. By having a flying capacitor, the proposed converter saves 1 auxiliary branch for establishing ZVS, and 1 power FET compared to the conventional buck-boost topology. With ZVS turn-on of all power FETs, the proposed converter is able to operate in the MHz range with high power efficiency in high input voltages via minimizing the switching loss. The flying capacitor further reduces the main inductor current in the step-down mode, significantly decreasing the inductor conduction loss. The proposed converter was validated using 100v e-mode GaN FETs with the on-chip gate drivers and control circuitry implemented in a HV 0.5µm BCD process. The proposed converter can support a wide input range from 9V to 45V with a maximum 48W output power, operate at 2MHz, and achieve peak power efficiencies of 98% and 96% in step-down and -up modes, respectively. The volume of external components in the proposed converter is also reduced by at least 5 times compared with the prior art.
{"title":"A 9 - 45V Input 2MHz 3-Switch ZVS Step-up / -down Hybrid Converter with 5x Volume Reduction","authors":"Chen Chen, Jin Liu, Hoi Lee","doi":"10.1109/CICC48029.2020.9075880","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075880","url":null,"abstract":"This paper presents a 3-switch zero-voltage switching (ZVS) step-up /-down hybrid DC-DC converter for automotive applications. By having a flying capacitor, the proposed converter saves 1 auxiliary branch for establishing ZVS, and 1 power FET compared to the conventional buck-boost topology. With ZVS turn-on of all power FETs, the proposed converter is able to operate in the MHz range with high power efficiency in high input voltages via minimizing the switching loss. The flying capacitor further reduces the main inductor current in the step-down mode, significantly decreasing the inductor conduction loss. The proposed converter was validated using 100v e-mode GaN FETs with the on-chip gate drivers and control circuitry implemented in a HV 0.5µm BCD process. The proposed converter can support a wide input range from 9V to 45V with a maximum 48W output power, operate at 2MHz, and achieve peak power efficiencies of 98% and 96% in step-down and -up modes, respectively. The volume of external components in the proposed converter is also reduced by at least 5 times compared with the prior art.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122779453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075877
Ckristian Duran, Megan Wachs, G. LuisE.Rueda, A. Huntington, Javier Ardila, Jack Kang, Andres Amaya, H. Gómez, Juan Romero, L. Fernandez, Felipe Flechas, Rolando Torres, Juan Sebastian Moya, Wilmer Ramirez, Julian Arenas, J. Gómez, Hanssel Morales, Camilo Rojas, A. Mantilla, E. Roa, K. Asanović
Reported work on minimum-energy (ME) computing for low-power applications has focused entirely on tracking solely the microprocessor ME voltage supply. However, the use of low-power systems requires accounting for regulator losses, voltage monitors, biasing, peripheral, clock sources, and start-up energies to adapt the correct ME supply to different operation modes. Here we demonstrate a 32-bit RISC-V IMAC based microcontroller (MCU) in 180nm CMOS technology featuring a low-energy always-on (AON) subsystem extending on ME adaption by including peripherals. AON peripherals enable the MCU for low-duty-cycle sensor node applications. Low-energy clock sources and voltage monitors enable 32.768kHz to 55MHz operation and power-gate the MCU into three power states adjusted to work at the ME supply operation. Measured start-up energies using integrated RC-based oscillators show restarting energies down to 6pJ, which is 1000X less than the energy required in MCUs that apply crystal oscillators.
{"title":"An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications","authors":"Ckristian Duran, Megan Wachs, G. LuisE.Rueda, A. Huntington, Javier Ardila, Jack Kang, Andres Amaya, H. Gómez, Juan Romero, L. Fernandez, Felipe Flechas, Rolando Torres, Juan Sebastian Moya, Wilmer Ramirez, Julian Arenas, J. Gómez, Hanssel Morales, Camilo Rojas, A. Mantilla, E. Roa, K. Asanović","doi":"10.1109/CICC48029.2020.9075877","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075877","url":null,"abstract":"Reported work on minimum-energy (ME) computing for low-power applications has focused entirely on tracking solely the microprocessor ME voltage supply. However, the use of low-power systems requires accounting for regulator losses, voltage monitors, biasing, peripheral, clock sources, and start-up energies to adapt the correct ME supply to different operation modes. Here we demonstrate a 32-bit RISC-V IMAC based microcontroller (MCU) in 180nm CMOS technology featuring a low-energy always-on (AON) subsystem extending on ME adaption by including peripherals. AON peripherals enable the MCU for low-duty-cycle sensor node applications. Low-energy clock sources and voltage monitors enable 32.768kHz to 55MHz operation and power-gate the MCU into three power states adjusted to work at the ME supply operation. Measured start-up energies using integrated RC-based oscillators show restarting energies down to 6pJ, which is 1000X less than the energy required in MCUs that apply crystal oscillators.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125538482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075890
A. Townley, Nima Baniasadi, Sashank Krishnamurthy, Constantine Sideris, A. Hajimiri, E. Alon, A. Niknejad
In order to meet the demand for increasingly higher data rate wireless links, broad-bandwidth transceivers that support high-spectral-efficiency modulation schemes are required. In this paper, a mm-wave transceiver IC operating at 113GHz is demonstrated, achieving a single-channel data rate of 80Gb/s. The transceiver achieves a high level of integration, including LO generation circuitry, a bits-to-RF TX DAC, and two transceiver channels for polarization diversity. The chip is flip-chip packaged onto a PCB with two orthogonally polarized antennas.
{"title":"A Fully Integrated, Dual Channel, Flip Chip Packaged 113 GHz Transceiver in 28nm CMOS supporting an 80 Gb/s Wireless Link","authors":"A. Townley, Nima Baniasadi, Sashank Krishnamurthy, Constantine Sideris, A. Hajimiri, E. Alon, A. Niknejad","doi":"10.1109/CICC48029.2020.9075890","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075890","url":null,"abstract":"In order to meet the demand for increasingly higher data rate wireless links, broad-bandwidth transceivers that support high-spectral-efficiency modulation schemes are required. In this paper, a mm-wave transceiver IC operating at 113GHz is demonstrated, achieving a single-channel data rate of 80Gb/s. The transceiver achieves a high level of integration, including LO generation circuitry, a bits-to-RF TX DAC, and two transceiver channels for polarization diversity. The chip is flip-chip packaged onto a PCB with two orthogonally polarized antennas.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116431442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075934
H. Krishnamurthy, K. Z. Ahmed, Xiaosen Liu, Nachiket V. Desai, Suhwan Kim, N. Butzen, S. Amin, Sheldon Weng, K. Ravichandran, J. Tschanz, V. De
This work presents a summary of the digital control techniques in todays advanced, state of the art IVRs and the role digital control is playing to enhance their key performance metrics. Examples from high switching frequency Buck converters, computationally controlled digital LDOs as well as digitally assisted analog and hybrid LDOs speaks not only to the growing popularity of digital control in a wide variety of applications but also demonstrates its suitability on advanced process nodes which is inherently tough on analog circuits.
{"title":"Digital Control of Switching and Linear Integrated Voltage Regulators","authors":"H. Krishnamurthy, K. Z. Ahmed, Xiaosen Liu, Nachiket V. Desai, Suhwan Kim, N. Butzen, S. Amin, Sheldon Weng, K. Ravichandran, J. Tschanz, V. De","doi":"10.1109/CICC48029.2020.9075934","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075934","url":null,"abstract":"This work presents a summary of the digital control techniques in todays advanced, state of the art IVRs and the role digital control is playing to enhance their key performance metrics. Examples from high switching frequency Buck converters, computationally controlled digital LDOs as well as digitally assisted analog and hybrid LDOs speaks not only to the growing popularity of digital control in a wide variety of applications but also demonstrates its suitability on advanced process nodes which is inherently tough on analog circuits.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075938
D. Wentzloff, A. Alghaihab, Jaeho Im
Efficient wireless connectivity is an important requirement for IoT applications and has attracted a lot of research interest recently. The receivers designed for such applications need to be low power while still supporting sufficient communication range and co-existing with other receivers that share the same frequency band. In addition, supporting adopted communication standards is key for ubiquitous integration with the existing infrastructure. This paper presents a review of the recent design trends and techniques in ultra-low power receivers for IoT applications.
{"title":"Ultra-Low Power Receivers for IoT Applications: A Review","authors":"D. Wentzloff, A. Alghaihab, Jaeho Im","doi":"10.1109/CICC48029.2020.9075938","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075938","url":null,"abstract":"Efficient wireless connectivity is an important requirement for IoT applications and has attracted a lot of research interest recently. The receivers designed for such applications need to be low power while still supporting sufficient communication range and co-existing with other receivers that share the same frequency band. In addition, supporting adopted communication standards is key for ubiquitous integration with the existing infrastructure. This paper presents a review of the recent design trends and techniques in ultra-low power receivers for IoT applications.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075950
Jaehyuk Lee, Surin Gweon, Kwonjoon Lee, Soyeon Um, Kyoung-Rog Lee, Kwantae Kim, Jihee Lee, H. Yoo
A 10MHz wide-bandwidth Electrical Impedance Tomography (EIT) IC is proposed for compact and high-precision breast cancer detection system. The proposed IC has three key features: 1) wide dynamic range LNA (WDR-LNA), enabling low noise impedance measurements for the high-resolution imaging, 2) reconfigurable front-end architecture (RFA) to remove external multiplexer for the compact system integration, and 3) phase compensation loop (PCL) to efficiently correct the phase error, which is the primary challenge in wide-bandwidth EIT system. Thanks to the key features, the proposed prototype breast cancer detection system with the dedicated EIT IC can operate up to 10 MHz with a small phase error of 4.32 degree, eventually can detect a small size target object of 0.5 cm and verified with the phantom experiments.
{"title":"A 9.6 mW/Ch 10 MHz Wide-bandwidth Electrical Impedance Tomography IC with Accurate Phase Compensation for Breast Cancer Detection","authors":"Jaehyuk Lee, Surin Gweon, Kwonjoon Lee, Soyeon Um, Kyoung-Rog Lee, Kwantae Kim, Jihee Lee, H. Yoo","doi":"10.1109/CICC48029.2020.9075950","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075950","url":null,"abstract":"A 10MHz wide-bandwidth Electrical Impedance Tomography (EIT) IC is proposed for compact and high-precision breast cancer detection system. The proposed IC has three key features: 1) wide dynamic range LNA (WDR-LNA), enabling low noise impedance measurements for the high-resolution imaging, 2) reconfigurable front-end architecture (RFA) to remove external multiplexer for the compact system integration, and 3) phase compensation loop (PCL) to efficiently correct the phase error, which is the primary challenge in wide-bandwidth EIT system. Thanks to the key features, the proposed prototype breast cancer detection system with the dedicated EIT IC can operate up to 10 MHz with a small phase error of 4.32 degree, eventually can detect a small size target object of 0.5 cm and verified with the phantom experiments.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116554560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：