Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075907
Anjana Dissanayake, J. Moody, Henry L. Bishop, D. Truesdell, Henry Muhlbauer, Ruochen Lu, A. Gao, S. Gong, B. Calhoun, S. Bowers
A -108dBm sensitivity, 430MHz, 130nW-41µW, 6.25bps-4.2kbps, digitally tunable wake-up and data receiver in 65nm CMOS is presented. Employing 2-tone RF OOK modulation and an AlN MEMS resonator, the receiver attains close-in SIR of -25dB at 0.12% and far-out SIR of -28dB at 0.7% frequency offset from the carrier. Digitally configurable dynamic ranges of 11dB, 410X, 672X are achieved for sensitivity, power, and latency, respectively. The design receives data at a 4.2kbps bit-rate at - 108dBm sensitivity while consuming 41µW. The proposed WuRx is a highly reconfigurable and interference robust candidate for emerging ultra-long range IoT LPWAN applications.
{"title":"A- 108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver","authors":"Anjana Dissanayake, J. Moody, Henry L. Bishop, D. Truesdell, Henry Muhlbauer, Ruochen Lu, A. Gao, S. Gong, B. Calhoun, S. Bowers","doi":"10.1109/CICC48029.2020.9075907","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075907","url":null,"abstract":"A -108dBm sensitivity, 430MHz, 130nW-41µW, 6.25bps-4.2kbps, digitally tunable wake-up and data receiver in 65nm CMOS is presented. Employing 2-tone RF OOK modulation and an AlN MEMS resonator, the receiver attains close-in SIR of -25dB at 0.12% and far-out SIR of -28dB at 0.7% frequency offset from the carrier. Digitally configurable dynamic ranges of 11dB, 410X, 672X are achieved for sensitivity, power, and latency, respectively. The design receives data at a 4.2kbps bit-rate at - 108dBm sensitivity while consuming 41µW. The proposed WuRx is a highly reconfigurable and interference robust candidate for emerging ultra-long range IoT LPWAN applications.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126004504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075885
Xiaoteng Zhao, Yong Chen, Pui-in Mak, R. Martins
A single-loop full-rate bang-bang CDR without the reference and separate frequency detector (FD) is reported. Its phase detector innovates a strobe-point selection scheme and a hybrid control circuit to automate and accelerate the frequency acquisition over a wide frequency range. Prototyped in 28nm CMOS, our CDR achieves a 23-to-29Gb/s capture range of four-level pulse amplitude modulation (PAM-4) data. The acquisition speed [8.2(Gb/s)/µs], die area (0.0285mm2) and energy efficiency (0.68pJ/bit) compare favorably with the prior art.
{"title":"A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS","authors":"Xiaoteng Zhao, Yong Chen, Pui-in Mak, R. Martins","doi":"10.1109/CICC48029.2020.9075885","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075885","url":null,"abstract":"A single-loop full-rate bang-bang CDR without the reference and separate frequency detector (FD) is reported. Its phase detector innovates a strobe-point selection scheme and a hybrid control circuit to automate and accelerate the frequency acquisition over a wide frequency range. Prototyped in 28nm CMOS, our CDR achieves a 23-to-29Gb/s capture range of four-level pulse amplitude modulation (PAM-4) data. The acquisition speed [8.2(Gb/s)/µs], die area (0.0285mm2) and energy efficiency (0.68pJ/bit) compare favorably with the prior art.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130407688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075914
Hyung-Jin Lee, Steven Callender, S. Rami, W. Shin, Q. Yu, J. Marulanda
Intel's 22FFL is the comprehensive FinFET technology offering the best-in-class RF transistors achieving $f_{t}$ and $f_{max}$ above 300GHz and 450GHz, respectively. The addition of a high-power RF device (HyPowerFF) and enhanced mmWave BEOL support the opportunity to push silicon technology beyond the 5G era.
{"title":"Intel 22nm Low-Power FinFET (22FFL) Process Technology for 5G and Beyond","authors":"Hyung-Jin Lee, Steven Callender, S. Rami, W. Shin, Q. Yu, J. Marulanda","doi":"10.1109/CICC48029.2020.9075914","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075914","url":null,"abstract":"Intel's 22FFL is the comprehensive FinFET technology offering the best-in-class RF transistors achieving $f_{t}$ and $f_{max}$ above 300GHz and 450GHz, respectively. The addition of a high-power RF device (HyPowerFF) and enhanced mmWave BEOL support the opportunity to push silicon technology beyond the 5G era.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121566369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075939
S. Dong, I. Momson, S. Kshattry, Pavan Yelleswarapu, W. Choi, K. O. Kenneth
A 180 GHz mixer-first phase-locked-loop based MSK receiver is demonstrated in 65-nm CMOS. Double balanced anti-parallel-diode-pair (APDP) based sub-harmonic mixer forms the phase detector. Compensation using multiple zeros reduces the effect of in-loop delay on the stability of PLL. Without external LO synchronization, the receiver achieves 10 Gbps with a BER < 10−12 at -24-dBm available input power. The open loop measurements show the down-conversion chain has a 3-dB bandwidth of approximately 48 GHz at 180 GHz and the minimum single side band (SSB) noise figure of 18.6 dB. This receiver is the self-synchronized receiver using coherent detection with the highest operating frequency in CMOS. This work also demonstrates that a PLL based receiver can support data rates in excess of 10 Gbps.
{"title":"A Wideband 180-GHz Phase-Lacked-Loop Based MSK Receiver","authors":"S. Dong, I. Momson, S. Kshattry, Pavan Yelleswarapu, W. Choi, K. O. Kenneth","doi":"10.1109/CICC48029.2020.9075939","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075939","url":null,"abstract":"A 180 GHz mixer-first phase-locked-loop based MSK receiver is demonstrated in 65-nm CMOS. Double balanced anti-parallel-diode-pair (APDP) based sub-harmonic mixer forms the phase detector. Compensation using multiple zeros reduces the effect of in-loop delay on the stability of PLL. Without external LO synchronization, the receiver achieves 10 Gbps with a BER < 10−12 at -24-dBm available input power. The open loop measurements show the down-conversion chain has a 3-dB bandwidth of approximately 48 GHz at 180 GHz and the minimum single side band (SSB) noise figure of 18.6 dB. This receiver is the self-synchronized receiver using coherent detection with the highest operating frequency in CMOS. This work also demonstrates that a PLL based receiver can support data rates in excess of 10 Gbps.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"561 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123106249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075918
N. M. Rahman, Edward Lee, Venkata Chaitanya Krishna Chekuri, Ashutosh Kumar Singh, S. Mukhopadhyay
A dual-mode PRINCE encryption cipher is implemented, in 65nm technology, that is configurable between pipelined and fully unrolled modes. Correlation Power and EM analysis on test-chip measurements show minimal exploitability of leakage from intermediate registers in pipelined mode. The pipelined PRINCE designs are seen to exhibit similar side channel resistance to unrolled designs while providing higher frequency and throughput. The overall dual-mode system has a minimum MTD of 460K and a projected maximum throughput of 492 Mega encryptions per second.
{"title":"A Configurable Dual-Mode PRINCE Cipher with Security Aware Pipelining in 65nm for High Throughput Applications","authors":"N. M. Rahman, Edward Lee, Venkata Chaitanya Krishna Chekuri, Ashutosh Kumar Singh, S. Mukhopadhyay","doi":"10.1109/CICC48029.2020.9075918","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075918","url":null,"abstract":"A dual-mode PRINCE encryption cipher is implemented, in 65nm technology, that is configurable between pipelined and fully unrolled modes. Correlation Power and EM analysis on test-chip measurements show minimal exploitability of leakage from intermediate registers in pipelined mode. The pipelined PRINCE designs are seen to exhibit similar side channel resistance to unrolled designs while providing higher frequency and throughput. The overall dual-mode system has a minimum MTD of 460K and a projected maximum throughput of 492 Mega encryptions per second.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131013976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075910
Yijie Wei, Qiankai Cao, Jie Gu, Kofi Otseidu, L. Hargrove
An ultra-low-power gesture and gait classification SoC is presented for rehabilitation application featuring (1) mixed-signal feature extraction and integrated low-noise amplifier eliminating expensive ADC and digital feature extraction, (2) an integrated distributed deep neural network (DNN) ASIC supporting a scalable multi-chip neural network for sensor fusion with distortion resiliency for low-cost front end modules, (3) onchip learning of DNN engine allowing in-situ training of user specific operations. A 12-channel 65nm CMOS test chip was fabricated with 1μW power per channel, less than 3ms computation latency, on-chip training for user-specific DNN model and multi-chip networking capability.
{"title":"A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training","authors":"Yijie Wei, Qiankai Cao, Jie Gu, Kofi Otseidu, L. Hargrove","doi":"10.1109/CICC48029.2020.9075910","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075910","url":null,"abstract":"An ultra-low-power gesture and gait classification SoC is presented for rehabilitation application featuring (1) mixed-signal feature extraction and integrated low-noise amplifier eliminating expensive ADC and digital feature extraction, (2) an integrated distributed deep neural network (DNN) ASIC supporting a scalable multi-chip neural network for sensor fusion with distortion resiliency for low-cost front end modules, (3) onchip learning of DNN engine allowing in-situ training of user specific operations. A 12-channel 65nm CMOS test chip was fabricated with 1μW power per channel, less than 3ms computation latency, on-chip training for user-specific DNN model and multi-chip networking capability.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128751118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075915
Baibhab Chatterjee, Shreyas Sen
Adaptive communication for Internet of Things (IoT) and Wireless Body Area Network (WBAN) technologies is becoming increasingly popular due to the large power-performance trade-offs and highly dynamic channel conditions. Path loss, low signal to noise ratio (SNR) in the channel and network congestion adversely affect the data communication, each of which can be taken care of using different strategies such as reducing the data rate (for reducing congestion), increasing the output power (for increased path loss) and application of error correction coding (ECC, for low SNR). In this paper, we present a digital-friendly Transceiver SoC consisting of an RF-DAC based transmitter with orthogonally tunable output power, data rate and ECC that enables optimum system level bit error rate (BER) and energy for over 3-orders of energy-performance scalability, along with an ultra-low-power OOK receiver that receives the transmitter's control bits from a nearby base station for closed-loop control. The data rate and ECC control is achieved through a digital baseband, while a tapped capacitor matching network controls the output power. The energy efficiency of the transmitter is 27.6pJ/b at 10MSps and at 0.8V supply (~9X improvement over state-of-the-art), while the entire SoC (Transmitter+OOK receiver for controller feedback) consumes only 41.5pJ/b.
{"title":"A 41.5 pJ/b, 2.4GHz Digital-Friendly Orthogonally Tunable Transceiver SoC with 3-decades of Energy-Performance Scalability","authors":"Baibhab Chatterjee, Shreyas Sen","doi":"10.1109/CICC48029.2020.9075915","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075915","url":null,"abstract":"Adaptive communication for Internet of Things (IoT) and Wireless Body Area Network (WBAN) technologies is becoming increasingly popular due to the large power-performance trade-offs and highly dynamic channel conditions. Path loss, low signal to noise ratio (SNR) in the channel and network congestion adversely affect the data communication, each of which can be taken care of using different strategies such as reducing the data rate (for reducing congestion), increasing the output power (for increased path loss) and application of error correction coding (ECC, for low SNR). In this paper, we present a digital-friendly Transceiver SoC consisting of an RF-DAC based transmitter with orthogonally tunable output power, data rate and ECC that enables optimum system level bit error rate (BER) and energy for over 3-orders of energy-performance scalability, along with an ultra-low-power OOK receiver that receives the transmitter's control bits from a nearby base station for closed-loop control. The data rate and ECC control is achieved through a digital baseband, while a tapped capacitor matching network controls the output power. The energy efficiency of the transmitter is 27.6pJ/b at 10MSps and at 0.8V supply (~9X improvement over state-of-the-art), while the entire SoC (Transmitter+OOK receiver for controller feedback) consumes only 41.5pJ/b.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124442519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075936
Yanqiao Li, Benjamin L. Dobbins, J. Stauth
This work presents an efficient high-voltage drive circuit for mm-scale electrostatic and piezoelectric microrobotic transducers. A reconfigurable series-parallel switched-capacitor (SC) DC-DC converter interfaces between either on-chip photovoltaic cells or a single off-chip battery, and a high-voltage MEMs actuator. The SC converter boosts a nominal -5-7.4V input by -16× to 80-117V. By charging the output sequentially and recovering charge in discharge cycles, the converter reduces power consumption by over 14×, compared to a conventional hard-switching driver. Measured results show effective operation with loads up to 20nF and operating frequency over 50kHz.
{"title":"An 80-117V Pseudo-Adiabatic Drive Circuit for Microrobotic Actuators with Optical Power Delivery and Peak Power Reduction Factor over 14×","authors":"Yanqiao Li, Benjamin L. Dobbins, J. Stauth","doi":"10.1109/CICC48029.2020.9075936","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075936","url":null,"abstract":"This work presents an efficient high-voltage drive circuit for mm-scale electrostatic and piezoelectric microrobotic transducers. A reconfigurable series-parallel switched-capacitor (SC) DC-DC converter interfaces between either on-chip photovoltaic cells or a single off-chip battery, and a high-voltage MEMs actuator. The SC converter boosts a nominal -5-7.4V input by -16× to 80-117V. By charging the output sequentially and recovering charge in discharge cycles, the converter reduces power consumption by over 14×, compared to a conventional hard-switching driver. Measured results show effective operation with loads up to 20nF and operating frequency over 50kHz.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121822894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075932
Tayebeh Yousefi, Mansour Taghadosi, Alireza Dabbaghian, Ryan Siu, Gerd Grau, Georg Zoidl, Hossein Kassiri
The design, development, and experimental validation of a mm-scale self-contained bidirectional optogenetic stimulator are presented. A novel current-mode LED driving circuit architecture is employed that allows for fully-linear control of optical stimulation up to ILED?10mA, with the smallest reported 200mV headroom, significantly boosting the electrical-to-optical energy conversion efficiency. The system's energy efficiency is further improved by inkjet printing of custom-designed optical µlenses on top of the device to enhance the generated light directivity. Our results show a 30.46× irradiance (optical power per area) improvement for the same electrical power consumption. In addition to the two stimulation channels, the SoC integrates two recording channels for LFP recording and digitization, and is powered through an on-chip coil with PTE?2.24%. Full experimental SoC electrical and optical characterization and in vitro measurement results are reported.
{"title":"A 12.5mg mm-Scale Inductively-Powered Light-Directivity-Enhanced Highly-Linear Bidirectional Optogenetic Neuro-Stimulator","authors":"Tayebeh Yousefi, Mansour Taghadosi, Alireza Dabbaghian, Ryan Siu, Gerd Grau, Georg Zoidl, Hossein Kassiri","doi":"10.1109/CICC48029.2020.9075932","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075932","url":null,"abstract":"The design, development, and experimental validation of a mm-scale self-contained bidirectional optogenetic stimulator are presented. A novel current-mode LED driving circuit architecture is employed that allows for fully-linear control of optical stimulation up to ILED?10mA, with the smallest reported 200mV headroom, significantly boosting the electrical-to-optical energy conversion efficiency. The system's energy efficiency is further improved by inkjet printing of custom-designed optical µlenses on top of the device to enhance the generated light directivity. Our results show a 30.46× irradiance (optical power per area) improvement for the same electrical power consumption. In addition to the two stimulation channels, the SoC integrates two recording channels for LFP recording and digitization, and is powered through an on-chip coil with PTE?2.24%. Full experimental SoC electrical and optical characterization and in vitro measurement results are reported.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"65 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01DOI: 10.1109/CICC48029.2020.9075940
Fangyu Mao, Yan Lu, E. Bonizzoni, F. Boera, Mo Huang, F. Maloberti, R. Martins
This paper presents a hybrid single-inductor bipolar-output (SIBO) DC-DC converter for active-matrix organic light-emitting diode (AMOLED) displays which are relatively more sensitive to the supply noises on their positive supply. This design significantly improves the display quality by achieving a near-zero voltage ripple at the positive output thanks to the negative output floating and the use of low-power shunt regulators. In addition, with the hybrid topology and the proposed cross-coupled bootstrap-based level-shifter with a dual-PMOS inverter buffer, low-voltage devices without deep-N-well are used, reducing the chip area and cost. The proposed converter is implemented in a 0.35-µm CMOS process with 5-V devices. The targeted output voltages are 5.3V and -4.7V. Operating at 1MHz, the measured positive output ripple is lower than 1mV in all the conditions. The measured peak power efficiency is 89.3% at 1.1W output power. The maximum output power is 3.5W.
{"title":"A Power-Efficient Hybrid Single-Inductor Bipolar-Output DC-DC Converter with Floating Negative Output for AMOLED Displays","authors":"Fangyu Mao, Yan Lu, E. Bonizzoni, F. Boera, Mo Huang, F. Maloberti, R. Martins","doi":"10.1109/CICC48029.2020.9075940","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075940","url":null,"abstract":"This paper presents a hybrid single-inductor bipolar-output (SIBO) DC-DC converter for active-matrix organic light-emitting diode (AMOLED) displays which are relatively more sensitive to the supply noises on their positive supply. This design significantly improves the display quality by achieving a near-zero voltage ripple at the positive output thanks to the negative output floating and the use of low-power shunt regulators. In addition, with the hybrid topology and the proposed cross-coupled bootstrap-based level-shifter with a dual-PMOS inverter buffer, low-voltage devices without deep-N-well are used, reducing the chip area and cost. The proposed converter is implemented in a 0.35-µm CMOS process with 5-V devices. The targeted output voltages are 5.3V and -4.7V. Operating at 1MHz, the measured positive output ripple is lower than 1mV in all the conditions. The measured peak power efficiency is 89.3% at 1.1W output power. The maximum output power is 3.5W.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130094614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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