Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067917
P. Das
The objective of this paper is to design a miniaturized and multiband MIMO antenna using slotting technique which can be used for many devices like cell phones, microwave radio relay. The MIMO antenna module consists of four micro strip antennas which are arranged in two MIMO antenna pairs. Reduction in size, multi-broadband, moderation in gain and good efficiency is obtained. The main aim is to reduce mutual coupling while optimizing the antenna size. The present work would be aimed at designing an antenna which is used mainly for wireless applications.
{"title":"Miniaturized dual band MIMO antennas for wireless application","authors":"P. Das","doi":"10.1109/ICNETS2.2017.8067917","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067917","url":null,"abstract":"The objective of this paper is to design a miniaturized and multiband MIMO antenna using slotting technique which can be used for many devices like cell phones, microwave radio relay. The MIMO antenna module consists of four micro strip antennas which are arranged in two MIMO antenna pairs. Reduction in size, multi-broadband, moderation in gain and good efficiency is obtained. The main aim is to reduce mutual coupling while optimizing the antenna size. The present work would be aimed at designing an antenna which is used mainly for wireless applications.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067947
S. Raajkumar, S. Muthulakshmi, A. Venkatesh
Electrical appliances that operate at high voltages require customized tests based on the appliance rating and insulation range to ensure the safety and wastage of current. This system will focus on a custom Virtual Instrumentation technique for testing key parameters and validating the machine based on its specifications/name plate details. Hardware section of this instrument will operate in tandem with a user configured Field Programmable Gate Array (FPGA) and provide documented results from LabVIEW about the health of the device under test. The Virtual Instrument used in this system is National Instrument Single-Board RIO (NI sbRIO) which provides real time limelight on unique feature of an application. This system focus on efficient usage of High Voltage for the specified applications, improves the time and reduces the complexity of system using the latest advancement in Virtual Instrumentation.
{"title":"FPGA based hand-held high voltage testing equipment","authors":"S. Raajkumar, S. Muthulakshmi, A. Venkatesh","doi":"10.1109/ICNETS2.2017.8067947","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067947","url":null,"abstract":"Electrical appliances that operate at high voltages require customized tests based on the appliance rating and insulation range to ensure the safety and wastage of current. This system will focus on a custom Virtual Instrumentation technique for testing key parameters and validating the machine based on its specifications/name plate details. Hardware section of this instrument will operate in tandem with a user configured Field Programmable Gate Array (FPGA) and provide documented results from LabVIEW about the health of the device under test. The Virtual Instrument used in this system is National Instrument Single-Board RIO (NI sbRIO) which provides real time limelight on unique feature of an application. This system focus on efficient usage of High Voltage for the specified applications, improves the time and reduces the complexity of system using the latest advancement in Virtual Instrumentation.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123367286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067949
Siva Kumar Akurati, A. Angeline, V. S. K. Bhaaskaran
Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True Single Phase Clocking (TSPC), Limited Switch Dynamic Logic (LSDL) and Pseudo Dynamic Buffer (PDB). The PDB structure reduces the dynamic power to a greater extent, without increase in the number of transistors. Findings: The design of Arithmetic and logical units using PDB is presented in the paper for validating the claim. Conclusion: This paper details the design of an ALU using PDB based domino methodology. The PDB based domino logic ALU demonstrates an average power 11.86 mw with a delay of 152.75 ps. Simulations are carried using Cadence® Virtuoso with 180nm technology library file.
{"title":"ALU design using Pseudo Dynamic Buffer based domino logic","authors":"Siva Kumar Akurati, A. Angeline, V. S. K. Bhaaskaran","doi":"10.1109/ICNETS2.2017.8067949","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067949","url":null,"abstract":"Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True Single Phase Clocking (TSPC), Limited Switch Dynamic Logic (LSDL) and Pseudo Dynamic Buffer (PDB). The PDB structure reduces the dynamic power to a greater extent, without increase in the number of transistors. Findings: The design of Arithmetic and logical units using PDB is presented in the paper for validating the claim. Conclusion: This paper details the design of an ALU using PDB based domino methodology. The PDB based domino logic ALU demonstrates an average power 11.86 mw with a delay of 152.75 ps. Simulations are carried using Cadence® Virtuoso with 180nm technology library file.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116274800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067974
Prakhar D. Vyas, G. Kumar, Abhijit G. Raut, U. K. Kommuri
This Work Presents the design of two different antenna. First, a Microstrip patch antenna with different shapes of cut in slot is designed. In order to increase the bandwidth and to obtain Dual polarization power divider having 50, 70 and 100 Ohm transmission line is fed in vertical and horizontal direction to the designed antenna. Second, a Serpinski Gasket antenna is designed for a working bandwidth of 5.1–5.8 Ghz A comparison is done between a antenna properties like frequency, return loss and gain of the two designed antennas.
{"title":"Design of miniaturized dual polarized MIMO antenna","authors":"Prakhar D. Vyas, G. Kumar, Abhijit G. Raut, U. K. Kommuri","doi":"10.1109/ICNETS2.2017.8067974","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067974","url":null,"abstract":"This Work Presents the design of two different antenna. First, a Microstrip patch antenna with different shapes of cut in slot is designed. In order to increase the bandwidth and to obtain Dual polarization power divider having 50, 70 and 100 Ohm transmission line is fed in vertical and horizontal direction to the designed antenna. Second, a Serpinski Gasket antenna is designed for a working bandwidth of 5.1–5.8 Ghz A comparison is done between a antenna properties like frequency, return loss and gain of the two designed antennas.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125738898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067908
N. Haider, K. Misra
TiO2 nanoparticles are prepared by sol-gel method. As revealed by X-ray diffraction (XRD) spectra the nanoparticles change their phase from anatase to rutile when the annealing temperature goes beyond 650°C. W-H plot for the powder samples annealed at 450°C and 750°C shows the presence of tensile strain in them which affects the particle size. The difference in particle sizes obtained from Debye-Scherer formula and W-H plot is seen to reduce for lesser strain value. The field emission scanning electron microscope (FESEM) images are observed to depict the agglomerated clusters of the particles whose average size favors the XRD results. The absorption is seen to show a red shift, as annealing temperature is raised.
{"title":"Effect of annealing on sol-gel derived TiO2 nanoparticles in acidic medium","authors":"N. Haider, K. Misra","doi":"10.1109/ICNETS2.2017.8067908","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067908","url":null,"abstract":"TiO2 nanoparticles are prepared by sol-gel method. As revealed by X-ray diffraction (XRD) spectra the nanoparticles change their phase from anatase to rutile when the annealing temperature goes beyond 650°C. W-H plot for the powder samples annealed at 450°C and 750°C shows the presence of tensile strain in them which affects the particle size. The difference in particle sizes obtained from Debye-Scherer formula and W-H plot is seen to reduce for lesser strain value. The field emission scanning electron microscope (FESEM) images are observed to depict the agglomerated clusters of the particles whose average size favors the XRD results. The absorption is seen to show a red shift, as annealing temperature is raised.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134012942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067925
V. M. Shobana, R. Srinivasan, V. Vaithianathan, K. K. Nagarajan
Semiconductor industry has explored various novel device structures to extend CMOS scaling. Circular geometry devices have been recently proposed to improve immunity to short channel effects without compromising planarity. In this work, one such circular geometry device called RingFET is considered and its performance enhancement through Lightly Doped Drain (LDD) implantation is sought using 3D TCAD simulations. RingFET has a circular gate geometry, which has better short channel immunity compared to conventional MOSFET structure mainly because of the elimination of side interface regions, that gives rise to trap induced leakages. This reduces the OFF current consequently, making RingFET better in the short channel regime. RingFET structure has a planar geometry but differs only lithographically with respect to MOSFET. This makes RingFET an interesting device to explore. The impact of LDD and its variants are studied with respect to DC and AC analysis using 3D TCAD simulations. The parameters under consideration are ON current, OFF current, Ion/Ioff ratio, sub-threshold swing (SS), transconductance (gm) and unity gain frequency (fT).
{"title":"Performance optimization of RingFET using LDD implantation","authors":"V. M. Shobana, R. Srinivasan, V. Vaithianathan, K. K. Nagarajan","doi":"10.1109/ICNETS2.2017.8067925","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067925","url":null,"abstract":"Semiconductor industry has explored various novel device structures to extend CMOS scaling. Circular geometry devices have been recently proposed to improve immunity to short channel effects without compromising planarity. In this work, one such circular geometry device called RingFET is considered and its performance enhancement through Lightly Doped Drain (LDD) implantation is sought using 3D TCAD simulations. RingFET has a circular gate geometry, which has better short channel immunity compared to conventional MOSFET structure mainly because of the elimination of side interface regions, that gives rise to trap induced leakages. This reduces the OFF current consequently, making RingFET better in the short channel regime. RingFET structure has a planar geometry but differs only lithographically with respect to MOSFET. This makes RingFET an interesting device to explore. The impact of LDD and its variants are studied with respect to DC and AC analysis using 3D TCAD simulations. The parameters under consideration are ON current, OFF current, Ion/Ioff ratio, sub-threshold swing (SS), transconductance (gm) and unity gain frequency (fT).","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132607049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067942
A. Reddy, A. M. Marks, S. Prabaharan, S. Muthulakshmi
Objectives: Post hospitalization care of a patient treated for critical illness, for instance cardiac arrest has been regarded as imperative. Nevertheless, it has become inevitable to skip follow-ups by the patients themselves. Method: This paper aims at designing a system which continuously monitors the health of the patient despite the patient being busy with his routine. An application is developed on android platform combined with Internet of Things (IoT) and sensor devices. Health of patient will be monitored by sensors and data from sensors will be sent to cloud which can be accessed anytime by the doctor and/or caretaker both in the cloud and application for necessary follow-ups in real time. Findings: In order to find the health of a patient more parameters are needed. But the main parameter for identifying the health of a patient are heart rate and temperatures. More parameters can be added to the system developed. Improvements/Applications: More sensors can be added to the system and the system has many application scenarios such as family health care.
{"title":"IoT augmented health monitoring system","authors":"A. Reddy, A. M. Marks, S. Prabaharan, S. Muthulakshmi","doi":"10.1109/ICNETS2.2017.8067942","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067942","url":null,"abstract":"Objectives: Post hospitalization care of a patient treated for critical illness, for instance cardiac arrest has been regarded as imperative. Nevertheless, it has become inevitable to skip follow-ups by the patients themselves. Method: This paper aims at designing a system which continuously monitors the health of the patient despite the patient being busy with his routine. An application is developed on android platform combined with Internet of Things (IoT) and sensor devices. Health of patient will be monitored by sensors and data from sensors will be sent to cloud which can be accessed anytime by the doctor and/or caretaker both in the cloud and application for necessary follow-ups in real time. Findings: In order to find the health of a patient more parameters are needed. But the main parameter for identifying the health of a patient are heart rate and temperatures. More parameters can be added to the system developed. Improvements/Applications: More sensors can be added to the system and the system has many application scenarios such as family health care.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114904215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067904
Murshed Ali Naskar, Maruti Tamrakar, D. Thiripurasundari
This paper represents a new technique to achieve a wideband rejection between 5.15 GHz to 5.85 GHz using a compact metamaterial structure. Metamaterials are narrowband resonator, which has bandwidth of 3% approx., but under this paper the novelty lies in incorporating a ‘V’ shaped metamaterial structure to achieve a fractional bandwidth of 13.17% within nominal space. Single ‘V’ shaped resonator has been simulated in full wave simulator and substantiated for permeability (μ), permittivity (□) and refractive index (n) values using Matlab code. The order of the resonator is increased upto 4 to achieve better rejection bandwidth and rejection level. The resonator and its complementary have been simulated along with a transmission line. The simulation result shows that the proposed 4th order ‘V’ shaped complementary resonator has better response and provides a wideband rejection from 5.15–5.85 GHz (WLAN Band) below −10dB for a dimension of 9×9 mm2.
{"title":"Compact ‘V’ shaped metamaterial based resonator for wide band rejection","authors":"Murshed Ali Naskar, Maruti Tamrakar, D. Thiripurasundari","doi":"10.1109/ICNETS2.2017.8067904","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067904","url":null,"abstract":"This paper represents a new technique to achieve a wideband rejection between 5.15 GHz to 5.85 GHz using a compact metamaterial structure. Metamaterials are narrowband resonator, which has bandwidth of 3% approx., but under this paper the novelty lies in incorporating a ‘V’ shaped metamaterial structure to achieve a fractional bandwidth of 13.17% within nominal space. Single ‘V’ shaped resonator has been simulated in full wave simulator and substantiated for permeability (μ), permittivity (□) and refractive index (n) values using Matlab code. The order of the resonator is increased upto 4 to achieve better rejection bandwidth and rejection level. The resonator and its complementary have been simulated along with a transmission line. The simulation result shows that the proposed 4th order ‘V’ shaped complementary resonator has better response and provides a wideband rejection from 5.15–5.85 GHz (WLAN Band) below −10dB for a dimension of 9×9 mm2.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121911318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067970
A. Saxena, R. Prakash
The exponential increase in the utilization of smart devices at consumer level as well as industrial grade level, the need to serve hundreds of sensors for effective computerization is of incredible conspicuousness in the field of M2M. HTTP convention was surely understood for remote checking, examination of information from extensive number of sensing components. There are some disadvantages of HTTP protocol like high consumption of bandwidth, more power requirement and lesser efficiency [1]. The different protocol like MQTT, AMQP and COAP are uses low bandwidth and capable of working in a network constraint situations in order to increase efficiency of embedded devices [2]. In this proposed model MQTT protocol has been used which is an IoT protocols used as a advancement to previous controlling methods. Brushless DC (BLDC) motors are replacing traditional brushed DC motors due to higher reliability, higher efficiency (about 50%) and lower noise. The efficient BLDC control solution for industrial IoT (Internet of Things) is proposed based on the industrial grade requirements, designed for low to high voltage operation. As the era of connecting the devices with the cloud is being increasing gradually, the proposed method uses an IoT protocol for monitoring as well as controlling over the motor. The proposed method provides us the control over motor rotation speed, forward & reverse rotation and failure detection like commutation error, over current and over voltage.
{"title":"Universal BLDC controller — With IIoT set of features","authors":"A. Saxena, R. Prakash","doi":"10.1109/ICNETS2.2017.8067970","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067970","url":null,"abstract":"The exponential increase in the utilization of smart devices at consumer level as well as industrial grade level, the need to serve hundreds of sensors for effective computerization is of incredible conspicuousness in the field of M2M. HTTP convention was surely understood for remote checking, examination of information from extensive number of sensing components. There are some disadvantages of HTTP protocol like high consumption of bandwidth, more power requirement and lesser efficiency [1]. The different protocol like MQTT, AMQP and COAP are uses low bandwidth and capable of working in a network constraint situations in order to increase efficiency of embedded devices [2]. In this proposed model MQTT protocol has been used which is an IoT protocols used as a advancement to previous controlling methods. Brushless DC (BLDC) motors are replacing traditional brushed DC motors due to higher reliability, higher efficiency (about 50%) and lower noise. The efficient BLDC control solution for industrial IoT (Internet of Things) is proposed based on the industrial grade requirements, designed for low to high voltage operation. As the era of connecting the devices with the cloud is being increasing gradually, the proposed method uses an IoT protocol for monitoring as well as controlling over the motor. The proposed method provides us the control over motor rotation speed, forward & reverse rotation and failure detection like commutation error, over current and over voltage.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124057487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067910
Ashish K. Sharma, V. Ravi
SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %.
SRAM是目前世界上应用广泛的高速缓存存储器。实现具有最高稳定性的低功耗SRAM是迫切需要的。多年来，对快速低功耗器件的需求不断增加。在本文中，第一部分描述了ADM (extract from N-Curve)的稳定性分析。然后给出泄漏功率的信息。提出了一种低功耗、高稳定性的8T SRAM电路。这篇论文承诺减少66%的电力。细胞的稳定性也有所提高，即WNM提高了15.9%;惩罚是人民币贬值7.9%。
{"title":"A novel method for design and implementation of low power, high stable SRAM cell","authors":"Ashish K. Sharma, V. Ravi","doi":"10.1109/ICNETS2.2017.8067910","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067910","url":null,"abstract":"SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"11 suppl_1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128424818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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