Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067977
S. Prabaharan, Satyajeet Sahoo, S. K. Mishra
Memristor (the so called Resistive Random Access Memory (Re-RAM), is an emerging next generation non-volatile memory, which shows promise towards achieving faster operation speed and also various advantages such as non-volatility, low power consumption, most importantly lesser density and latency. It can store information and can also switch between different states. It is a two terminal device. This type of memories would not lose its data even when the power is switched off. Recently Memristor's applications lie even in complex and interesting areas like Artificial Intelligence. Memristor's can be used to model human brain since its properties is more similar to synapses. Therefore with the help of synapse as Memristor and neurons as a CMOS control circuit, the entire brain can be modeled and fabricated on a single chip. Memristor can replace the power consuming transistors which can be productive in creating a logic circuit. This allows flexibility in using a circuit both for storage purpose and logical operations simultaneously. Memories are usually designed based on the crossbar architecture, where a single switching cell (1Memristor in our case) is placed at the cross-points of word line and bit line. The main finding of this work is that, when this model is applied to a crossbar structure, there is no resistance change except the desired one because of its voltage control nature in comparison to other models. As a result we are avoiding the undesired current the so called sneak current along with reducing the circuit elements i.e. the technique involved in a complete arrest of sneak path current like complementary resistive switching or connecting a diode for each cell as in other models (Linear ion Drift model, TEAM model) for memory operation. The reduction in circuit elements has helped in enhancing the density, making the design less complex and reduction in die area.
{"title":"Memristor augmented ReRAM cell for cross-bar memory architecture","authors":"S. Prabaharan, Satyajeet Sahoo, S. K. Mishra","doi":"10.1109/ICNETS2.2017.8067977","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067977","url":null,"abstract":"Memristor (the so called Resistive Random Access Memory (Re-RAM), is an emerging next generation non-volatile memory, which shows promise towards achieving faster operation speed and also various advantages such as non-volatility, low power consumption, most importantly lesser density and latency. It can store information and can also switch between different states. It is a two terminal device. This type of memories would not lose its data even when the power is switched off. Recently Memristor's applications lie even in complex and interesting areas like Artificial Intelligence. Memristor's can be used to model human brain since its properties is more similar to synapses. Therefore with the help of synapse as Memristor and neurons as a CMOS control circuit, the entire brain can be modeled and fabricated on a single chip. Memristor can replace the power consuming transistors which can be productive in creating a logic circuit. This allows flexibility in using a circuit both for storage purpose and logical operations simultaneously. Memories are usually designed based on the crossbar architecture, where a single switching cell (1Memristor in our case) is placed at the cross-points of word line and bit line. The main finding of this work is that, when this model is applied to a crossbar structure, there is no resistance change except the desired one because of its voltage control nature in comparison to other models. As a result we are avoiding the undesired current the so called sneak current along with reducing the circuit elements i.e. the technique involved in a complete arrest of sneak path current like complementary resistive switching or connecting a diode for each cell as in other models (Linear ion Drift model, TEAM model) for memory operation. The reduction in circuit elements has helped in enhancing the density, making the design less complex and reduction in die area.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132424829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067954
Subhani Shaik, R. P. Dwivedi
Circularly polarized antennas are used mostly due to the advantages over linearly polarized antennas like Mis-alignment and cross-polarization etc. In this paper, a high gain stacked patch antenna is proposed in this two patches are arranging one above the other in a single substrate to achieve dual band characteristics for high gain frequency selective surface has been used. The proposed antenna operates at band of 2.4 GHz for the application of WLAN, second antenna operates at two bands one is 2.2GHz and other at 3.6GHz. Simulation results evaluated in term of return loss, bandwidth, radiation pattern, directivity, gain and axial ratio. Gain of the antennas is 3.28 dB for trimmed square patch and 2.4 dB for inset feed antenna and 2.8 dB for centre feed antenna. For proposed antenna gain is 8.9dB at 2.2GHz and 3.9dB at 3.6GHz. Circular polarization antennas are one such a kind to their applications in satellite communications, Navigation systems, and mobile communications, proposed antenna can be used in WLAN, Wi-MAX, WPAN and RFID applications. Center frequency can be optimized; further more gain and matching can be obtained by integrating active components like diode, transistor and FET etc.
{"title":"High gain stacked patch antenna with circular polarization for wireless applications","authors":"Subhani Shaik, R. P. Dwivedi","doi":"10.1109/ICNETS2.2017.8067954","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067954","url":null,"abstract":"Circularly polarized antennas are used mostly due to the advantages over linearly polarized antennas like Mis-alignment and cross-polarization etc. In this paper, a high gain stacked patch antenna is proposed in this two patches are arranging one above the other in a single substrate to achieve dual band characteristics for high gain frequency selective surface has been used. The proposed antenna operates at band of 2.4 GHz for the application of WLAN, second antenna operates at two bands one is 2.2GHz and other at 3.6GHz. Simulation results evaluated in term of return loss, bandwidth, radiation pattern, directivity, gain and axial ratio. Gain of the antennas is 3.28 dB for trimmed square patch and 2.4 dB for inset feed antenna and 2.8 dB for centre feed antenna. For proposed antenna gain is 8.9dB at 2.2GHz and 3.9dB at 3.6GHz. Circular polarization antennas are one such a kind to their applications in satellite communications, Navigation systems, and mobile communications, proposed antenna can be used in WLAN, Wi-MAX, WPAN and RFID applications. Center frequency can be optimized; further more gain and matching can be obtained by integrating active components like diode, transistor and FET etc.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130268151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067976
K. Rani, N. Shabana, P. Tanmayee, S. Loganathan, G. Velmathi
This project work involves trickle implantation observing framework for use in hospitals. The framework comprises of a drip infusion, sugar level observing gadgets and a monitoring screen. The mixture observing gadget utilizing a pressure sensor (MPX10GP) technology module can identify the trickle implantation rate and a vacant imbuement arrangement sack, and after that, this information is sent to the monitoring screen put at the medical caretaker's station by means of the radio frequency (nrf24L01). The monitoring screen gets the information from trickle implantation observing gadgets and after that shows graphically them. When pressure sensor value reaches the threshold value, control valve will close which stops immediately flow of fluid without any airflow in patient's vein. In this manner, the created framework can screen seriously the dribble implantation circumstance of the few patients at the medical caretakers' station.
{"title":"Smart drip infusion monitoring system for instant alert-through nRF24L01","authors":"K. Rani, N. Shabana, P. Tanmayee, S. Loganathan, G. Velmathi","doi":"10.1109/ICNETS2.2017.8067976","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067976","url":null,"abstract":"This project work involves trickle implantation observing framework for use in hospitals. The framework comprises of a drip infusion, sugar level observing gadgets and a monitoring screen. The mixture observing gadget utilizing a pressure sensor (MPX10GP) technology module can identify the trickle implantation rate and a vacant imbuement arrangement sack, and after that, this information is sent to the monitoring screen put at the medical caretaker's station by means of the radio frequency (nrf24L01). The monitoring screen gets the information from trickle implantation observing gadgets and after that shows graphically them. When pressure sensor value reaches the threshold value, control valve will close which stops immediately flow of fluid without any airflow in patient's vein. In this manner, the created framework can screen seriously the dribble implantation circumstance of the few patients at the medical caretakers' station.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126014366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067955
N. Kasiviswanathan, K. Srivatsan
A pair of 32 bit Gaussian Random Numbers (GRaNs) is generated. Box Muller (BM) transformation is widely used for generation of high quality Gaussian Random Numbers in hardware. The BM transformation is a direct method to convert random numbers into a Gaussian random numbers. For the generation of uniform random number skip-ahead linear feedback shift register (SA-LFSR) is used which is given as input to BM transformation. CORDIC algorithm is used for the hardware design of BM transformation. The SA-LFSR does not suffer from correlations since they skip n number of bits at every sample.
{"title":"An efficient hardware implementation of Gaussian random number generator","authors":"N. Kasiviswanathan, K. Srivatsan","doi":"10.1109/ICNETS2.2017.8067955","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067955","url":null,"abstract":"A pair of 32 bit Gaussian Random Numbers (GRaNs) is generated. Box Muller (BM) transformation is widely used for generation of high quality Gaussian Random Numbers in hardware. The BM transformation is a direct method to convert random numbers into a Gaussian random numbers. For the generation of uniform random number skip-ahead linear feedback shift register (SA-LFSR) is used which is given as input to BM transformation. CORDIC algorithm is used for the hardware design of BM transformation. The SA-LFSR does not suffer from correlations since they skip n number of bits at every sample.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121379799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067888
R. Indhu, J. Mercy, K. M. Shreemathi, S. Radha, S. Kirubaveni, B. S. Sreeja
Conventionally separation of bio-particle from blood is a long term process. Different methods are involved in separation of bio-particles. Bio-particles like bacteria, WBC, RBC are separated in a micro fluidic device by using pillars and applying different types of fields. In this paper, different shapes of pillars are analysed for efficient separation of bio-particles without applying different types of field, which pays way for the development of bio-particle separation filter. The overall length of the channel is 1cm and the size of the pillars is 12×15×8 μm.
{"title":"Separation of bio-particles in micro fluidic device","authors":"R. Indhu, J. Mercy, K. M. Shreemathi, S. Radha, S. Kirubaveni, B. S. Sreeja","doi":"10.1109/ICNETS2.2017.8067888","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067888","url":null,"abstract":"Conventionally separation of bio-particle from blood is a long term process. Different methods are involved in separation of bio-particles. Bio-particles like bacteria, WBC, RBC are separated in a micro fluidic device by using pillars and applying different types of fields. In this paper, different shapes of pillars are analysed for efficient separation of bio-particles without applying different types of field, which pays way for the development of bio-particle separation filter. The overall length of the channel is 1cm and the size of the pillars is 12×15×8 μm.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"128 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114038401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067938
Nitesh Yerma, K. Suganthi
This paper presents the design and simulation of a narrow band Low Noise Amplifier (LNA) based on 180nm CMOS technology. This LNA consists of 2-stage design in which common source stage is followed by cascade stage. Different matching techniques is used at input, output and intermediate stage in the design to obtain the best result and to minimize the loss as much as possible. The LNA is designed for low power, high gain applications and it provides a series of good performance like noise figure, linearity, figure of merit (FOM) and power consumption. The proposed LNA is design and simulated using Agilent Advance design system in an 180nm CMOS technology and measurement results shows voltage gain of 38dB noise figure of 1.867 dB at 4 GHz frequency which is best suited for DBS application.
{"title":"Low noise amplifier at 4GHz frequency for DBS application","authors":"Nitesh Yerma, K. Suganthi","doi":"10.1109/ICNETS2.2017.8067938","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067938","url":null,"abstract":"This paper presents the design and simulation of a narrow band Low Noise Amplifier (LNA) based on 180nm CMOS technology. This LNA consists of 2-stage design in which common source stage is followed by cascade stage. Different matching techniques is used at input, output and intermediate stage in the design to obtain the best result and to minimize the loss as much as possible. The LNA is designed for low power, high gain applications and it provides a series of good performance like noise figure, linearity, figure of merit (FOM) and power consumption. The proposed LNA is design and simulated using Agilent Advance design system in an 180nm CMOS technology and measurement results shows voltage gain of 38dB noise figure of 1.867 dB at 4 GHz frequency which is best suited for DBS application.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125232607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067950
C. Sekhar, K. Kranthi, M. K. Chakravarthi
Background/Objectives: As the quantity of urban vehicles develops rapidly comes about development of traffic, the deregulation of traffic signs has turned into a common sympathy toward all police furthermore it prompts the mishaps close to the activity signals. Lately the halting of vehicle is finished with the assistance of the GSM module and by versatile Apps by sending a control sign to the vehicle and stops the vehicle. These frameworks are very little effective in light of the fact that the scope of the sign is so less and the sign send by the GSM module relies on upon the signal to the GSM module. Methods/Statistical analysis: Our exploration introduces a straightforward, proficient and propelled framework for ending of vehicles with the help Internet of things (IoT). The system happens in a way that the individual who deregulates the activity flags his/her vehicle enlistment number is entered into the database manually, then an exceptional code which is as of now present in the database is sent to the vehicle through the IOT and it ends the vehicle by blocking the throttle valve, the correspondence process happened in this procedure is Internet to vehicle (I to V). Findings: This system makes straightforward catch of persons who deregulates the traffic signals and also sends the area of vehicle (where it is halted) with the assistance of GPS module for taking after (Where the vehicle is stopped). Improvements/Applications: The present work can be developed with the integration of a mobile application interface. It would serve many automotive safety needs if launched along with the CAN and LIN bus technologies.
{"title":"Traffic signal breach vehicle stop system using IOT","authors":"C. Sekhar, K. Kranthi, M. K. Chakravarthi","doi":"10.1109/ICNETS2.2017.8067950","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067950","url":null,"abstract":"Background/Objectives: As the quantity of urban vehicles develops rapidly comes about development of traffic, the deregulation of traffic signs has turned into a common sympathy toward all police furthermore it prompts the mishaps close to the activity signals. Lately the halting of vehicle is finished with the assistance of the GSM module and by versatile Apps by sending a control sign to the vehicle and stops the vehicle. These frameworks are very little effective in light of the fact that the scope of the sign is so less and the sign send by the GSM module relies on upon the signal to the GSM module. Methods/Statistical analysis: Our exploration introduces a straightforward, proficient and propelled framework for ending of vehicles with the help Internet of things (IoT). The system happens in a way that the individual who deregulates the activity flags his/her vehicle enlistment number is entered into the database manually, then an exceptional code which is as of now present in the database is sent to the vehicle through the IOT and it ends the vehicle by blocking the throttle valve, the correspondence process happened in this procedure is Internet to vehicle (I to V). Findings: This system makes straightforward catch of persons who deregulates the traffic signals and also sends the area of vehicle (where it is halted) with the assistance of GPS module for taking after (Where the vehicle is stopped). Improvements/Applications: The present work can be developed with the integration of a mobile application interface. It would serve many automotive safety needs if launched along with the CAN and LIN bus technologies.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067940
Oindrila Pal, K. Paldurai
In the recent times we see that the digital signal processing applications are increasingly becoming complex which leads to the extensive using of the floating point numbers in the hardware processing implementations. In this paper, we will focus on the various advantages the HUB technique has when implemented on FPGA applications. The one advantage which the HUB floating point technique has that it helps in eliminating the rounding logic on the arithmetic units. In this we have discussed using the adders and the multipliers. The experimental procedure shows that the HUB technique and the corresponding arithmetic unit have the same accuracy level when compared with the standard format. Whereas, after the implementation is being done it reveals that the HUB technique is better as it has improved speed, area and power consumption. However, for some particular sizes HUB multipliers require lot more resources than the one used in standard format.
{"title":"FPGA implementation of DSP applications using HUB floating point technique","authors":"Oindrila Pal, K. Paldurai","doi":"10.1109/ICNETS2.2017.8067940","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067940","url":null,"abstract":"In the recent times we see that the digital signal processing applications are increasingly becoming complex which leads to the extensive using of the floating point numbers in the hardware processing implementations. In this paper, we will focus on the various advantages the HUB technique has when implemented on FPGA applications. The one advantage which the HUB floating point technique has that it helps in eliminating the rounding logic on the arithmetic units. In this we have discussed using the adders and the multipliers. The experimental procedure shows that the HUB technique and the corresponding arithmetic unit have the same accuracy level when compared with the standard format. Whereas, after the implementation is being done it reveals that the HUB technique is better as it has improved speed, area and power consumption. However, for some particular sizes HUB multipliers require lot more resources than the one used in standard format.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134395920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067964
Ameya Chandras, V. S. K. Bhaaskaran
Background/Objective: The memory system occupy a significantly larger area of the SoCs (System on Chip) and it also contributes heavily to the increasing power consumption. The major part of the power consumption is due to the peripheral circuits of the memory systems, with the sense amplifier playing a dominant role, while the memory is accessed for the reading operation. This paper presents a modification of the conventional 6T SRAM cell into the 8T SRAM (Static Random Access Memory) cell memory architecture, focusing on enhancing the writing and reading stability of the memory cell with an additional advantage of providing a separate path for reading the data. Statistical Analysis/Method: To enhance the sensing performance, various sensing schemes such as the domino sensing scheme, AC Coupled sensing scheme and Switching pMOS sense amplifier have been employed. The above mentioned sensing schemes use single bit line for sensing the data. These single ended sensing schemes are implemented and simulated on industry standard Cadence EDA tool using 45nm technology. These are employed for sensing the data from the SRAM banks comprising 8T SRAM cells. Findings: The simulation results show that the power consumption during sensing operation is reduced as compared to traditional sense amplifier due to the advantage of single ended bit line sensing. Conclusion: The investigation and comparison among the three single ended sensing schemes reveals that the switching pMOS sense amplifier exhibits better performance with considerable amount of reduction in sensing power.
{"title":"Sensing schemes of sense amplifier for single-ended SRAM","authors":"Ameya Chandras, V. S. K. Bhaaskaran","doi":"10.1109/ICNETS2.2017.8067964","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067964","url":null,"abstract":"Background/Objective: The memory system occupy a significantly larger area of the SoCs (System on Chip) and it also contributes heavily to the increasing power consumption. The major part of the power consumption is due to the peripheral circuits of the memory systems, with the sense amplifier playing a dominant role, while the memory is accessed for the reading operation. This paper presents a modification of the conventional 6T SRAM cell into the 8T SRAM (Static Random Access Memory) cell memory architecture, focusing on enhancing the writing and reading stability of the memory cell with an additional advantage of providing a separate path for reading the data. Statistical Analysis/Method: To enhance the sensing performance, various sensing schemes such as the domino sensing scheme, AC Coupled sensing scheme and Switching pMOS sense amplifier have been employed. The above mentioned sensing schemes use single bit line for sensing the data. These single ended sensing schemes are implemented and simulated on industry standard Cadence EDA tool using 45nm technology. These are employed for sensing the data from the SRAM banks comprising 8T SRAM cells. Findings: The simulation results show that the power consumption during sensing operation is reduced as compared to traditional sense amplifier due to the advantage of single ended bit line sensing. Conclusion: The investigation and comparison among the three single ended sensing schemes reveals that the switching pMOS sense amplifier exhibits better performance with considerable amount of reduction in sensing power.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114391060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067948
Chintalapudi Satish Kumar, A. Prathiba, V. Bhaskaran
Cryptography is the art of realizing security by the strength of mathematics involved in the security algorithm, the security is compromised by the mathematics of cryptanalysis using the side channel attacks. Differential power analysis (DPA) is the most effective form of side channel power analysis, which analyses the power consumption of the cryptographic device statistically and reveals the secret information. This paper investigates the implementation of the S-BOX with the DPA resistant logical style, namely, the Three Phase Dual rail Pre-charge logic (TDPL) which makes the power consumption of the device insensitive to intermediate values. To make the power consumption constant an additional phase is added in addition to the pre-charge and evaluation phases of the three phase dual rail logic. In this paper, the implementation of the S-BOX is carried out in both the static CMOS logic and the TDPL logic to compare their DPA resistance. It is proved that the static CMOS logic is more vulnerable to power analysis than the considered three phase logic. The correlation analysis is performed to estimate the property of the DPA resistance of the S-box implementation.
{"title":"DPA resistance analysis of the cryptographic S-box implementation in static CMOS and TDPL logic style","authors":"Chintalapudi Satish Kumar, A. Prathiba, V. Bhaskaran","doi":"10.1109/ICNETS2.2017.8067948","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067948","url":null,"abstract":"Cryptography is the art of realizing security by the strength of mathematics involved in the security algorithm, the security is compromised by the mathematics of cryptanalysis using the side channel attacks. Differential power analysis (DPA) is the most effective form of side channel power analysis, which analyses the power consumption of the cryptographic device statistically and reveals the secret information. This paper investigates the implementation of the S-BOX with the DPA resistant logical style, namely, the Three Phase Dual rail Pre-charge logic (TDPL) which makes the power consumption of the device insensitive to intermediate values. To make the power consumption constant an additional phase is added in addition to the pre-charge and evaluation phases of the three phase dual rail logic. In this paper, the implementation of the S-BOX is carried out in both the static CMOS logic and the TDPL logic to compare their DPA resistance. It is proved that the static CMOS logic is more vulnerable to power analysis than the considered three phase logic. The correlation analysis is performed to estimate the property of the DPA resistance of the S-box implementation.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122594299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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