Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067891
S. Baudha, Shailendra Kumar Dhakad
This paper introduces detailed information about a miniaturized compact super broadband printed antenna. The antenna consists of a semicircular patch, microstrip line and a partial ground plane, which is fabricated on a low cost, commercially available FR4 substrate. The overall size of the dielectric substrate is 38 × 43 × 1.5 cubic millimeter. This simple structure of the antenna has an impedance bandwidth of 1.9 to above 100 GHz. The higher operating bandwidth is achieved due to the semicircular radiating patch. The peak gain of the proposed antenna is 8.5 dB, whereas the maximum radiation efficiency is 0.75 dB. The antenna is suitable for research, military and commercial applications. The impedance bandwidth of the antenna covers applications such as 5.2/5.8 GHz WLAN bands, 5.5 GHz WiMAX bands, X band (8–12 GHz), Ku band (12–18 GHz), Ka band (26.5–40 GHz), U band (40–60 GHz), V band (50–75 GHz), W band (75–100 GHz), space and satellite communication services. Details about the gain, radiation efficiency, radiation pattern and surface current are being described in this paper.
{"title":"Miniaturized compact super broadband printed monopole antenna","authors":"S. Baudha, Shailendra Kumar Dhakad","doi":"10.1109/ICNETS2.2017.8067891","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067891","url":null,"abstract":"This paper introduces detailed information about a miniaturized compact super broadband printed antenna. The antenna consists of a semicircular patch, microstrip line and a partial ground plane, which is fabricated on a low cost, commercially available FR4 substrate. The overall size of the dielectric substrate is 38 × 43 × 1.5 cubic millimeter. This simple structure of the antenna has an impedance bandwidth of 1.9 to above 100 GHz. The higher operating bandwidth is achieved due to the semicircular radiating patch. The peak gain of the proposed antenna is 8.5 dB, whereas the maximum radiation efficiency is 0.75 dB. The antenna is suitable for research, military and commercial applications. The impedance bandwidth of the antenna covers applications such as 5.2/5.8 GHz WLAN bands, 5.5 GHz WiMAX bands, X band (8–12 GHz), Ku band (12–18 GHz), Ka band (26.5–40 GHz), U band (40–60 GHz), V band (50–75 GHz), W band (75–100 GHz), space and satellite communication services. Details about the gain, radiation efficiency, radiation pattern and surface current are being described in this paper.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131904377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067969
N. Yamini, P. Sasipriya, V. S. K. Bhaaskaran
Background/Objective: Energy recovery is one of the most promising methods for low power design methodologies. The main idea behind the energy recovery circuits is the use of a slowly rising and slowly falling AC power supply i.e., sinusoidal or trapezoidal clock signal. Hence, it is essential to design low power clocking schemes for such energy recovery circuits. This paper presents an efficient clocking scheme for the energy recovery circuits. Methods/Statistical Analysis: The single phase sinusoidal clock signal which is used to operate the energy recovery circuits is generated from the 2N2P resonant clock generator. The sinusoidal clock signal is routed to the energy recovery circuits through the H-tree clock distribution network. Findings: Single phase energy recovery circuit, namely, the Glitch free and Cascadable Adiabatic Logic (GFCAL) is used to validate the clock network design. 16 inverters are cascaded and connected to the output nodes of the clock tree, and the cascaded chain is driven by the clock signal. Conclusion/Improvement: The simulation results show that the 16-bit adiabatic inverter chain operated at 2GHz incur a power consumption of 184.1 μWatts and the conventional CMOS inverter chain of 16-bit operated at the same frequency incurs power dissipation of 190.2μWatts. All the simulations have been carried out using the industry standard Cadence® Virtuoso tool using 180nm technology library files.
{"title":"Clock distribution network design for single phase energy recovery circuits","authors":"N. Yamini, P. Sasipriya, V. S. K. Bhaaskaran","doi":"10.1109/ICNETS2.2017.8067969","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067969","url":null,"abstract":"Background/Objective: Energy recovery is one of the most promising methods for low power design methodologies. The main idea behind the energy recovery circuits is the use of a slowly rising and slowly falling AC power supply i.e., sinusoidal or trapezoidal clock signal. Hence, it is essential to design low power clocking schemes for such energy recovery circuits. This paper presents an efficient clocking scheme for the energy recovery circuits. Methods/Statistical Analysis: The single phase sinusoidal clock signal which is used to operate the energy recovery circuits is generated from the 2N2P resonant clock generator. The sinusoidal clock signal is routed to the energy recovery circuits through the H-tree clock distribution network. Findings: Single phase energy recovery circuit, namely, the Glitch free and Cascadable Adiabatic Logic (GFCAL) is used to validate the clock network design. 16 inverters are cascaded and connected to the output nodes of the clock tree, and the cascaded chain is driven by the clock signal. Conclusion/Improvement: The simulation results show that the 16-bit adiabatic inverter chain operated at 2GHz incur a power consumption of 184.1 μWatts and the conventional CMOS inverter chain of 16-bit operated at the same frequency incurs power dissipation of 190.2μWatts. All the simulations have been carried out using the industry standard Cadence® Virtuoso tool using 180nm technology library files.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133610139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067975
C. SaiTeja, Vineeta Singh, K. Venkatesh, U. K. Kommuri
Micro-electro-mechanical frameworks (MEMS) Technology has risen as a key methodology for building low-misfortune stage shifters, which is crucial for cutting edge radar and correspondence frameworks. This MEMS innovation is utilized as a part of stage shifters, which are vital for advanced telecom, car, and protection applications. The principle idea here is to evacuate every single existent capacitance of an inductor, as it is in the planar conductor, including controllable capacitor in parallel with the unadulterated inductor to create no good disseminated coplanar waveguide stage shifter. The reverberation state of the additional controllable capacitors makes extensive variety of working zone to accomplish expansive stage moving per unit cell. Utilizing this technique the quantity of cells is diminished. Accordingly size and misfortune are diminished.
{"title":"Miniaturizing of RF MEMS DMTL phase shifter","authors":"C. SaiTeja, Vineeta Singh, K. Venkatesh, U. K. Kommuri","doi":"10.1109/ICNETS2.2017.8067975","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067975","url":null,"abstract":"Micro-electro-mechanical frameworks (MEMS) Technology has risen as a key methodology for building low-misfortune stage shifters, which is crucial for cutting edge radar and correspondence frameworks. This MEMS innovation is utilized as a part of stage shifters, which are vital for advanced telecom, car, and protection applications. The principle idea here is to evacuate every single existent capacitance of an inductor, as it is in the planar conductor, including controllable capacitor in parallel with the unadulterated inductor to create no good disseminated coplanar waveguide stage shifter. The reverberation state of the additional controllable capacitors makes extensive variety of working zone to accomplish expansive stage moving per unit cell. Utilizing this technique the quantity of cells is diminished. Accordingly size and misfortune are diminished.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127804176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067951
Shyamali Padhi, A. Angeline, V. S. K. Bhaaskaran
Background/Objectives: Domino logic designs are widely used owing to its high speed and less area. However, the on chip variation of the design becomes more severe on scaling down the technology nodes. Methods/Statistical analysis: This paper details the design of variation tolerant domino logic with novel keeper architecture which comprises of a stacked grounded keeper with a body-bias generator. Furthermore, this paper elaborates the process variation tolerance techniques and compares the proposed keeper style with the existing styles. The design and analysis are carried out on wide fan-in domino logic circuits using Cadence® Spectre and Monte Carlo simulations in ADE-XL environment Findings: The results demonstrate that the novel variation tolerant keeper has an advantage of less delay compared to the conventional keeper. Additionally, it offers lesser delay variability of 7.24% and 9.18% and power variability of 14.01% and 0.15% using 180nm and 45nm technology libraries. Improvements/Applications: The proposed architecture enables the domino logic circuits to be used in applications that require robust and fast processing.
{"title":"Design of process variation tolerant domino logic keeper architecture","authors":"Shyamali Padhi, A. Angeline, V. S. K. Bhaaskaran","doi":"10.1109/ICNETS2.2017.8067951","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067951","url":null,"abstract":"Background/Objectives: Domino logic designs are widely used owing to its high speed and less area. However, the on chip variation of the design becomes more severe on scaling down the technology nodes. Methods/Statistical analysis: This paper details the design of variation tolerant domino logic with novel keeper architecture which comprises of a stacked grounded keeper with a body-bias generator. Furthermore, this paper elaborates the process variation tolerance techniques and compares the proposed keeper style with the existing styles. The design and analysis are carried out on wide fan-in domino logic circuits using Cadence® Spectre and Monte Carlo simulations in ADE-XL environment Findings: The results demonstrate that the novel variation tolerant keeper has an advantage of less delay compared to the conventional keeper. Additionally, it offers lesser delay variability of 7.24% and 9.18% and power variability of 14.01% and 0.15% using 180nm and 45nm technology libraries. Improvements/Applications: The proposed architecture enables the domino logic circuits to be used in applications that require robust and fast processing.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129759048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067937
A. Arora, N. Kumar
The demand for today is to have a Compact and reduced size devices, hence requires reduced sized antenna. For reduced sized, array elements can be placed closer to each other. However, the problem of mutual coupling, depending on interelement separation and their relative orientation, becomes a challenge [3][4]. To overcome this, we proposed an EBG structured antenna. The most used characteristics of Electromagnetic Band Gap (EBG) structure are the surface wave suppression effect within its band gap. Hence, they can reduce the mutual coupling due to surface wave propagation [2][9][10]. EBG provides better compactness, easy integrated feature and 2-D band gap properties. Also, by using EBG structure, antenna array characteristics like total size and radiation efficiency can also be improvised [1].
{"title":"To reduce mutual coupling in microstrip patch antenna arrays elements using electromagnetic band gap structures for X-band","authors":"A. Arora, N. Kumar","doi":"10.1109/ICNETS2.2017.8067937","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067937","url":null,"abstract":"The demand for today is to have a Compact and reduced size devices, hence requires reduced sized antenna. For reduced sized, array elements can be placed closer to each other. However, the problem of mutual coupling, depending on interelement separation and their relative orientation, becomes a challenge [3][4]. To overcome this, we proposed an EBG structured antenna. The most used characteristics of Electromagnetic Band Gap (EBG) structure are the surface wave suppression effect within its band gap. Hence, they can reduce the mutual coupling due to surface wave propagation [2][9][10]. EBG provides better compactness, easy integrated feature and 2-D band gap properties. Also, by using EBG structure, antenna array characteristics like total size and radiation efficiency can also be improvised [1].","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128936208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067944
Elizabeth Kadiyala, Shravya Meda, Revathi Basani, S. Muthulakshmi
Objectives: With the fast increment in the quality of client of the internet over the previous decade has made the internet as a feature of the life and IoT is the most recent and developing innovation. Internet of Things (IoT) is developing systems of ordinary item from customer merchandise to mechanical machine that can share data and complete and while you are occupied with different exercises. This system is planned minimal effort and expandable permitting a variety of device to be monitored. In this project only sensors has been monitored for better result they has to be controlled wirelessly through IoT. Methods/Statistical analysis: All the sensors that are connected to the Atmega are sensing the values at different conditions and displaying the values in LCD as well as the values are stored in the cloud. Whenever there is a change in the measured parameter that changed values are being updated. This ensures the correctness of the system at every instant of time the values are automatically updated in the cloud. Findings: Global industrial process monitoring through IoT is a system that uses computer or mobile devices to monitor functions in industry. It is intended to spare electric force and human vitality. The sensors that can be checked are temperature, light intensity, water level, current and voltage. These sensors are associated with Atmega and interface with Raspberry pi and observed qualities are put away in cloud. The modern procedure monitoring system varied from other system by permitting the client to work the system from any place around the globe through internet association. The system will consequently change on the base of the sensors information. Application: Engineers and scientists around the world use embedded systems to prototype and diagnostics, monitoring, and control applications within a variety of demanding industry environments. Rugged and modular hardware provides the flexibility to meet your specific embedded system application needs today and in the future.
{"title":"Global industrial process monitoring through IoT using Raspberry pi","authors":"Elizabeth Kadiyala, Shravya Meda, Revathi Basani, S. Muthulakshmi","doi":"10.1109/ICNETS2.2017.8067944","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067944","url":null,"abstract":"Objectives: With the fast increment in the quality of client of the internet over the previous decade has made the internet as a feature of the life and IoT is the most recent and developing innovation. Internet of Things (IoT) is developing systems of ordinary item from customer merchandise to mechanical machine that can share data and complete and while you are occupied with different exercises. This system is planned minimal effort and expandable permitting a variety of device to be monitored. In this project only sensors has been monitored for better result they has to be controlled wirelessly through IoT. Methods/Statistical analysis: All the sensors that are connected to the Atmega are sensing the values at different conditions and displaying the values in LCD as well as the values are stored in the cloud. Whenever there is a change in the measured parameter that changed values are being updated. This ensures the correctness of the system at every instant of time the values are automatically updated in the cloud. Findings: Global industrial process monitoring through IoT is a system that uses computer or mobile devices to monitor functions in industry. It is intended to spare electric force and human vitality. The sensors that can be checked are temperature, light intensity, water level, current and voltage. These sensors are associated with Atmega and interface with Raspberry pi and observed qualities are put away in cloud. The modern procedure monitoring system varied from other system by permitting the client to work the system from any place around the globe through internet association. The system will consequently change on the base of the sensors information. Application: Engineers and scientists around the world use embedded systems to prototype and diagnostics, monitoring, and control applications within a variety of demanding industry environments. Rugged and modular hardware provides the flexibility to meet your specific embedded system application needs today and in the future.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123338167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067898
M. Raghavendra, H. S. Prasantha, S. Sandya
The astounding augmentation of multimedia in the fields of communication media, medicine, surveillance etc. resulted in the huge volume of data acquirement. The storage of these data requires massive memory. For communication, these data need enormous transmission bandwidth. The only solution to reduce the storage and the transmission bandwidth is the data compression. From the literature survey it is learnt that there is a need to achieve compression ratio greater than 30 with a PSNR greater than 25 dB for non critical applications. In order to facilitate this, a colour image compression method is proposed. In this method, the colour image is converted into the “YCbCr” format using formulated New Equation Set-1. The “Y” component matrix is divided into 16×16 blocks. The DCT is applied to all the 16×16 blocks. The DC-Coefficient of all 16×16 block DCT is taken out and zero is inserted in place of it. The data types of all the DC-coefficients are changed from the “double” to the “16 bit integer” data type and they are stored. The transformed matrix consists of 16×16 block DCT of all the blocks. In this matrix, all those elements less than the threshold value “th” are made zero. This matrix is decomposed into matrices “U”, “S” and “V” using SVD. All those elements of the matrix “U” less than the threshold value “thu”, all those elements of the matrix “S” less than the threshold value “ths” and all those elements of the matrix “V” less than the threshold value “thv” are made zero. Then these matrices are multiplied to form one matrix such that X=USVT. All those elements of the matrix “X” less than the threshold value “th” are made zero. Now all the elements of the matrix “X” are divided by 10. Then the matrix “X” becomes a sparse matrix. This sparse matrix is represented in the “triplet form”. The data types of the “row values” and the “column values” of the triplet form are converted from the “double” to the “16 bit integer” data type. The data type of the “data elements” of the “triplet form” is converted into the “8 bit integer” data type. Then the RLE is applied to the “column values” of the “triplet form”. After this, the compressed form of the Y-Component Matrix is obtained. Similarly, the “Cb” and the “Cr” component matrices are compressed. Then the experiments are conducted by converting the given image into the “YCbCr” format by the formulated New Equation Set-2, New Equation Set-3 and the basic “YCbCr” equation. The results are compared with parameters such as Compression Ratio, PSNR, SSIM and Quality Index. Experiments are conducted using MATLAB. From the results, it can be concluded that, the compression ratio obtained from the method which has got the colour conversion using New Equation Set-1 is good. The maximum compression ratio obtained with this method is 43.5079 with a PSNR of Red, Green and Blue Component equal to 25.9583 dB, 25.7501 dB and 26.4837 dB respectively.
{"title":"Colour image compression with colour conversion and hybrid algorithm","authors":"M. Raghavendra, H. S. Prasantha, S. Sandya","doi":"10.1109/ICNETS2.2017.8067898","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067898","url":null,"abstract":"The astounding augmentation of multimedia in the fields of communication media, medicine, surveillance etc. resulted in the huge volume of data acquirement. The storage of these data requires massive memory. For communication, these data need enormous transmission bandwidth. The only solution to reduce the storage and the transmission bandwidth is the data compression. From the literature survey it is learnt that there is a need to achieve compression ratio greater than 30 with a PSNR greater than 25 dB for non critical applications. In order to facilitate this, a colour image compression method is proposed. In this method, the colour image is converted into the “YCbCr” format using formulated New Equation Set-1. The “Y” component matrix is divided into 16×16 blocks. The DCT is applied to all the 16×16 blocks. The DC-Coefficient of all 16×16 block DCT is taken out and zero is inserted in place of it. The data types of all the DC-coefficients are changed from the “double” to the “16 bit integer” data type and they are stored. The transformed matrix consists of 16×16 block DCT of all the blocks. In this matrix, all those elements less than the threshold value “th” are made zero. This matrix is decomposed into matrices “U”, “S” and “V” using SVD. All those elements of the matrix “U” less than the threshold value “thu”, all those elements of the matrix “S” less than the threshold value “ths” and all those elements of the matrix “V” less than the threshold value “thv” are made zero. Then these matrices are multiplied to form one matrix such that X=USV<sup>T</sup>. All those elements of the matrix “X” less than the threshold value “th” are made zero. Now all the elements of the matrix “X” are divided by 10. Then the matrix “X” becomes a sparse matrix. This sparse matrix is represented in the “triplet form”. The data types of the “row values” and the “column values” of the triplet form are converted from the “double” to the “16 bit integer” data type. The data type of the “data elements” of the “triplet form” is converted into the “8 bit integer” data type. Then the RLE is applied to the “column values” of the “triplet form”. After this, the compressed form of the Y-Component Matrix is obtained. Similarly, the “Cb” and the “Cr” component matrices are compressed. Then the experiments are conducted by converting the given image into the “YCbCr” format by the formulated New Equation Set-2, New Equation Set-3 and the basic “YCbCr” equation. The results are compared with parameters such as Compression Ratio, PSNR, SSIM and Quality Index. Experiments are conducted using MATLAB. From the results, it can be concluded that, the compression ratio obtained from the method which has got the colour conversion using New Equation Set-1 is good. The maximum compression ratio obtained with this method is 43.5079 with a PSNR of Red, Green and Blue Component equal to 25.9583 dB, 25.7501 dB and 26.4837 dB respectively.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127899211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067961
Siddharth Saxena, C. Hemanth, R. Sangeetha
Objectives: Electroencephalogram (EEG) plays an important role in recording the activity of human brain. Identification of epileptic seizures can be done using EEG signals. Methods/ Statistical Analysis: In this work for classification of EEG signals a method known as Empirical mode decomposition (EMD) is used and compared with empirical wavelet transform (EWT) based method. Findings: In this paper the EMD has been considered for five classes of EEG signals. Intrinsic Mode functions obtained for these EEG signals have been shown. The amplitude modulation bandwidth BAM and frequency modulation bandwidth BFM have been calculated. Applications/ Improvements: The classification based on bandwidth features and least square support vector machine (LS-SVM) provided better categorization accuracy than earlier adopted methods. Results have been shown in this report.
{"title":"Classification of normal, seizure and seizure-free EEG signals using EMD and EWT","authors":"Siddharth Saxena, C. Hemanth, R. Sangeetha","doi":"10.1109/ICNETS2.2017.8067961","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067961","url":null,"abstract":"Objectives: Electroencephalogram (EEG) plays an important role in recording the activity of human brain. Identification of epileptic seizures can be done using EEG signals. Methods/ Statistical Analysis: In this work for classification of EEG signals a method known as Empirical mode decomposition (EMD) is used and compared with empirical wavelet transform (EWT) based method. Findings: In this paper the EMD has been considered for five classes of EEG signals. Intrinsic Mode functions obtained for these EEG signals have been shown. The amplitude modulation bandwidth BAM and frequency modulation bandwidth BFM have been calculated. Applications/ Improvements: The classification based on bandwidth features and least square support vector machine (LS-SVM) provided better categorization accuracy than earlier adopted methods. Results have been shown in this report.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116723655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067953
K. Arun, K. Srivatsan
Objective: To implement an algorithm for improving the speed of Floating Point Multiplication. Methods/Statistical analysis: Recursive Dadda algorithm is used for implementing the floating point multiplier. IEEE 754 single precision binary floating point representation is used for representing Floating Point number. For the multiplication of mantissa Carry Save multiplier is replaced by Dadda multiplier for improving the speed. Using Verilog HDL multiplier is implemented and it is targeted to Xilinx vertex-5 FPGA. Improvements: The speed of operation is increased compared with Carry Save Multiplier. The multiplier which we developed handles both overflow and underflow cases.
{"title":"A binary high speed floating point multiplier","authors":"K. Arun, K. Srivatsan","doi":"10.1109/ICNETS2.2017.8067953","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067953","url":null,"abstract":"Objective: To implement an algorithm for improving the speed of Floating Point Multiplication. Methods/Statistical analysis: Recursive Dadda algorithm is used for implementing the floating point multiplier. IEEE 754 single precision binary floating point representation is used for representing Floating Point number. For the multiplication of mantissa Carry Save multiplier is replaced by Dadda multiplier for improving the speed. Using Verilog HDL multiplier is implemented and it is targeted to Xilinx vertex-5 FPGA. Improvements: The speed of operation is increased compared with Carry Save Multiplier. The multiplier which we developed handles both overflow and underflow cases.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115948828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067884
K. F. K. Jiavana, Nitin Gurjar
In this paper, designing of stochastic multiplier and divider is proposed for designing of Lower-Upper decomposition (LUD) scheme. By using stochastic computation complicated operations of LUD can be performed by simple logic gates. By using stochastic multiplier and divider computational complexity is reduced. Stochastic multiplier and divider use the stochastic stream which reduces the computational complexity by minimizing the stream length. The problems in Lower-Upper decomposition with stochastic stream are long computational latency and large computation variance. Dual partition based computation scheme which reduces input stream length is used to overcome the challenges. The design and implementation of stochastic LUD is carried out using Cadence Encounter tool. We have designed stochastic multiplier, divider and stochastic LUD with CMOS 180nm technology.
{"title":"Stochastic multiplier and divider for stochastic LU decomposition","authors":"K. F. K. Jiavana, Nitin Gurjar","doi":"10.1109/ICNETS2.2017.8067884","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067884","url":null,"abstract":"In this paper, designing of stochastic multiplier and divider is proposed for designing of Lower-Upper decomposition (LUD) scheme. By using stochastic computation complicated operations of LUD can be performed by simple logic gates. By using stochastic multiplier and divider computational complexity is reduced. Stochastic multiplier and divider use the stochastic stream which reduces the computational complexity by minimizing the stream length. The problems in Lower-Upper decomposition with stochastic stream are long computational latency and large computation variance. Dual partition based computation scheme which reduces input stream length is used to overcome the challenges. The design and implementation of stochastic LUD is carried out using Cadence Encounter tool. We have designed stochastic multiplier, divider and stochastic LUD with CMOS 180nm technology.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126194630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：