Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067958
M. Athira, Lekha Abrahami, R. Sangeetha
Background/Objective: Interior gateway protocols are used for communication between devices in an organizational network. The setup which includes routers, switches and hosts is simulated in GNS3 software to represent a complex real time enterprise level network. Each protocol is implemented in the designed topology. Methods/Statistical analysis: Interior gateway protocols-RIP (Routing Information Protocol), OSPF (Open Shortest Path First) and EIGRP (Enhanced Interior Gateway Routing Protocol) are analyzed in a complex enterprise level network using GNS3 software. Findings: Each protocol implemented in the designed topology is analyzed in terms of throughput, end to end delay and convergence time. Authentication is provided at each node so as to ensure secure transmission of data. The aim of the study is to find out the best feasible interior gateway routing protocol for different traffic scenarios. Application: The best interior gateway protocol can be found which can be used in an organizational network.
{"title":"Study on network performance of interior gateway protocols — RIP, EIGRP and OSPF","authors":"M. Athira, Lekha Abrahami, R. Sangeetha","doi":"10.1109/ICNETS2.2017.8067958","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067958","url":null,"abstract":"Background/Objective: Interior gateway protocols are used for communication between devices in an organizational network. The setup which includes routers, switches and hosts is simulated in GNS3 software to represent a complex real time enterprise level network. Each protocol is implemented in the designed topology. Methods/Statistical analysis: Interior gateway protocols-RIP (Routing Information Protocol), OSPF (Open Shortest Path First) and EIGRP (Enhanced Interior Gateway Routing Protocol) are analyzed in a complex enterprise level network using GNS3 software. Findings: Each protocol implemented in the designed topology is analyzed in terms of throughput, end to end delay and convergence time. Authentication is provided at each node so as to ensure secure transmission of data. The aim of the study is to find out the best feasible interior gateway routing protocol for different traffic scenarios. Application: The best interior gateway protocol can be found which can be used in an organizational network.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129069991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067886
Radhika Ramesh, Nitin Tiwari, Pravin Joshi
There is an increase in demand for high speed photodetectors in optical fiber networks for both short and long-haul applications with the continuously increasing demand in bandwidth. The main challenges in this direction is the focusing of light into small areas, as a slight misalignment in the assembly can lead to degradation of the system performance. In this paper, we design a lens assembly using a ball lens with a parabolic mirror and study the impact of lateral misalignments between fiber and ball lens and at the detector on the system performance using CodeV and Synopsys RSoft ModeSYS® tool.
{"title":"Design of a coupling lens assembly and study on the impact of optical misalignments and variations of lens assembly on BER of a system","authors":"Radhika Ramesh, Nitin Tiwari, Pravin Joshi","doi":"10.1109/ICNETS2.2017.8067886","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067886","url":null,"abstract":"There is an increase in demand for high speed photodetectors in optical fiber networks for both short and long-haul applications with the continuously increasing demand in bandwidth. The main challenges in this direction is the focusing of light into small areas, as a slight misalignment in the assembly can lead to degradation of the system performance. In this paper, we design a lens assembly using a ball lens with a parabolic mirror and study the impact of lateral misalignments between fiber and ball lens and at the detector on the system performance using CodeV and Synopsys RSoft ModeSYS® tool.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115584599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067922
K. Nagarajan, V. V. Kumar, S. Sophia
Orthogonal Frequency Division Multiplexing is one of the enhanced communication techniques which makes the emerging fourth generation (4G) and fifth generation (5G) communication possible. Because of multipath propagation & noise the performance of OFDM system is affected by channel leakage. OFDM channel is analyzed to estimate the channel leakage, MSE — Mean Square Error and SNR — Signal to Noise Ratio using DWT — Discrete Wavelet Transforms Techniques. And the major problem found in an OFDM system is high PAPR — Peak to Average Power Ratio of the OFDM signal. Generally the OFDM transmitter system consists of an HPA — High Power Amplifier which is used to obtain sufficient power to the transmitted signals. However this HPA has limited range, the OFDM signals with high PAPR value gets distorted by the non-linearity of HPA which adds more interference to the system. This work proposes DWT for analyzing the channel estimation and PTS — Partial Time Sequence to reduce PAPR in a 16 QAM OFDM system.
{"title":"Analysis of OFDM systems for high bandwidth application","authors":"K. Nagarajan, V. V. Kumar, S. Sophia","doi":"10.1109/ICNETS2.2017.8067922","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067922","url":null,"abstract":"Orthogonal Frequency Division Multiplexing is one of the enhanced communication techniques which makes the emerging fourth generation (4G) and fifth generation (5G) communication possible. Because of multipath propagation & noise the performance of OFDM system is affected by channel leakage. OFDM channel is analyzed to estimate the channel leakage, MSE — Mean Square Error and SNR — Signal to Noise Ratio using DWT — Discrete Wavelet Transforms Techniques. And the major problem found in an OFDM system is high PAPR — Peak to Average Power Ratio of the OFDM signal. Generally the OFDM transmitter system consists of an HPA — High Power Amplifier which is used to obtain sufficient power to the transmitted signals. However this HPA has limited range, the OFDM signals with high PAPR value gets distorted by the non-linearity of HPA which adds more interference to the system. This work proposes DWT for analyzing the channel estimation and PTS — Partial Time Sequence to reduce PAPR in a 16 QAM OFDM system.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127244722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067913
A. Keerthika, V. Berlin Hency
In recent years Wireless sensor networks (WSNs) play a vital role in various real time application, by collecting a huge amount of various sensory data from the field. The routing protocol for wireless sensor networks mainly aims in the energy-efficiency of the network. Due to restricted energy, memory, transmission range, power and high traffic load, the nodes which act as a sink get depleted quickly. Because of these so many approaches proposed over past years to reduce energy consumption and to prolong network lifetime. Energy consumption of the network can be reduced by means of using the mobile sink and it also reduces the hotspot problem. Hence Virtual Grid based Data Gathering technique using mobile agent (VGDG-MA) for WSN with mobile sink is proposed. Mobile agent is the one which is used to collect the data by flexibly planning its route. In this paper, virtual grid based data gathering technique using mobile agent is presented that mainly aims to reduce the route construction path frequently in a grid structure. Mobile agent is placed in a multihop environment which automatically clones and migrates based on the environmental changes. Instead of mobile sink, these mobile agents migrate in the environment and collect data, clone when it leaves the particular node results in energy consumption and also reduce the construction cost of the network. Based on residual energy of the node, sink relocates its position and avoids network failure. Proposed method shows that mobile agent can powerfully transfer data from sink to source and source to which results in energy consumption, good packet delivery ratio. Simulation results shows that the proposed VGDG-MA increases the network lifetime and gives better results in terms of energy consumption, packet delivery ratio and throughput when compared with other protocols. Simulation is carried out in OMNeT++.
{"title":"Virtuial grid based data gathering technique using mobile agent (VGDG-MA)","authors":"A. Keerthika, V. Berlin Hency","doi":"10.1109/ICNETS2.2017.8067913","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067913","url":null,"abstract":"In recent years Wireless sensor networks (WSNs) play a vital role in various real time application, by collecting a huge amount of various sensory data from the field. The routing protocol for wireless sensor networks mainly aims in the energy-efficiency of the network. Due to restricted energy, memory, transmission range, power and high traffic load, the nodes which act as a sink get depleted quickly. Because of these so many approaches proposed over past years to reduce energy consumption and to prolong network lifetime. Energy consumption of the network can be reduced by means of using the mobile sink and it also reduces the hotspot problem. Hence Virtual Grid based Data Gathering technique using mobile agent (VGDG-MA) for WSN with mobile sink is proposed. Mobile agent is the one which is used to collect the data by flexibly planning its route. In this paper, virtual grid based data gathering technique using mobile agent is presented that mainly aims to reduce the route construction path frequently in a grid structure. Mobile agent is placed in a multihop environment which automatically clones and migrates based on the environmental changes. Instead of mobile sink, these mobile agents migrate in the environment and collect data, clone when it leaves the particular node results in energy consumption and also reduce the construction cost of the network. Based on residual energy of the node, sink relocates its position and avoids network failure. Proposed method shows that mobile agent can powerfully transfer data from sink to source and source to which results in energy consumption, good packet delivery ratio. Simulation results shows that the proposed VGDG-MA increases the network lifetime and gives better results in terms of energy consumption, packet delivery ratio and throughput when compared with other protocols. Simulation is carried out in OMNeT++.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127288429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067962
N. Desai, J. Alex
Urban air pollution rate has grown to alarming state across the India. Most of the cities are facing issue of poor air quality which fails to meet standards of air for good health. It is indeed necessary to develop an air pollution measurement and prediction system for a smart city. This proposed work acquires carbon dioxide and carbon monoxide level in the air along with Global Positioning System (GPS) location by using pollution detection sensor and uploads into Azure cloud services. Low cost embedded Beagle bone board along with gas sensors are used for data acquisition. Microsoft's Azure Machine learning service is used to predict the pollution metrics with the help of previous data. Processed data is fetched and represented by Power BI tool. Calibrated gas sensor data is fetched from sensors and successfully uploaded into cloud. Data stored in cloud is utilized by different cloud services to make the data meaningful. Proposed system is implemented and useful to monitor and reduce the pollution in a smart city by avoiding the pollution causes.
{"title":"IoT based air pollution monitoring and predictor system on Beagle bone black","authors":"N. Desai, J. Alex","doi":"10.1109/ICNETS2.2017.8067962","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067962","url":null,"abstract":"Urban air pollution rate has grown to alarming state across the India. Most of the cities are facing issue of poor air quality which fails to meet standards of air for good health. It is indeed necessary to develop an air pollution measurement and prediction system for a smart city. This proposed work acquires carbon dioxide and carbon monoxide level in the air along with Global Positioning System (GPS) location by using pollution detection sensor and uploads into Azure cloud services. Low cost embedded Beagle bone board along with gas sensors are used for data acquisition. Microsoft's Azure Machine learning service is used to predict the pollution metrics with the help of previous data. Processed data is fetched and represented by Power BI tool. Calibrated gas sensor data is fetched from sensors and successfully uploaded into cloud. Data stored in cloud is utilized by different cloud services to make the data meaningful. Proposed system is implemented and useful to monitor and reduce the pollution in a smart city by avoiding the pollution causes.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067963
B. S. Raghavan, V. S. K. Bhaaskaran
Background: Multiple-Valued Logic (MVL) is the non-binary-valued system, in which more than two levels of information content are available, i.e., L>2. In modern technologies, the dual level binary logic circuits have normally been used. However, these suffer from several significant issues such as the interconnection considerations including the parasitics, area and power dissipation. The MVL circuits have been proved to be consisting of reduced circuitry and increased efficiency in terms of higher utilization of the circuit resources through multiple levels of voltage. Innumerable algorithms have been developed for designing such MVL circuits. Extended form is one of the algebraic techniques used in designing these MVL circuits. Voltage mode design has also been employed for constructing various types of MVL circuits. Novelty: This paper proposes a novel MVLTRANS inverter, designed using conventional CMOS and pass transistor logic based MVLPTL inverter. Binary to MVL Converter/Encoder and MVL to binary Decoder/Converter are also presented in the paper. In addition to the proposed decoder circuit, a 4-bit novel MVL Binary decoder circuit is also proposed. Tools Used: All these circuits are designed, implemented and verified using Cadence® Virtuoso tools using 180 nm technology library.
{"title":"Design of novel Multiple Valued Logic (MVL) circuits","authors":"B. S. Raghavan, V. S. K. Bhaaskaran","doi":"10.1109/ICNETS2.2017.8067963","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067963","url":null,"abstract":"Background: Multiple-Valued Logic (MVL) is the non-binary-valued system, in which more than two levels of information content are available, i.e., L>2. In modern technologies, the dual level binary logic circuits have normally been used. However, these suffer from several significant issues such as the interconnection considerations including the parasitics, area and power dissipation. The MVL circuits have been proved to be consisting of reduced circuitry and increased efficiency in terms of higher utilization of the circuit resources through multiple levels of voltage. Innumerable algorithms have been developed for designing such MVL circuits. Extended form is one of the algebraic techniques used in designing these MVL circuits. Voltage mode design has also been employed for constructing various types of MVL circuits. Novelty: This paper proposes a novel MVLTRANS inverter, designed using conventional CMOS and pass transistor logic based MVLPTL inverter. Binary to MVL Converter/Encoder and MVL to binary Decoder/Converter are also presented in the paper. In addition to the proposed decoder circuit, a 4-bit novel MVL Binary decoder circuit is also proposed. Tools Used: All these circuits are designed, implemented and verified using Cadence® Virtuoso tools using 180 nm technology library.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128523086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067952
Swati Verma, A. A. Angelina, V. S. K. Bhaaskaran
Background/Objectives: Domino Logic is extensively used in high performance microprocessor designs. The conventional pipelining of domino logic designs are more prone to timing overhead due to the factors, namely, clock skew, delay caused by the latches, and its inability to borrow time. Methods/Statistical analysis: The cascaded pipelined domino stages utilizes two and four phase clocks for sequencing the operation. The pipelined stages are sensitive to clock edges, and are incapable of borrowing time. Hence, latches are included between the consecutive stages to facilitate the pipeline. Considering the required computation time of the circuit, the speed enhancement in a domino logic pipelined circuit could be achieved by reducing the precharge and evaluation period. Findings: In this paper, four phase self-timed clocking scheme is implemented on a pipelined domino logic ALU. In addition to the maximum computation time of an individual stage, the setup and hold time are also considered for defining the clock evaluation time in the four phase scheme. Furthermore, it is ensured that the precharge operation happens only after the previous output is passed on to the next stage. The analysis and comparison of the conventional pipelined domino circuit design, the skew tolerant self timed pipeline design of an inverter chain and the ALU, using two phase and four phase overlapping clocks are done using Cadence® Virtuoso Spectre employing 180nm technology library and analyzed in the ADE-L environment. Improvements/Applications: The skew tolerant self-timed design of the domino logic pipelined ALU demonstrates an increased speed of 60% and reduction in power of 30% as compared to the single phase pipelined ALU design.
{"title":"Multiphase pipelining in domino logic ALU","authors":"Swati Verma, A. A. Angelina, V. S. K. Bhaaskaran","doi":"10.1109/ICNETS2.2017.8067952","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067952","url":null,"abstract":"Background/Objectives: Domino Logic is extensively used in high performance microprocessor designs. The conventional pipelining of domino logic designs are more prone to timing overhead due to the factors, namely, clock skew, delay caused by the latches, and its inability to borrow time. Methods/Statistical analysis: The cascaded pipelined domino stages utilizes two and four phase clocks for sequencing the operation. The pipelined stages are sensitive to clock edges, and are incapable of borrowing time. Hence, latches are included between the consecutive stages to facilitate the pipeline. Considering the required computation time of the circuit, the speed enhancement in a domino logic pipelined circuit could be achieved by reducing the precharge and evaluation period. Findings: In this paper, four phase self-timed clocking scheme is implemented on a pipelined domino logic ALU. In addition to the maximum computation time of an individual stage, the setup and hold time are also considered for defining the clock evaluation time in the four phase scheme. Furthermore, it is ensured that the precharge operation happens only after the previous output is passed on to the next stage. The analysis and comparison of the conventional pipelined domino circuit design, the skew tolerant self timed pipeline design of an inverter chain and the ALU, using two phase and four phase overlapping clocks are done using Cadence® Virtuoso Spectre employing 180nm technology library and analyzed in the ADE-L environment. Improvements/Applications: The skew tolerant self-timed design of the domino logic pipelined ALU demonstrates an increased speed of 60% and reduction in power of 30% as compared to the single phase pipelined ALU design.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127687429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067935
P. Manikandan, B. Bindu
Acapacitor-less low drop-out linear regulator with a new compensation technique is presented. A conventional LDO suffers intrinsic stability problem at low load currents and require a large offchip capacitor to make LDO stable. This off-chip capacitor occupies large area in the chip and thus not ideal for SoC applications. Many LDO architectures have been proposed recently but still some of them requires off-chip capacitor and suffers due to bandwidth limitation and requires additional complex circuits. The proposed LDO architecture with a compensation network provides solution to the above problem. The proposed LDO is simulated and verified in Cadence using 180 nm CMOS technology.
{"title":"A capacitor-less low-dropout regulator (LDO) architecture for wireless application","authors":"P. Manikandan, B. Bindu","doi":"10.1109/ICNETS2.2017.8067935","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067935","url":null,"abstract":"Acapacitor-less low drop-out linear regulator with a new compensation technique is presented. A conventional LDO suffers intrinsic stability problem at low load currents and require a large offchip capacitor to make LDO stable. This off-chip capacitor occupies large area in the chip and thus not ideal for SoC applications. Many LDO architectures have been proposed recently but still some of them requires off-chip capacitor and suffers due to bandwidth limitation and requires additional complex circuits. The proposed LDO architecture with a compensation network provides solution to the above problem. The proposed LDO is simulated and verified in Cadence using 180 nm CMOS technology.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126423783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067911
T. Moorthy, P. Nair
The micro mirror is a miniature device which can be used to modulate the light parameters. The light modulation is achieved by moving the micro mirror in the piston and tip-tilt mode of operation with the help of the actuators attached to each side of the mirror. This paper presents the results of COMSOL Multiphysics® modeling and study of two types of electro thermal actuators (ETA's) for 3D actuation of hexagonal MEMS micro mirrors. These actuators work on the principle of joule heating and hence their size, shape and composition determine the angular and vertical displacement. An array of this hexagonal mirror is intended to be used for maskless laser interferometric lithography (LIL) for realization of periodic structures.
{"title":"Modeling 3-dimensional electro thermal actuation of MEMS mirrors","authors":"T. Moorthy, P. Nair","doi":"10.1109/ICNETS2.2017.8067911","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067911","url":null,"abstract":"The micro mirror is a miniature device which can be used to modulate the light parameters. The light modulation is achieved by moving the micro mirror in the piston and tip-tilt mode of operation with the help of the actuators attached to each side of the mirror. This paper presents the results of COMSOL Multiphysics® modeling and study of two types of electro thermal actuators (ETA's) for 3D actuation of hexagonal MEMS micro mirrors. These actuators work on the principle of joule heating and hence their size, shape and composition determine the angular and vertical displacement. An array of this hexagonal mirror is intended to be used for maskless laser interferometric lithography (LIL) for realization of periodic structures.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131081422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067887
B. Gomatheeshwari, J. Selvakumar
In this paper, Energy aware scheduling algorithms are developed for task allocation on heterogeneous multi-core processors is NP-hard. The objective is to create efficient scheduling method to solve problem. ETPS (Energy token proportionate sharing) algorithm and dynamic ETPS are the scheduling methods to generate optimality for task mapping on multi core. To validate the model extensive simulation were carried out in C++ simulator. MILP formulations are developed to create token based scheduling algorithms. Our simulated results achieve better performance and reduced 15% of task miss rate and maximize the energy efficiency.
{"title":"Token based energy aware scheduling algorithms for heterogeneous multi-core","authors":"B. Gomatheeshwari, J. Selvakumar","doi":"10.1109/ICNETS2.2017.8067887","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067887","url":null,"abstract":"In this paper, Energy aware scheduling algorithms are developed for task allocation on heterogeneous multi-core processors is NP-hard. The objective is to create efficient scheduling method to solve problem. ETPS (Energy token proportionate sharing) algorithm and dynamic ETPS are the scheduling methods to generate optimality for task mapping on multi core. To validate the model extensive simulation were carried out in C++ simulator. MILP formulations are developed to create token based scheduling algorithms. Our simulated results achieve better performance and reduced 15% of task miss rate and maximize the energy efficiency.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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