Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067966
S. Patil, V. S. K. Bhaaskaran
Background/Objective: In the recent years, the instantaneous power consumption and the total energy dissipation of a circuit have become very important factors to be considered in complex VLSI system design solutions. The adiabatic logic is a technique, which is used to optimize the power dissipation and the energy recovery capability of these circuits, and this logic makes the VLSI circuits reuse the consumed power. This paper compares different adiabatic SRAM cell structures presented in the literature. Furthermore, the conventional SRAM cell and all the related designs are implemented using FinFET devices aiming at low power operation capability. Methods/Statistical analysis: The SRAM cell design is carried out in Cadence® EDA environment and power and energy values are estimated for the CMOS processes, namely, 180nm and 32nm followed by the 32nm FinFET technology. The two different technology libraries have been employed to identify the effects of the lower technology nodal effect on the power dissipation. The layouts for these SRAM cells have been drawn using Cadence® Assura tool. Findings: The results show that the power consumption of the FinFET based adiabatic SRAM cells (8T and 9T cell structure) is less than the conventional 6T CMOS based SRAM cell. Conclusion/improvement: In this paper, the conventional SRAM cell and the adiabatic SRAM cells with different technology nodes, namely, DSM and UDSM are compared for their power and energy values. The adiabatic logic displays lower power and energy consumption compared to those incurred by the conventional 6T CMOS SRAM cell. Furthermore, the FinFET device based circuits portrays advantages with its better control over the device channel and reduced short channel effects, resulting in reduced leakage power. The FinFET based SRAM cell employing the adiabatic logic incurs the minimum power and energy dissipation.
{"title":"Optimization of power and energy in FinFET based SRAM cell using adiabatic logic","authors":"S. Patil, V. S. K. Bhaaskaran","doi":"10.1109/ICNETS2.2017.8067966","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067966","url":null,"abstract":"Background/Objective: In the recent years, the instantaneous power consumption and the total energy dissipation of a circuit have become very important factors to be considered in complex VLSI system design solutions. The adiabatic logic is a technique, which is used to optimize the power dissipation and the energy recovery capability of these circuits, and this logic makes the VLSI circuits reuse the consumed power. This paper compares different adiabatic SRAM cell structures presented in the literature. Furthermore, the conventional SRAM cell and all the related designs are implemented using FinFET devices aiming at low power operation capability. Methods/Statistical analysis: The SRAM cell design is carried out in Cadence® EDA environment and power and energy values are estimated for the CMOS processes, namely, 180nm and 32nm followed by the 32nm FinFET technology. The two different technology libraries have been employed to identify the effects of the lower technology nodal effect on the power dissipation. The layouts for these SRAM cells have been drawn using Cadence® Assura tool. Findings: The results show that the power consumption of the FinFET based adiabatic SRAM cells (8T and 9T cell structure) is less than the conventional 6T CMOS based SRAM cell. Conclusion/improvement: In this paper, the conventional SRAM cell and the adiabatic SRAM cells with different technology nodes, namely, DSM and UDSM are compared for their power and energy values. The adiabatic logic displays lower power and energy consumption compared to those incurred by the conventional 6T CMOS SRAM cell. Furthermore, the FinFET device based circuits portrays advantages with its better control over the device channel and reduced short channel effects, resulting in reduced leakage power. The FinFET based SRAM cell employing the adiabatic logic incurs the minimum power and energy dissipation.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"254 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114003172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067885
Saurav Sarkar
A cache memory unit and controller that makes instructions requiring large number of clocks by the processor more efficient. This cache memory has been introduced as an intermediary memory unit between the L1 cache and the processor. This specialized memory stores the instruction and the related data requiring large number of clock cycles for execution. Accordingly, a control unit and a cache memory has been designed. Instructions requiring less number of clock cycles for execution by processor than the number of clock cycles required for fetching it from the cache memory are not stored in the memory unit.
{"title":"Implementation of a novel cache memory unit for storing processed data and instructions","authors":"Saurav Sarkar","doi":"10.1109/ICNETS2.2017.8067885","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067885","url":null,"abstract":"A cache memory unit and controller that makes instructions requiring large number of clocks by the processor more efficient. This cache memory has been introduced as an intermediary memory unit between the L1 cache and the processor. This specialized memory stores the instruction and the related data requiring large number of clock cycles for execution. Accordingly, a control unit and a cache memory has been designed. Instructions requiring less number of clock cycles for execution by processor than the number of clock cycles required for fetching it from the cache memory are not stored in the memory unit.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067927
H. T. Salam, T. E. A. Khan, Nisha Kuruvila, S. Hameed
Reduced power without affecting delay is an important concern today. CAMs (Content Addressable Memories) are memories that implement lookup table functions using comparison circuitry. CAMs are used in table lookup Based applications such as Internet routers and processor caches. Deeply scaled technology node, with multigate devices, replacing planar MOSFETs, are expected to bring new era to CAM design. FinFET, a vertical channel gate wrap around double-gate device, has come up as the best alternative to cover up the short channel effects of planar MOSFETs. The aim of the project was to compare the N-curves of CAMs using compact models of 32-nm CMOS, 32nm-double gate FinFETs and BSIM-CMG model FinFETs in spice. The power and delay characteristics are also compared to show the superiority of BSIM-CMG CAMs.
{"title":"A comparative performance analysis of CAMs using different model files in Spice","authors":"H. T. Salam, T. E. A. Khan, Nisha Kuruvila, S. Hameed","doi":"10.1109/ICNETS2.2017.8067927","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067927","url":null,"abstract":"Reduced power without affecting delay is an important concern today. CAMs (Content Addressable Memories) are memories that implement lookup table functions using comparison circuitry. CAMs are used in table lookup Based applications such as Internet routers and processor caches. Deeply scaled technology node, with multigate devices, replacing planar MOSFETs, are expected to bring new era to CAM design. FinFET, a vertical channel gate wrap around double-gate device, has come up as the best alternative to cover up the short channel effects of planar MOSFETs. The aim of the project was to compare the N-curves of CAMs using compact models of 32-nm CMOS, 32nm-double gate FinFETs and BSIM-CMG model FinFETs in spice. The power and delay characteristics are also compared to show the superiority of BSIM-CMG CAMs.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114423296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067957
E. Reddy, A. Therese
Objectives: The first installed optical fiber links were used for transmitting the telephony signals about 6 Mb/s over distance of around 10 km. Since the demand on communication network increases for bandwidth hungry services such as voice, video and data, telecommunication companies greatly enhanced the capacity of fiber lines. As increasing in the research further more leads to development in Wireless optical communication. These systems work in the same IR range in which normally the Optical fiber systems work. Methods/Statistical analysis: The Free-space optical interconnection (FSOI) technology enables high interconnection speed in next-generation services. FSOI uses laser links between the transmitter and receiver provides a lower propagation delay due to the line-of-sight (LOS) path and lower index of refraction of air. The performance of the links highly dependent on different weather conditions such as Fog, Turbulence and Rain. In this paper the combined result of Fog, Rain and Turbulence on FSOI links are compared and the suitable modulation technique is suggested to increase the spacing between optical transmitter and receiver. Findings: This paper gives the idea of which modulation technique is better for outdoor environment and to multiple users. This paper shows that maximum distance of 4 km between transmitter and receiver is possible by using M-QAM (M=16). Application/Improvements: Longer distance transmission provided with less loss of data even in high attenuation (30 dB/km) also provides multi user transmission.
{"title":"Analysis of atmospheric effects on free space optical communication","authors":"E. Reddy, A. Therese","doi":"10.1109/ICNETS2.2017.8067957","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067957","url":null,"abstract":"Objectives: The first installed optical fiber links were used for transmitting the telephony signals about 6 Mb/s over distance of around 10 km. Since the demand on communication network increases for bandwidth hungry services such as voice, video and data, telecommunication companies greatly enhanced the capacity of fiber lines. As increasing in the research further more leads to development in Wireless optical communication. These systems work in the same IR range in which normally the Optical fiber systems work. Methods/Statistical analysis: The Free-space optical interconnection (FSOI) technology enables high interconnection speed in next-generation services. FSOI uses laser links between the transmitter and receiver provides a lower propagation delay due to the line-of-sight (LOS) path and lower index of refraction of air. The performance of the links highly dependent on different weather conditions such as Fog, Turbulence and Rain. In this paper the combined result of Fog, Rain and Turbulence on FSOI links are compared and the suitable modulation technique is suggested to increase the spacing between optical transmitter and receiver. Findings: This paper gives the idea of which modulation technique is better for outdoor environment and to multiple users. This paper shows that maximum distance of 4 km between transmitter and receiver is possible by using M-QAM (M=16). Application/Improvements: Longer distance transmission provided with less loss of data even in high attenuation (30 dB/km) also provides multi user transmission.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128987138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067973
M. R. Sree, P. Vetrivelan, R. Ratheesh
The necessity for a network to provide wireless multimedia services in various levels of quality of service (QoS) with maximizing the utilization of spectral resources. By joint relaying and relay selection we can allocate resources with adaptive resource scheduling. The enhanced coverage and capacity is achieved with the help of small cell deployment. The proposed joint relaying and scheduling strategy enhance the capacity and optimize the energy consumption of the network. This work also focus on of decreasing power consumption for multimedia traffics along with joint relaying and adaptive resource scheduling strategies for Long Term Evolution Advanced (LTE-A) networks.
{"title":"Energy aware joint relaying and adaptive resource scheduling strategies for multimedia traffics in LTE-A networks","authors":"M. R. Sree, P. Vetrivelan, R. Ratheesh","doi":"10.1109/ICNETS2.2017.8067973","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067973","url":null,"abstract":"The necessity for a network to provide wireless multimedia services in various levels of quality of service (QoS) with maximizing the utilization of spectral resources. By joint relaying and relay selection we can allocate resources with adaptive resource scheduling. The enhanced coverage and capacity is achieved with the help of small cell deployment. The proposed joint relaying and scheduling strategy enhance the capacity and optimize the energy consumption of the network. This work also focus on of decreasing power consumption for multimedia traffics along with joint relaying and adaptive resource scheduling strategies for Long Term Evolution Advanced (LTE-A) networks.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125391351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067907
M. Narula, Aman Kumar
This paper proposes a new design to implement chipless RFID technology using rectangular ring shaped microstrip resonators of various structures to obtain different frequency signatures in the super high frequency range (2–3 GHz). It is observed that the prototype has minimal return loss and maximum resonance level has also been achieved which has been verified with graphical stimulated results and by numerical retrieval of parameters.
{"title":"Miniaturized chipless RFID tag using multiple microstrip resonators","authors":"M. Narula, Aman Kumar","doi":"10.1109/ICNETS2.2017.8067907","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067907","url":null,"abstract":"This paper proposes a new design to implement chipless RFID technology using rectangular ring shaped microstrip resonators of various structures to obtain different frequency signatures in the super high frequency range (2–3 GHz). It is observed that the prototype has minimal return loss and maximum resonance level has also been achieved which has been verified with graphical stimulated results and by numerical retrieval of parameters.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122116176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067945
Agineti Ashok, V. Ravi
Objectives: The main aim of this paper is to implement 32Bit MIPS (Microprocessor Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using Verilog HDL (hardware description language). Methods/Statistical analysis: The proposed algorithm analyzes the different stages of instruction decoding such as Instruction fetch module, Decoder module, Execution module and design theory based on 32Bit MIPS RISC Processor. In addition to that the algorithm uses pipelining concept which involves Instruction Fetch, Instruction Decode, Execution, Memory and Write Back modules of MIPS RISC processor based on 32Bit MIPS Instruction set in a single clock cycle. Findings: RISC is a processor which is intended to perform a tiny set of operations, to expand the rate (speed) of the processor. In general, the processor works with a huge number of instructions every second by bringing the information from the memory. In the event that the processor speed does not coordinate with memory access speed then hardware interlocks happen. In concurring with this there is one more issue called stalls because of instruction pipelining in the CPU design. The primary desire of this paper is to design and synthesize the MIPS processor by making utilization of register files and to insert the ALU forwarding unit in order to avoid the stalls and hardware interlocks. Application/Improvements: Based on the literature survey, the proposed method brings significant power efficiency improvements with enhanced performance and reduced power dissipation due to not only technology scaling but also a great deal of design efforts.
{"title":"ASIC design of MIPS based RISC processor for high performance","authors":"Agineti Ashok, V. Ravi","doi":"10.1109/ICNETS2.2017.8067945","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067945","url":null,"abstract":"Objectives: The main aim of this paper is to implement 32Bit MIPS (Microprocessor Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using Verilog HDL (hardware description language). Methods/Statistical analysis: The proposed algorithm analyzes the different stages of instruction decoding such as Instruction fetch module, Decoder module, Execution module and design theory based on 32Bit MIPS RISC Processor. In addition to that the algorithm uses pipelining concept which involves Instruction Fetch, Instruction Decode, Execution, Memory and Write Back modules of MIPS RISC processor based on 32Bit MIPS Instruction set in a single clock cycle. Findings: RISC is a processor which is intended to perform a tiny set of operations, to expand the rate (speed) of the processor. In general, the processor works with a huge number of instructions every second by bringing the information from the memory. In the event that the processor speed does not coordinate with memory access speed then hardware interlocks happen. In concurring with this there is one more issue called stalls because of instruction pipelining in the CPU design. The primary desire of this paper is to design and synthesize the MIPS processor by making utilization of register files and to insert the ALU forwarding unit in order to avoid the stalls and hardware interlocks. Application/Improvements: Based on the literature survey, the proposed method brings significant power efficiency improvements with enhanced performance and reduced power dissipation due to not only technology scaling but also a great deal of design efforts.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122744693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067926
M. N. Babu, A. Chakravarthy, C. Ravindranath
A Wireless Sensor Network (WSN) is a group of specialized sensors with a communications infrastructure for monitoring and recording conditions at diverse locations. In WSN's to access the real time data from the sensor nodes a proper user authentication technique is required before allowing the users to access the data. In 2015 A.K. Das has proposed a user authentication technique with three factors consisting of Smart card, Password and Biometric. In this paper we have identified the vulnerabilities in A.K. Das scheme and we have proposed a modified authentication scheme. We have used formal security analysis and informal security analysis to demonstrate that our scheme is more secure when compared with the related schemes.
{"title":"The design of a secure three factor authentication protocol for wireless sensor networks","authors":"M. N. Babu, A. Chakravarthy, C. Ravindranath","doi":"10.1109/ICNETS2.2017.8067926","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067926","url":null,"abstract":"A Wireless Sensor Network (WSN) is a group of specialized sensors with a communications infrastructure for monitoring and recording conditions at diverse locations. In WSN's to access the real time data from the sensor nodes a proper user authentication technique is required before allowing the users to access the data. In 2015 A.K. Das has proposed a user authentication technique with three factors consisting of Smart card, Password and Biometric. In this paper we have identified the vulnerabilities in A.K. Das scheme and we have proposed a modified authentication scheme. We have used formal security analysis and informal security analysis to demonstrate that our scheme is more secure when compared with the related schemes.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124311726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067897
A. Krishnakumar, V. Anuratha
As of the technological growth, Wireless Sensor Networks (WSNs) becomes an emerging research area. Sensors are combined as group called clusters to collect the data from where it is deployed. Clusters are maintained by Cluster Head (CH) and it maintains the transmission process which needs high energy. LEACH Protocol is considered for this work and in which the CHs are elected based on threshold function. The proposed methodology enhances the threshold function of LEACH with distance and count of neighbor nodes metrics develops better energy efficient function. Power Amplification for the elected CH chosen high power in order to increase the performance of the network. The number of alive nodes and residual energy of a node based on distance metrics are checked with the existing model. The simulation result shows the proposed scheme achieves high impact than the existing methodologies for WSNs.
{"title":"An energy-efficient cluster head selection of LEACH protocol for wireless sensor networks","authors":"A. Krishnakumar, V. Anuratha","doi":"10.1109/ICNETS2.2017.8067897","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067897","url":null,"abstract":"As of the technological growth, Wireless Sensor Networks (WSNs) becomes an emerging research area. Sensors are combined as group called clusters to collect the data from where it is deployed. Clusters are maintained by Cluster Head (CH) and it maintains the transmission process which needs high energy. LEACH Protocol is considered for this work and in which the CHs are elected based on threshold function. The proposed methodology enhances the threshold function of LEACH with distance and count of neighbor nodes metrics develops better energy efficient function. Power Amplification for the elected CH chosen high power in order to increase the performance of the network. The number of alive nodes and residual energy of a node based on distance metrics are checked with the existing model. The simulation result shows the proposed scheme achieves high impact than the existing methodologies for WSNs.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123403720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICNETS2.2017.8067914
K. Sandhya, B. Karthikeyan
In order to alleviate the problem of traffic jams, an automatic traffic diversion plan needs to be devised wherein neighbouring traffic signals can communicate. The microcontroller in the traffic signal of a jammed road, communicates this to the previous traffic signal itself, so that users can automatically take a diversion. This prevents further congestion or accumulation of traffic and speeds up clearance, saving time and fuel and minimizing exhaust emissions. In this system, every traffic light needs an additional “fourth light” installed to show the direction of the blocked road. When an inductive loop sensor on the road, continues to detect the presence of vehicles, even few seconds after the signal has changed from red to green, it is inferred as traffic jam. The heart of the traffic control system is the microcontroller chip, and the communication between traffic signals is established using Zigbee as a prototype. Furthermore, the information about the jammed roads can also be intimated to emergency services like fire and ambulance operations.
{"title":"Automatic traffic diversion system using traffic signals","authors":"K. Sandhya, B. Karthikeyan","doi":"10.1109/ICNETS2.2017.8067914","DOIUrl":"https://doi.org/10.1109/ICNETS2.2017.8067914","url":null,"abstract":"In order to alleviate the problem of traffic jams, an automatic traffic diversion plan needs to be devised wherein neighbouring traffic signals can communicate. The microcontroller in the traffic signal of a jammed road, communicates this to the previous traffic signal itself, so that users can automatically take a diversion. This prevents further congestion or accumulation of traffic and speeds up clearance, saving time and fuel and minimizing exhaust emissions. In this system, every traffic light needs an additional “fourth light” installed to show the direction of the blocked road. When an inductive loop sensor on the road, continues to detect the presence of vehicles, even few seconds after the signal has changed from red to green, it is inferred as traffic jam. The heart of the traffic control system is the microcontroller chip, and the communication between traffic signals is established using Zigbee as a prototype. Furthermore, the information about the jammed roads can also be intimated to emergency services like fire and ambulance operations.","PeriodicalId":413865,"journal":{"name":"2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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