Pub Date : 2019-01-23DOI: 10.1109/TPEL.2019.2894647
Li Zhang, X. Ruan
The instantaneous input and output power of the single-phase converter are imbalanced, resulting in second harmonic current (SHC). This paper provides an insight for reducing the SHC in two-stage single-phase converter from the perspective of the dc-bus port-impedance characterization. It is found that the dc-dc converters in the two-stage single-phase converter can be categorized into two types. One is operating as a bus-voltage-controlled converter (BVCC) whose dc-bus port-impedance is approximately inverse-proportional to the voltage loop gain. The other is operating as a bus-current-controlled converter (BCCC) whose dc-bus port-impedance is a negative resistor. Based on the dc-bus port-impedance characterization, critical points for SHC reduction are summarized, indicating that, for reducing SHC in BVCC, proper control scheme needs be incorporated for increasing the dc-bus port-impedance at twice the input frequency $(2f_{text{in}})$ or output frequency $(2f_{mathrm{o}});$ concurrently, the dc bus voltage ripple should be limited for reducing the SHC in the dc source or load; by contrast, for reducing SHC in BCCC, the dc bus voltage ripple should be reduced; simultaneously, the loop gain at $2fi_{text{in}}$ or $2f_{mathrm{o}}$ should be high enough for eliminating the SHC in the dc source or load. Thereafter, proper SHC reduction approaches are recommended for different types of two-stage single-phase converters, and pros and cons of different SHC reduction schemes are carefully reviewed. Finally, potential challenges and issues related to this research topic are discussed.
{"title":"Control Schemes for Reducing the Second Harmonic Current in Two-Stage Single-Phase Converter: An Overview from DC-Bus Port-Impedance Characterization","authors":"Li Zhang, X. Ruan","doi":"10.1109/TPEL.2019.2894647","DOIUrl":"https://doi.org/10.1109/TPEL.2019.2894647","url":null,"abstract":"The instantaneous input and output power of the single-phase converter are imbalanced, resulting in second harmonic current (SHC). This paper provides an insight for reducing the SHC in two-stage single-phase converter from the perspective of the dc-bus port-impedance characterization. It is found that the dc-dc converters in the two-stage single-phase converter can be categorized into two types. One is operating as a bus-voltage-controlled converter (BVCC) whose dc-bus port-impedance is approximately inverse-proportional to the voltage loop gain. The other is operating as a bus-current-controlled converter (BCCC) whose dc-bus port-impedance is a negative resistor. Based on the dc-bus port-impedance characterization, critical points for SHC reduction are summarized, indicating that, for reducing SHC in BVCC, proper control scheme needs be incorporated for increasing the dc-bus port-impedance at twice the input frequency $(2f_{text{in}})$ or output frequency $(2f_{mathrm{o}});$ concurrently, the dc bus voltage ripple should be limited for reducing the SHC in the dc source or load; by contrast, for reducing SHC in BCCC, the dc bus voltage ripple should be reduced; simultaneously, the loop gain at $2fi_{text{in}}$ or $2f_{mathrm{o}}$ should be high enough for eliminating the SHC in the dc source or load. Thereafter, proper SHC reduction approaches are recommended for different types of two-stage single-phase converters, and pros and cons of different SHC reduction schemes are carefully reviewed. Finally, potential challenges and issues related to this research topic are discussed.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125352271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8557532
Caleb W. Secrest, D. S. Ochs, Brent S. Gagas
This paper presents a detailed analysis of the Enhanced Luenberger Style Motion Observer (ELSO) for motor control applications. The analysis reveals that the state block diagram presented in the literature does not correctly represent the hand-code implementation of the structure that is presented in that same literature. As a result, the block diagram does not correctly model ELSO dynamic behavior. Here, a discussion of some common errors in discrete observer modeling are presented and used to correct the ELSO state block diagram. These common errors include: 1) failing to model the inherent delay present in the feedback path of all discrete state-filter and observer structures, 2) incorrectly modeling the difference equation index shifts that exist in nearly all observer structures, and 3) improper signal nomenclature for the observer predicted states. In this paper, the ELSO block diagram and code implementation from the literature is reviewed and the modeling errors are exposed. Finally, correction of these modeling errors is presented. The discrete modeling techniques presented in this paper are applicable to all discrete state-filters and observers.
{"title":"Deriving State Block Diagrams that Correctly Model Hand-Code Implementation – Correcting the Enhanced Luenberger Style Motion Observer as an Example","authors":"Caleb W. Secrest, D. S. Ochs, Brent S. Gagas","doi":"10.1109/ECCE.2018.8557532","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8557532","url":null,"abstract":"This paper presents a detailed analysis of the Enhanced Luenberger Style Motion Observer (ELSO) for motor control applications. The analysis reveals that the state block diagram presented in the literature does not correctly represent the hand-code implementation of the structure that is presented in that same literature. As a result, the block diagram does not correctly model ELSO dynamic behavior. Here, a discussion of some common errors in discrete observer modeling are presented and used to correct the ELSO state block diagram. These common errors include: 1) failing to model the inherent delay present in the feedback path of all discrete state-filter and observer structures, 2) incorrectly modeling the difference equation index shifts that exist in nearly all observer structures, and 3) improper signal nomenclature for the observer predicted states. In this paper, the ELSO block diagram and code implementation from the literature is reviewed and the modeling errors are exposed. Finally, correction of these modeling errors is presented. The discrete modeling techniques presented in this paper are applicable to all discrete state-filters and observers.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115153662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8557875
Subhrasankha Ghosh, S. Chattopadhyay
This paper presents a novel droop control method for decentralized paralleling of inverters in distributed generation (DG) system. The controller satisfies two basic objectives simultaneously: It provides active power ($P$) and reactive power ($Q$) based droops on voltage and frequency references using d-axis and q-axis currents, respectively and also incorporates virtual impedance loop. A novel PLL (Phase Locked Loop) structure and an integrated droop control (IDC) strategy are devised to achieve the same. This control method enables parallel inverters to share any type of load viz. linear and nonlinear proportional to the inverter power ratings under any transmission line condition namely resistive and resistive-inductive type. Performance of the proposed control method is verified through experimental results.
{"title":"Performance Verification of a New Integrated Droop Controller with a Novel Virtual-Impedance Based PLL for Parallel Operation of Inverters","authors":"Subhrasankha Ghosh, S. Chattopadhyay","doi":"10.1109/ECCE.2018.8557875","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8557875","url":null,"abstract":"This paper presents a novel droop control method for decentralized paralleling of inverters in distributed generation (DG) system. The controller satisfies two basic objectives simultaneously: It provides active power ($P$) and reactive power ($Q$) based droops on voltage and frequency references using d-axis and q-axis currents, respectively and also incorporates virtual impedance loop. A novel PLL (Phase Locked Loop) structure and an integrated droop control (IDC) strategy are devised to achieve the same. This control method enables parallel inverters to share any type of load viz. linear and nonlinear proportional to the inverter power ratings under any transmission line condition namely resistive and resistive-inductive type. Performance of the proposed control method is verified through experimental results.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115301550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8557515
Soheila Eskandari, Kang Peng, Bo Tian, E. Santi
In the quest for higher power density in switching converters, the use of SiC MOSFETs provides increased switching speed, which allows higher switching frequencies and smaller filtering elements. In order to accurately estimate switching losses in these fast high-voltage devices, a detailed analytical loss model considering parasitic effects and parasitic elements is required. In this paper, a simple and accurate analytical loss model is presented which considers the device junction capacitances, parasitic inductances and reverse recovery of the high voltage SiC MOSFET body diode. The reverse recovery time is calculated and used in the model. The proposed model provides easy-to-use closed-form mathematical equations and gives insight into the switching process and the parameters that affect it. Analytical equations are validated by experimental results.
{"title":"Accurate Analytical Switching Loss Model for High Voltage SiC MOSFETs Includes Parasitics and Body Diode Reverse Recovery Effects","authors":"Soheila Eskandari, Kang Peng, Bo Tian, E. Santi","doi":"10.1109/ECCE.2018.8557515","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8557515","url":null,"abstract":"In the quest for higher power density in switching converters, the use of SiC MOSFETs provides increased switching speed, which allows higher switching frequencies and smaller filtering elements. In order to accurately estimate switching losses in these fast high-voltage devices, a detailed analytical loss model considering parasitic effects and parasitic elements is required. In this paper, a simple and accurate analytical loss model is presented which considers the device junction capacitances, parasitic inductances and reverse recovery of the high voltage SiC MOSFET body diode. The reverse recovery time is calculated and used in the model. The proposed model provides easy-to-use closed-form mathematical equations and gives insight into the switching process and the parameters that affect it. Analytical equations are validated by experimental results.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115357571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8558207
Nicole Woodman, R. Bass, M. Donnelly
As the proliferation of electric vehicles continues to grow, it is becoming important to understand the impacts that electric vehicle charging will have on distribution assets. EV chargers are non-linear, multi-state loads. This manuscript presents a design method for the modeling of EV charging units using a VHDL-AMS simulation environment, per IEEE Standard 1076.1. Voltage and current data collected from in-service EV charging stations were used to create harmonic profiles of the EV charging units. From these profiles, generalized models for both Level 2 and Level 3 EV chargers were created. These models were validated within a larger system context using the IEEE 13 node test feeder. A VHDL-AMS tool has been created so distribution engineers may assess the impacts that EV chargers have on distribution assets. The tool may also be used to assist with the selection of transformers, conductors, and protection equipment.
{"title":"Modeling Harmonic Impacts of Electric Vehicle Chargers on Distribution Networks","authors":"Nicole Woodman, R. Bass, M. Donnelly","doi":"10.1109/ECCE.2018.8558207","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8558207","url":null,"abstract":"As the proliferation of electric vehicles continues to grow, it is becoming important to understand the impacts that electric vehicle charging will have on distribution assets. EV chargers are non-linear, multi-state loads. This manuscript presents a design method for the modeling of EV charging units using a VHDL-AMS simulation environment, per IEEE Standard 1076.1. Voltage and current data collected from in-service EV charging stations were used to create harmonic profiles of the EV charging units. From these profiles, generalized models for both Level 2 and Level 3 EV chargers were created. These models were validated within a larger system context using the IEEE 13 node test feeder. A VHDL-AMS tool has been created so distribution engineers may assess the impacts that EV chargers have on distribution assets. The tool may also be used to assist with the selection of transformers, conductors, and protection equipment.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115447694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8557891
S. Pan, Ching-Jan Chen, Chieh-Ju Tsai
Ripple-based constant on-time (RBCOT) controlled buck converter is widely used in power conversion system, such as voltage regulator module (VRM) or point of load (POL), but it has instability problem caused by using the ceramic capacitor (low ESR) as its output capacitor. To solve this issue, this paper proposed a novel capacitor current constant on-time (C2COT) controlled buck converter, and it can achieve both fast transient response and be stable even if using the ceramic output capacitor. Moreover, the proposed dynamic on-time generator and novel minimum off-time generator for faster response and smaller chip area are introduced. The proposed control methodology was realized with 0.18um CMOS, operated at 4-MHz switching frequency and performed transient responses of settling time=200ns and 100ns at load current whose slew rate=1.3A/500ns step-up and step-down, respectively, in measurement results. Total chip size is only 1140.87um*993.08um with pad ring.
{"title":"A Novel Capacitor Current Constant on-Time Controlled Buck Converter at 4-MHz Switching Frequency","authors":"S. Pan, Ching-Jan Chen, Chieh-Ju Tsai","doi":"10.1109/ECCE.2018.8557891","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8557891","url":null,"abstract":"Ripple-based constant on-time (RBCOT) controlled buck converter is widely used in power conversion system, such as voltage regulator module (VRM) or point of load (POL), but it has instability problem caused by using the ceramic capacitor (low ESR) as its output capacitor. To solve this issue, this paper proposed a novel capacitor current constant on-time (C2COT) controlled buck converter, and it can achieve both fast transient response and be stable even if using the ceramic output capacitor. Moreover, the proposed dynamic on-time generator and novel minimum off-time generator for faster response and smaller chip area are introduced. The proposed control methodology was realized with 0.18um CMOS, operated at 4-MHz switching frequency and performed transient responses of settling time=200ns and 100ns at load current whose slew rate=1.3A/500ns step-up and step-down, respectively, in measurement results. Total chip size is only 1140.87um*993.08um with pad ring.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117338535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8558356
Syed Ahmed Ali Najafi, Awab A. Ali, Y. Sozer, Alex De Abreu-Garcia
This paper proposes a superior energy harvester system which uses magnetic fields as its source. The design parameters have been analyzed to determine their impact on the amount of power that can be harvested. An efficient and novel power processing unit which produces a regulated DC voltage and distributes the power between the load and the backup energy storage element has been proposed. Experimental results have demonstrated that the proposed harvester utilizing the nanocrystalline material can achieve a power density of 100.2 mW/cm3, which is much higher than that reported in many other researches. The proposed harvester can produce as much as 55 W of power from a power line carrying 615 A of AC current.
{"title":"Energy Harvesting from Overhead Transmission Line Magnetic fields","authors":"Syed Ahmed Ali Najafi, Awab A. Ali, Y. Sozer, Alex De Abreu-Garcia","doi":"10.1109/ECCE.2018.8558356","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8558356","url":null,"abstract":"This paper proposes a superior energy harvester system which uses magnetic fields as its source. The design parameters have been analyzed to determine their impact on the amount of power that can be harvested. An efficient and novel power processing unit which produces a regulated DC voltage and distributes the power between the load and the backup energy storage element has been proposed. Experimental results have demonstrated that the proposed harvester utilizing the nanocrystalline material can achieve a power density of 100.2 mW/cm3, which is much higher than that reported in many other researches. The proposed harvester can produce as much as 55 W of power from a power line carrying 615 A of AC current.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"37 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8557643
Hiromasa Motoyama, Y. Hayashi, T. Takeshita
This paper presents a simple control method of a wireless power transfer system using a three-phase to single-phase matrix converter. In this control method, the duty cycles of all switches can be obtained by simple calculation. In addition, the system operation and control method of the proposed wireless transfer system are explained. The effectiveness of the control method is verified by experiments.
{"title":"Simple Control Method of Wireless Power Ttansfer System Using Matrix Converter","authors":"Hiromasa Motoyama, Y. Hayashi, T. Takeshita","doi":"10.1109/ECCE.2018.8557643","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8557643","url":null,"abstract":"This paper presents a simple control method of a wireless power transfer system using a three-phase to single-phase matrix converter. In this control method, the duty cycles of all switches can be obtained by simple calculation. In addition, the system operation and control method of the proposed wireless transfer system are explained. The effectiveness of the control method is verified by experiments.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121120050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8557993
Merlin Chai, Naga Brahmendra Yadav Gorla, S. K. Panda
Solid-state transformers (SSTs) have attracted recent interests due to its potential in providing ancillary services in addition to step-up/step-down of voltages. In SSTs, a common topology used in the first AC-DC stage is the cascaded H-bridge (CHB) multilevel active rectifier. This paper proposes a novel dual-model predictive control method for the CHB multilevel active rectifier that achieves sinusoidal source current, maintains DC voltages at set-points, and balances the DC voltages in each of the H-bridge cells. The primary model of the CHB multilevel active rectifier aims to enable control over source current and output voltage. The secondary model uses conservation of energy to calculate the reference source current, which eliminates the need for a PI-control-based outer loop. A Luenberger-based observer is also implemented to estimate the DC load currents. The effectiveness of the proposed method under steady-state and transient conditions is validated through a laboratory prototype of a single-phase 7-level CHB active rectifier.
{"title":"Dual-Model Predictive Control for Cascaded H-Bridge Multilevel Active Rectifier with DC Voltage Balancing in a Solid-State Transformer","authors":"Merlin Chai, Naga Brahmendra Yadav Gorla, S. K. Panda","doi":"10.1109/ECCE.2018.8557993","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8557993","url":null,"abstract":"Solid-state transformers (SSTs) have attracted recent interests due to its potential in providing ancillary services in addition to step-up/step-down of voltages. In SSTs, a common topology used in the first AC-DC stage is the cascaded H-bridge (CHB) multilevel active rectifier. This paper proposes a novel dual-model predictive control method for the CHB multilevel active rectifier that achieves sinusoidal source current, maintains DC voltages at set-points, and balances the DC voltages in each of the H-bridge cells. The primary model of the CHB multilevel active rectifier aims to enable control over source current and output voltage. The secondary model uses conservation of energy to calculate the reference source current, which eliminates the need for a PI-control-based outer loop. A Luenberger-based observer is also implemented to estimate the DC load currents. The effectiveness of the proposed method under steady-state and transient conditions is validated through a laboratory prototype of a single-phase 7-level CHB active rectifier.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127222147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ECCE.2018.8557527
Pengfeng Lin, Chuanlin Zhang, Peng Wang, Jianfang Xiao, Chi Jin
DC microgrids (MGs) have obtained extensive attentions due to their high flexibilities and efficiencies. In DC systems, power electronic loads and motor drives are normally modeled as constant loads (CPLs) which present negative incremental impedances and may cause stability problem. To mitigate the potential instability of CPLs, a novel synthesized control scheme is proposed in this paper. The scheme consists of a generalized proportional-integral observer (GPIO) and a backstepping controller (BC). The GPIO enables to exactly and rapidly estimate the output power of the source converters, and the estimated quantity will be decoupled by the BC in a feedforward way. By using the proposed synthesized method, large signal stabilization of the DC MG can be effectively realized. Destabilizing effects of CPLs could hence be fully compensated, thus safeguarding the stable MG operations. Simulations and experiments consolidate the effectiveness and feasibility of the proposed scheme.
{"title":"A Synthesized Control Scheme for Large Signal Stabilization of DC Microgrids","authors":"Pengfeng Lin, Chuanlin Zhang, Peng Wang, Jianfang Xiao, Chi Jin","doi":"10.1109/ECCE.2018.8557527","DOIUrl":"https://doi.org/10.1109/ECCE.2018.8557527","url":null,"abstract":"DC microgrids (MGs) have obtained extensive attentions due to their high flexibilities and efficiencies. In DC systems, power electronic loads and motor drives are normally modeled as constant loads (CPLs) which present negative incremental impedances and may cause stability problem. To mitigate the potential instability of CPLs, a novel synthesized control scheme is proposed in this paper. The scheme consists of a generalized proportional-integral observer (GPIO) and a backstepping controller (BC). The GPIO enables to exactly and rapidly estimate the output power of the source converters, and the estimated quantity will be decoupled by the BC in a feedforward way. By using the proposed synthesized method, large signal stabilization of the DC MG can be effectively realized. Destabilizing effects of CPLs could hence be fully compensated, thus safeguarding the stable MG operations. Simulations and experiments consolidate the effectiveness and feasibility of the proposed scheme.","PeriodicalId":415217,"journal":{"name":"2018 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124918890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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