Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004006
T. Esteban, Samuel Arturo
A suitable method for transforming OTA-C filter circuits working in voltage-mode to current-mode is presented. First, the ideal behavior of the OTA is modeled using the nullor concept. Second, the transformation process is conducted by applying a set of four basic rules related to the interconnection pattern of the nullors. Third, the nullors of the transformed circuit are synthesized by OTAs. Finally, the computation of the transfer function of the given and the transformed circuit demonstrates the appropriateness of this method to be used as an analytical tool.
{"title":"Transforming OTA-C filters from voltage- to current-mode","authors":"T. Esteban, Samuel Arturo","doi":"10.1109/ICCDCS.2002.1004006","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004006","url":null,"abstract":"A suitable method for transforming OTA-C filter circuits working in voltage-mode to current-mode is presented. First, the ideal behavior of the OTA is modeled using the nullor concept. Second, the transformation process is conducted by applying a set of four basic rules related to the interconnection pattern of the nullors. Third, the nullors of the transformed circuit are synthesized by OTAs. Finally, the computation of the transfer function of the given and the transformed circuit demonstrates the appropriateness of this method to be used as an analytical tool.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117119731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004116
E.E. Zurek, J. Leffew, W. Moreno
This paper contains a review of objective measurements for VoIP compression algorithms. An overview of VoIP networks is presented along with a description of the main characteristics of ITU-T G.729 and G.723.1 standards. PSQM, PAMS, and PESQ measurements for voice clarity are reviewed, and an explanation of the application of perceptual models for the objective measurement of voice clarity is presented. The factors that affect voice quality, delay, echo, and clarity, are discussed briefly.
{"title":"Objective evaluation of voice clarity measurements for VoIP compression algorithms","authors":"E.E. Zurek, J. Leffew, W. Moreno","doi":"10.1109/ICCDCS.2002.1004116","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004116","url":null,"abstract":"This paper contains a review of objective measurements for VoIP compression algorithms. An overview of VoIP networks is presented along with a description of the main characteristics of ITU-T G.729 and G.723.1 standards. PSQM, PAMS, and PESQ measurements for voice clarity are reviewed, and an explanation of the application of perceptual models for the objective measurement of voice clarity is presented. The factors that affect voice quality, delay, echo, and clarity, are discussed briefly.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124717732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004089
V. Grimblatt
A transformation of the semiconductor industry is happening at present. Software is taking a more important role as customers are looking for systems (embedded systems) instead of chips. A few years ago, the semiconductor industry's customers bought chips to design systems using those chips (e.g. TV set, communication equipment). Now, they want systems instead of chips to produce faster, smaller, smarter, and cheaper products. The design of embedded systems and/or products produced by the semiconductor industry must change. It must be adapted to this new market requirement. This paper presents the most common design methodology used at present and the problems associated with this methodology. It also presents a different design methodology taking into account what the market is expecting from the semiconductor industry.
{"title":"Software in the semiconductor industry","authors":"V. Grimblatt","doi":"10.1109/ICCDCS.2002.1004089","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004089","url":null,"abstract":"A transformation of the semiconductor industry is happening at present. Software is taking a more important role as customers are looking for systems (embedded systems) instead of chips. A few years ago, the semiconductor industry's customers bought chips to design systems using those chips (e.g. TV set, communication equipment). Now, they want systems instead of chips to produce faster, smaller, smarter, and cheaper products. The design of embedded systems and/or products produced by the semiconductor industry must change. It must be adapted to this new market requirement. This paper presents the most common design methodology used at present and the problems associated with this methodology. It also presents a different design methodology taking into account what the market is expecting from the semiconductor industry.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116399357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004095
S. Pawel, J. Lehrmann, R. Herzer, M. Netzel
A solution is presented for the monolithic integration of up to four low side drivers inside full bridge power conversion systems. Inexpensive 1 /spl mu/m high voltage CMOS technology was used in order to keep costs down. It was thus necessary to design special level shifter circuits to facilitate the use of negative turn off voltages. Output currents up to 3.5 A per stage, high insensibility to ESD, soft turn off on short-circuiting, and a complex internal fault management are additional key features. The driver transistors, which are optimized for capacitive loads, control IGBTs up to 1200 V and 150 A per stage.
{"title":"High power four channel IGBT driver IC","authors":"S. Pawel, J. Lehrmann, R. Herzer, M. Netzel","doi":"10.1109/ICCDCS.2002.1004095","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004095","url":null,"abstract":"A solution is presented for the monolithic integration of up to four low side drivers inside full bridge power conversion systems. Inexpensive 1 /spl mu/m high voltage CMOS technology was used in order to keep costs down. It was thus necessary to design special level shifter circuits to facilitate the use of negative turn off voltages. Output currents up to 3.5 A per stage, high insensibility to ESD, soft turn off on short-circuiting, and a complex internal fault management are additional key features. The driver transistors, which are optimized for capacitive loads, control IGBTs up to 1200 V and 150 A per stage.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004096
S. Musumeci, R. Pagano, A. Raciti, L. Fragapane, M. Melito
The paper deals with the short circuit behavior of a new family of robust IGBT devices in several laboratory tests conditions. The transient behaviors in hard switching fault (HSF) and fault under load (FUL) have been determined by means of laboratory tests on inductive load. The IGBTs have been tested in several working conditions aiming to account for the different device characteristics, the differences in both the layout parasitic and the gate driving conditions. Also the temperature variation has been considered in the faulted behavior in order to fully evaluate the switching performances as function of the main involved parameters. Finally the characteristics of a smart IGBT device with increased short circuit ruggedness are discussed.
{"title":"Experimental investigation on the short circuit behaviors of robust IGBT devices","authors":"S. Musumeci, R. Pagano, A. Raciti, L. Fragapane, M. Melito","doi":"10.1109/ICCDCS.2002.1004096","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004096","url":null,"abstract":"The paper deals with the short circuit behavior of a new family of robust IGBT devices in several laboratory tests conditions. The transient behaviors in hard switching fault (HSF) and fault under load (FUL) have been determined by means of laboratory tests on inductive load. The IGBTs have been tested in several working conditions aiming to account for the different device characteristics, the differences in both the layout parasitic and the gate driving conditions. Also the temperature variation has been considered in the faulted behavior in order to fully evaluate the switching performances as function of the main involved parameters. Finally the characteristics of a smart IGBT device with increased short circuit ruggedness are discussed.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124962646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004084
S. Contreras
In Latin America, the educational level differences between the high and low social classes are really appreciable, thus hindering social mobility. The need and urgency to reduce this educational gap is clearly recognized by everyone. Many efforts in educational policies (educational reforms, more specialized teachers, etc.) have been made. In addition, several studies show that the introduction of computers to the schools, and more specifically educational games, is a proven way to accelerate childrens' learning. The high cost of computers is, however, a good reason for poor schools to not to purchase them or only to purchase a few. On other hand, some researches using improvised educational handheld devices have shown an amazing improvement in learning when children used them. This paper shows how Motorola designed a new low-cost educational handheld platform and how this design went, in a short time, from a wire-wrap prototype to a complete product ready for production.
{"title":"Designing a low cost educational handheld device for children","authors":"S. Contreras","doi":"10.1109/ICCDCS.2002.1004084","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004084","url":null,"abstract":"In Latin America, the educational level differences between the high and low social classes are really appreciable, thus hindering social mobility. The need and urgency to reduce this educational gap is clearly recognized by everyone. Many efforts in educational policies (educational reforms, more specialized teachers, etc.) have been made. In addition, several studies show that the introduction of computers to the schools, and more specifically educational games, is a proven way to accelerate childrens' learning. The high cost of computers is, however, a good reason for poor schools to not to purchase them or only to purchase a few. On other hand, some researches using improvised educational handheld devices have shown an amazing improvement in learning when children used them. This paper shows how Motorola designed a new low-cost educational handheld platform and how this design went, in a short time, from a wire-wrap prototype to a complete product ready for production.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127001082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004024
I. Lattenberg, K. Vrba, T. Dostál
The internal bipolar structure of the third-generation current conveyor and the multifunctional filter with CCIII in the current mode are presented. Some results of PSpice simulation on the CCIII+ and CCIII- presented and of a simulation on a filter with CCIII are included.
{"title":"Bipolar CCIII+ and CCIII- conveyors and their current mode-filter application","authors":"I. Lattenberg, K. Vrba, T. Dostál","doi":"10.1109/ICCDCS.2002.1004024","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004024","url":null,"abstract":"The internal bipolar structure of the third-generation current conveyor and the multifunctional filter with CCIII in the current mode are presented. Some results of PSpice simulation on the CCIII+ and CCIII- presented and of a simulation on a filter with CCIII are included.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116760617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004030
Q. Ouyang, X.D. Chen, S. Jayanarayanan, F. Prins, S. Banerjee
Graded channel doping in vertical sub-100 nm nMOSFETs was investigated in this study. Conventional single step ion implantation was used to form the asymmetric, graded doping profile in the channel. No large-angle-tilt implant was needed. The device fabrication was compatible with conventional Si CMOS technology. In a graded doped channel, with the higher doping level in the source end of the channel, drain induced barrier lowering and off-state leakage current were reduced significantly. In addition, lower longitudinal electric field in the drain end can be achieved without lightly doped drain (LDD), and hot carrier effects were reduced substantially with this device.
{"title":"Performance enhancement in vertical sub-100 nm nMOSFETs with graded doped channels","authors":"Q. Ouyang, X.D. Chen, S. Jayanarayanan, F. Prins, S. Banerjee","doi":"10.1109/ICCDCS.2002.1004030","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004030","url":null,"abstract":"Graded channel doping in vertical sub-100 nm nMOSFETs was investigated in this study. Conventional single step ion implantation was used to form the asymmetric, graded doping profile in the channel. No large-angle-tilt implant was needed. The device fabrication was compatible with conventional Si CMOS technology. In a graded doped channel, with the higher doping level in the source end of the channel, drain induced barrier lowering and off-state leakage current were reduced significantly. In addition, lower longitudinal electric field in the drain end can be achieved without lightly doped drain (LDD), and hot carrier effects were reduced substantially with this device.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121601519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-19DOI: 10.1109/ICCDCS.2002.1004083
G. Acevedo, J. Ramírez-Angulo
An innovative self-diagnostic method called VDDQ is presented. The proposed method is compliant with the IEEE 1149.4 mixed-signal test bus standard. It performs a pass or fail function of the analog circuit. The VDDQ method sequentially senses the quiescent voltage of several nodes on the circuit under test (CUT) and compares them with their nominal value. The method produces a 10 bit digital vector, with nodal information including a pass or fail flag, plus the analog voltage sensed. Simulation results are provided for the flag and amplifier circuit used for the design of the testing circuit. Through simulations, this testing scheme has performed a test per node every millisecond. This will potentially allow a defect free IC to enter the market in significantly less time than with conventional testing methods.
{"title":"VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard","authors":"G. Acevedo, J. Ramírez-Angulo","doi":"10.1109/ICCDCS.2002.1004083","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004083","url":null,"abstract":"An innovative self-diagnostic method called VDDQ is presented. The proposed method is compliant with the IEEE 1149.4 mixed-signal test bus standard. It performs a pass or fail function of the analog circuit. The VDDQ method sequentially senses the quiescent voltage of several nodes on the circuit under test (CUT) and compares them with their nominal value. The method produces a 10 bit digital vector, with nodal information including a pass or fail flag, plus the analog voltage sensed. Simulation results are provided for the flag and amplifier circuit used for the design of the testing circuit. Through simulations, this testing scheme has performed a test per node every millisecond. This will potentially allow a defect free IC to enter the market in significantly less time than with conventional testing methods.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126460844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCDCS.2002.1004076
N. A. Grant
The Advanced Microwave Sounder (AMSU-B) was originally designed in the late 1970's early 1980's and whilst have proven highly successful, they however do not take advantage of significant advancements that have been made since the original design phase. This paper describes the recent concept investigation into a 21st Century state-of-the-art microwave sounder using the very latest Hybrid Receiver technologies.
{"title":"Next generation mm-wave and submm-wave heterodyne hybrid/MIC receivers for passive radiometer meteorological satellite applications","authors":"N. A. Grant","doi":"10.1109/ICCDCS.2002.1004076","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004076","url":null,"abstract":"The Advanced Microwave Sounder (AMSU-B) was originally designed in the late 1970's early 1980's and whilst have proven highly successful, they however do not take advantage of significant advancements that have been made since the original design phase. This paper describes the recent concept investigation into a 21st Century state-of-the-art microwave sounder using the very latest Hybrid Receiver technologies.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124363751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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