Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004005
F. Lobato-Lopez, S. Solis-Bustos, H. Sucar
This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 /spl mu/m low voltage CMOS (LVCMOS) technology.
{"title":"Design of an LVCMOS high resolution frequency synthesizer","authors":"F. Lobato-Lopez, S. Solis-Bustos, H. Sucar","doi":"10.1109/ICCDCS.2002.1004005","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004005","url":null,"abstract":"This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 /spl mu/m low voltage CMOS (LVCMOS) technology.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128037182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004098
J. Abu-Qahouq, N. Pongratananukul, I. Batarseh, T. Kasparis
Applying the voltage-mode hysteretic control to multiphase Voltage Regulator Modules (VRMs) can satisfy many of the new and future generation of microprocessors and ICs powering requirements. This is because of the numerous advantages that can be obtained when both techniques are used. However, several challenges arise that include current sharing, multiphase control signals distribution, high-speed comparators noise sensitivity, hysteretic band accuracy and stability, VRM operation startup, and the stability of the controller operation at large load transients. Addressing these challenges cannot be easily achieved using analog and discrete components but rather DSP can be used to solve these problems. In this paper, multiphase voltage-mode hysteretic controlled VRM with DSP control and novel current sharing is proposed.
{"title":"Multiphase voltage-mode hysteretic controlled VRM with DSP control and novel current sharing","authors":"J. Abu-Qahouq, N. Pongratananukul, I. Batarseh, T. Kasparis","doi":"10.1109/ICCDCS.2002.1004098","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004098","url":null,"abstract":"Applying the voltage-mode hysteretic control to multiphase Voltage Regulator Modules (VRMs) can satisfy many of the new and future generation of microprocessors and ICs powering requirements. This is because of the numerous advantages that can be obtained when both techniques are used. However, several challenges arise that include current sharing, multiphase control signals distribution, high-speed comparators noise sensitivity, hysteretic band accuracy and stability, VRM operation startup, and the stability of the controller operation at large load transients. Addressing these challenges cannot be easily achieved using analog and discrete components but rather DSP can be used to solve these problems. In this paper, multiphase voltage-mode hysteretic controlled VRM with DSP control and novel current sharing is proposed.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124021736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004093
J. Restrepo, M. Giménez, V. Guzmán, J. Aller, A. Bueno, A. Millan
This work presents the third version of the "Plataforma" integrated test system, a test rig for experiments required to validate dynamically different types of new strategies and control schemes based on vector control theories, parametric estimation, and neural networks applied to AC machine drives; and to analyze the effect of these control strategies over the mains quality. The equipment includes the AC driver power stages, the mechanical load emulation stage, the instrumentation stage and the signal processing and control stage. Two main improvements have been performed: (1) an improved instrumentation stage; (2) a dynamic load system implemented with a torque controlled DC motor. Due to its high versatility, this test system can be used both in research laboratories and postgraduate courses.
{"title":"Platform III: A new version for the integrated test system for AC machine drives performance analysis","authors":"J. Restrepo, M. Giménez, V. Guzmán, J. Aller, A. Bueno, A. Millan","doi":"10.1109/ICCDCS.2002.1004093","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004093","url":null,"abstract":"This work presents the third version of the \"Plataforma\" integrated test system, a test rig for experiments required to validate dynamically different types of new strategies and control schemes based on vector control theories, parametric estimation, and neural networks applied to AC machine drives; and to analyze the effect of these control strategies over the mains quality. The equipment includes the AC driver power stages, the mechanical load emulation stage, the instrumentation stage and the signal processing and control stage. Two main improvements have been performed: (1) an improved instrumentation stage; (2) a dynamic load system implemented with a torque controlled DC motor. Due to its high versatility, this test system can be used both in research laboratories and postgraduate courses.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125234611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004032
V.S. Pitanov, A. Yakimenko
We have investigated I-V characteristics of nearly ideal Schottky contacts Mo/n-Si by power exponent method in order to determine physical phenomena which bear responsibility for reverse current soft behavior. The static and differential resistances as functions of reverse bias were studied. They allowed to obtain power exponent depending on the applied reverse bias. The absolute values of Schottky barrier lowerings were found up to 50 V. Nonlinear regression analysis was used for determining of basic effects, which give rise to barrier lowering in Mo/n-Si contacts. There are interfacial image forces and dipole effect, created by electric field increasing at the metal-semiconductor boundary owing to reverse voltage growth. The largest absolute value of barrier lowering is equal to 4.8 kT (0,12 eV) at 50 V and not exceed by 18% of zero-bias Schottky barrier height. It is established that thermoionic-field emission and barrier height inhomogeneities are not substantial in comparison with both above-mentioned effects.
{"title":"Schottky barrier lowering in Mo/n-Si contacts at the reverse bias","authors":"V.S. Pitanov, A. Yakimenko","doi":"10.1109/ICCDCS.2002.1004032","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004032","url":null,"abstract":"We have investigated I-V characteristics of nearly ideal Schottky contacts Mo/n-Si by power exponent method in order to determine physical phenomena which bear responsibility for reverse current soft behavior. The static and differential resistances as functions of reverse bias were studied. They allowed to obtain power exponent depending on the applied reverse bias. The absolute values of Schottky barrier lowerings were found up to 50 V. Nonlinear regression analysis was used for determining of basic effects, which give rise to barrier lowering in Mo/n-Si contacts. There are interfacial image forces and dipole effect, created by electric field increasing at the metal-semiconductor boundary owing to reverse voltage growth. The largest absolute value of barrier lowering is equal to 4.8 kT (0,12 eV) at 50 V and not exceed by 18% of zero-bias Schottky barrier height. It is established that thermoionic-field emission and barrier height inhomogeneities are not substantial in comparison with both above-mentioned effects.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124270693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004062
R. Quintero, A. Cerdeira
The transient current density distribution in the plane XZ parallel to the electrodes of thyristors and other 4-layer devices is of interest. Since numerical simulations based on the carrier transport equations that include the XZ plane would have to be carried out in 3D, they would become time consuming and expensive. Spice-based XZ simulators as reported in literature are much faster, but the results depend strongly on the necessarily simple equivalent circuits that are used. This paper compares plasma spread simulations in a thyristor, done with an XZ Spice-based simulator previously reported by the authors, with 2D-XY simulations based on the carrier transport equations. It found that for the simulated structure, plasma spread velocity deviates +38% at the beginning of the transient, and -32% near the end of it. On the other hand, for the XZ simulations, it is assumed that the anode current is perpendicular to the XZ plane, and, therefore, the number of discrete elements depend on the extent of validity of that assumption. From the XY simulations it is confirmed that the current flow is almost parallel to the Y direction, making possible high degrees of XZ discretizations.
{"title":"A comparison of Spice-based and carrier transport based simulations of plasma spread in thyristors","authors":"R. Quintero, A. Cerdeira","doi":"10.1109/ICCDCS.2002.1004062","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004062","url":null,"abstract":"The transient current density distribution in the plane XZ parallel to the electrodes of thyristors and other 4-layer devices is of interest. Since numerical simulations based on the carrier transport equations that include the XZ plane would have to be carried out in 3D, they would become time consuming and expensive. Spice-based XZ simulators as reported in literature are much faster, but the results depend strongly on the necessarily simple equivalent circuits that are used. This paper compares plasma spread simulations in a thyristor, done with an XZ Spice-based simulator previously reported by the authors, with 2D-XY simulations based on the carrier transport equations. It found that for the simulated structure, plasma spread velocity deviates +38% at the beginning of the transient, and -32% near the end of it. On the other hand, for the XZ simulations, it is assumed that the anode current is perpendicular to the XZ plane, and, therefore, the number of discrete elements depend on the extent of validity of that assumption. From the XY simulations it is confirmed that the current flow is almost parallel to the Y direction, making possible high degrees of XZ discretizations.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132541415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004036
H. Mnif, T. Zimmer, J. Battaglia, B. Ardouin, D. Berger, D. Céli
A new physical model which describes the self-heating phenomena - the device temperature rise due to its own internal power dissipation - is presented. It permits the accurate temporal response determination of the BJT junction's temperature rise. This model is validated using measurements from an silicon-germanium heterojunction bipolar transistor (Si-Ge HBT).
{"title":"A new approach for modelling the thermal behaviour of bipolar transistors","authors":"H. Mnif, T. Zimmer, J. Battaglia, B. Ardouin, D. Berger, D. Céli","doi":"10.1109/ICCDCS.2002.1004036","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004036","url":null,"abstract":"A new physical model which describes the self-heating phenomena - the device temperature rise due to its own internal power dissipation - is presented. It permits the accurate temporal response determination of the BJT junction's temperature rise. This model is validated using measurements from an silicon-germanium heterojunction bipolar transistor (Si-Ge HBT).","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004001
L. Hernández-Martínez, H. Vázquez-Leal, A. Sarmiento-Reyes
This paper presents a method focused on assessing the uniqueness of the DC solution of transistor networks. It determines the conditions for such a network in order to possess multiple DC operating points. The method is based on identifying positive feedback structures (PFSs) by resorting to the definitions given by Hasler (Fosseprez et al, IEEE Trans. Circuits and Sys. vol. 18, no. 3, pp. 393-402, 1989; Hasler, Int. J. Circuit Theory and Appl., vol. 14, pp. 237-262, 1986; Fosseprez and Hasler, ibid., vol. 18, no. 6, pp. 625-638, 1990). The topological conditions for the existence of PFSs at nullator and norator level are established.
{"title":"Identifying positive feedback structures for assessing the uniqueness of the DC solution by using topological conditions","authors":"L. Hernández-Martínez, H. Vázquez-Leal, A. Sarmiento-Reyes","doi":"10.1109/ICCDCS.2002.1004001","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004001","url":null,"abstract":"This paper presents a method focused on assessing the uniqueness of the DC solution of transistor networks. It determines the conditions for such a network in order to possess multiple DC operating points. The method is based on identifying positive feedback structures (PFSs) by resorting to the definitions given by Hasler (Fosseprez et al, IEEE Trans. Circuits and Sys. vol. 18, no. 3, pp. 393-402, 1989; Hasler, Int. J. Circuit Theory and Appl., vol. 14, pp. 237-262, 1986; Fosseprez and Hasler, ibid., vol. 18, no. 6, pp. 625-638, 1990). The topological conditions for the existence of PFSs at nullator and norator level are established.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132251700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004026
T. Rodrigo-Rodriguez, E. Gutiérrez-D., R. Arturo-Sarmiento, S. Selberherr
By making use of the MOS diode theory, the carrier, and current distribution, as well as the mobility in a MOS device is evaluated. Simple analytical expressions are used for parameters like mobility, carrier concentration, and transversal electric field. Agreement between experimental and simulated results from an LDD MOSFET and an n-well resistance is in agreement, probing this approach is suitable as a plug-in model tester for quick model evaluation.
{"title":"Macro-modeling for MOS device simulation","authors":"T. Rodrigo-Rodriguez, E. Gutiérrez-D., R. Arturo-Sarmiento, S. Selberherr","doi":"10.1109/ICCDCS.2002.1004026","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004026","url":null,"abstract":"By making use of the MOS diode theory, the carrier, and current distribution, as well as the mobility in a MOS device is evaluated. Simple analytical expressions are used for parameters like mobility, carrier concentration, and transversal electric field. Agreement between experimental and simulated results from an LDD MOSFET and an n-well resistance is in agreement, probing this approach is suitable as a plug-in model tester for quick model evaluation.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125374125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004067
V.M. Sanchez-Z, J. Munguía, M. Estrada
Very low deposition rates, below 0.56 nm/min, of SiO/sub 2/ were investigated using photo-induced chemical vapor deposition (photo-CVD). These low deposition rates are adequate to grow very thin and ultra thin layers of SiO/sub 2/. Details on the design of the reaction chamber, reactive gases and process parameters to obtain the desired deposition regime are presented. Dependence of deposition rate on pressure in the chamber is discussed. Deposited layers were characterized using I-V and C-V techniques.
{"title":"Very low photo-CVD deposition rate process for high quality thin SiO/sub 2/ films","authors":"V.M. Sanchez-Z, J. Munguía, M. Estrada","doi":"10.1109/ICCDCS.2002.1004067","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004067","url":null,"abstract":"Very low deposition rates, below 0.56 nm/min, of SiO/sub 2/ were investigated using photo-induced chemical vapor deposition (photo-CVD). These low deposition rates are adequate to grow very thin and ultra thin layers of SiO/sub 2/. Details on the design of the reaction chamber, reactive gases and process parameters to obtain the desired deposition regime are presented. Dependence of deposition rate on pressure in the chamber is discussed. Deposited layers were characterized using I-V and C-V techniques.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115051061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004088
S. Baffreau, S. Bendhia, M. Ramdani, E. Sicard
Work in the field of electromagnetic compatibility (EMC), generally concentrating on noise and interference at electronic systems, has recently focused more attention on integrated circuits (ICs). In this work, we mainly focus on immunity of programmable devices to radio frequency interference (RFI). This paper presents various kinds of RFI and how it can be coupled to a digital signal processor (DSP) or micro-controller. A new approach for immunity measurement is introduced and some ways to improve embedded software are proposed.
{"title":"Characterisation of microcontroller susceptibility to radio frequency interference","authors":"S. Baffreau, S. Bendhia, M. Ramdani, E. Sicard","doi":"10.1109/ICCDCS.2002.1004088","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004088","url":null,"abstract":"Work in the field of electromagnetic compatibility (EMC), generally concentrating on noise and interference at electronic systems, has recently focused more attention on integrated circuits (ICs). In this work, we mainly focus on immunity of programmable devices to radio frequency interference (RFI). This paper presents various kinds of RFI and how it can be coupled to a digital signal processor (DSP) or micro-controller. A new approach for immunity measurement is introduced and some ways to improve embedded software are proposed.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129650523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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