Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004011
F. Lobato-Lopez, J. L. Finol
This paper describe the design of a basic cell for the implementation of a Linear Cellular Neural Network (LCNN). This kind of system could be considered as resistive networks but as its basis are a new way of analog image processing system based on bayesian estimation and regularization theory then a new class of Cellular Neural Networks (CNN), whose activation function is a linear function, emerge in a natural way. This LCNN has characteristic that enable gray-scale image processing. The main focus in this work is the Low Voltage CMOS (LVCMOS) design of the basic building blocks that compose the basic cell of this systems. The design was fabricated on a 0.18 /spl mu/m LVCMOS technology.
{"title":"A low voltage CMOS implementation of a linear cellular neural network for image processing applications","authors":"F. Lobato-Lopez, J. L. Finol","doi":"10.1109/ICCDCS.2002.1004011","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004011","url":null,"abstract":"This paper describe the design of a basic cell for the implementation of a Linear Cellular Neural Network (LCNN). This kind of system could be considered as resistive networks but as its basis are a new way of analog image processing system based on bayesian estimation and regularization theory then a new class of Cellular Neural Networks (CNN), whose activation function is a linear function, emerge in a natural way. This LCNN has characteristic that enable gray-scale image processing. The main focus in this work is the Low Voltage CMOS (LVCMOS) design of the basic building blocks that compose the basic cell of this systems. The design was fabricated on a 0.18 /spl mu/m LVCMOS technology.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"1137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126760085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004115
J. Martins, A. Giulietti, M. Strum
Turbo codes have become an important branch on channel coding research due to their exceptional performance on forward error correcting. They are based on concatenated codes and iterative decoding, where Soft Input/Soft Output (SISO) decoders produce an information refinement in each iteration. In this paper we apply turbo coding for different operating modes, based on the Hiperlan2 and IEEE 802.11a standards (third generation of WALNs). We studied the flexibility of two turbo coding schemes (Block Turbo Codes and Convolutional Turbo Codes) when applied to targeted block sizes and code rates. For BTCs, high rate and small blocks were found when concatenating a BCH code with a single parity check bit. Experimental results showed that each coding scheme outperforms the other depending on the targeted BER.
{"title":"Performance comparison of convolutional and block turbo codes for WLAN applications","authors":"J. Martins, A. Giulietti, M. Strum","doi":"10.1109/ICCDCS.2002.1004115","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004115","url":null,"abstract":"Turbo codes have become an important branch on channel coding research due to their exceptional performance on forward error correcting. They are based on concatenated codes and iterative decoding, where Soft Input/Soft Output (SISO) decoders produce an information refinement in each iteration. In this paper we apply turbo coding for different operating modes, based on the Hiperlan2 and IEEE 802.11a standards (third generation of WALNs). We studied the flexibility of two turbo coding schemes (Block Turbo Codes and Convolutional Turbo Codes) when applied to targeted block sizes and code rates. For BTCs, high rate and small blocks were found when concatenating a BCH code with a single parity check bit. Experimental results showed that each coding scheme outperforms the other depending on the targeted BER.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126300323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004040
R. Paszkiewicz, A. Tyszka-Zawadzka, P. Szczepański
We analyze the influence of integrated outcoupler, characterized by effective end-reflectivity, on the statistical properties of light generated by circular-grating distributed Bragg reflector laser. In our paper we concentrate on the effects resulting from the nonorthogonality properties of laser modes. The semi classical approach based on stationary and time-dependent solution of the Fokker-Planck equation is used. Numerical results obtained for CG-DBR structure reveal the behavior of statistical parameters of light such as the mean laser intensity, intensity fluctuations and the laser linewidth as a functions of the effective complex reflection of the integrated outcoupler.
{"title":"The statistical properties of light generated by circular-grating distributed Bragg reflector laser with integrated outcoupler","authors":"R. Paszkiewicz, A. Tyszka-Zawadzka, P. Szczepański","doi":"10.1109/ICCDCS.2002.1004040","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004040","url":null,"abstract":"We analyze the influence of integrated outcoupler, characterized by effective end-reflectivity, on the statistical properties of light generated by circular-grating distributed Bragg reflector laser. In our paper we concentrate on the effects resulting from the nonorthogonality properties of laser modes. The semi classical approach based on stationary and time-dependent solution of the Fokker-Planck equation is used. Numerical results obtained for CG-DBR structure reveal the behavior of statistical parameters of light such as the mean laser intensity, intensity fluctuations and the laser linewidth as a functions of the effective complex reflection of the integrated outcoupler.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125894768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004046
T. Ytterdal, T. Fjeldly, S. Baier, J. Deng, M. Shur
In this paper, we present an efficient approach to the modeling and simulation of mixed-domain electrical/optical systems utilizing a single kernel simulator. The approach is illustrated by a case study of an optoelectronic interconnect system.
{"title":"Modeling and simulation of optoelectronic interconnect systems using a single kernel simulator","authors":"T. Ytterdal, T. Fjeldly, S. Baier, J. Deng, M. Shur","doi":"10.1109/ICCDCS.2002.1004046","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004046","url":null,"abstract":"In this paper, we present an efficient approach to the modeling and simulation of mixed-domain electrical/optical systems utilizing a single kernel simulator. The approach is illustrated by a case study of an optoelectronic interconnect system.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126834212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004108
D. Biolek, J. Cajka, K. Vrba
A procedure for universal filter design using generalized current conveyors is described. The proposed network can be realized with the aid of so-called universal current conveyors. It can therefore be easily transformed from the current mode into the voltage mode and vice versa.
{"title":"Current-mode universal biquad","authors":"D. Biolek, J. Cajka, K. Vrba","doi":"10.1109/ICCDCS.2002.1004108","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004108","url":null,"abstract":"A procedure for universal filter design using generalized current conveyors is described. The proposed network can be realized with the aid of so-called universal current conveyors. It can therefore be easily transformed from the current mode into the voltage mode and vice versa.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132211540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004090
S. Szostak, L. Lukasiak, A. Jakubowski
The performance of MOS devices is to a large extent determined by the quality of the Si-SiO/sub 2/ interface. This paper presents a new system for characterization of MOS and MOS SOI structures by means of charge pumping. MOSFETs and SOI MOSFETs are used as test structures.
{"title":"System for extensive characterization of MOS and SOI MOS structures by means of charge pumping","authors":"S. Szostak, L. Lukasiak, A. Jakubowski","doi":"10.1109/ICCDCS.2002.1004090","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004090","url":null,"abstract":"The performance of MOS devices is to a large extent determined by the quality of the Si-SiO/sub 2/ interface. This paper presents a new system for characterization of MOS and MOS SOI structures by means of charge pumping. MOSFETs and SOI MOSFETs are used as test structures.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134398993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004000
Narcizo Sabbatini, Antonio Mauricio Brochi, Tulio Ibanez Nunes
The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included.
{"title":"Reuse issues on the verification of embedded MCU cores","authors":"Narcizo Sabbatini, Antonio Mauricio Brochi, Tulio Ibanez Nunes","doi":"10.1109/ICCDCS.2002.1004000","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004000","url":null,"abstract":"The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"414 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130906297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004028
G. Gautier, C. E. Viana, S. Crand, R. Rogel, N. Morimoto, O. Bonnaud
After several experimental studies on improvement of the electrical performances of N-type polysilicon thin-film transistors (NMOS-TFT) fabricated by LPCVD (Low Pressure Chemical Vapor Deposition) and SPC (Solid Phase Crystallization) techniques at low temperature, it was necessary to implement a process to design a complementary TFT cell technology (CMOS-like TFT). This elementary cell is useful indeed essential to design efficient digital circuits. This paper describes the process developed and presents a comparison between two inverters: NMOS-inverter based on the use of two NMOS-TFTs and a CMOS-like TFT inverter. This work has allowed to validate the process and to quantify the improvement of the electrical characteristics such as noise margins, gain and output voltage amplitude.
{"title":"Comparison of NMOS and CMOS TFT inverters fabricated by LPCVD and SPC techniques at low temperature (<600/spl deg/C)","authors":"G. Gautier, C. E. Viana, S. Crand, R. Rogel, N. Morimoto, O. Bonnaud","doi":"10.1109/ICCDCS.2002.1004028","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004028","url":null,"abstract":"After several experimental studies on improvement of the electrical performances of N-type polysilicon thin-film transistors (NMOS-TFT) fabricated by LPCVD (Low Pressure Chemical Vapor Deposition) and SPC (Solid Phase Crystallization) techniques at low temperature, it was necessary to implement a process to design a complementary TFT cell technology (CMOS-like TFT). This elementary cell is useful indeed essential to design efficient digital circuits. This paper describes the process developed and presents a comparison between two inverters: NMOS-inverter based on the use of two NMOS-TFTs and a CMOS-like TFT inverter. This work has allowed to validate the process and to quantify the improvement of the electrical characteristics such as noise margins, gain and output voltage amplitude.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115272901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004063
F. Guarín, G. La Rosa, Z.J. Yang, S. Rauch
Practical studies of the influence of various reliability mechanisms on the lifetime estimation and the impact of widely accepted assumptions to the accuracy of the reliability degradation predictions are discussed in detail. The inaccuracies of the "industry standard" approach to reliability stressing as well as the methodology utilized for the prediction of lifetimes in advanced CMOS technologies are addressed. A review of measurement practices and stress conditions is also given. Methodologies for improving the accuracy of reliability predictions have been developed and validated with experimental results for devices with an L/sub EFF/ range spanning well into the deep sub-micron regime, and with stress conditions covering a wide V/sub GS/ and V/sub DS/ range. The impact of NFET and PFET reliability degradation on circuit performance has been characterized using ring oscillator stressing. The traditional view that only NFET hot carrier degradation contributes to circuit performance degradation has been shown not to be applicable for advanced sub-micron CMOS technologies. The need of a more comprehensive reliability evaluation for realistic lifetime projections is described.
{"title":"A practical approach for the accurate lifetime estimation of device degradation in deep sub-micron CMOS technologies","authors":"F. Guarín, G. La Rosa, Z.J. Yang, S. Rauch","doi":"10.1109/ICCDCS.2002.1004063","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004063","url":null,"abstract":"Practical studies of the influence of various reliability mechanisms on the lifetime estimation and the impact of widely accepted assumptions to the accuracy of the reliability degradation predictions are discussed in detail. The inaccuracies of the \"industry standard\" approach to reliability stressing as well as the methodology utilized for the prediction of lifetimes in advanced CMOS technologies are addressed. A review of measurement practices and stress conditions is also given. Methodologies for improving the accuracy of reliability predictions have been developed and validated with experimental results for devices with an L/sub EFF/ range spanning well into the deep sub-micron regime, and with stress conditions covering a wide V/sub GS/ and V/sub DS/ range. The impact of NFET and PFET reliability degradation on circuit performance has been characterized using ring oscillator stressing. The traditional view that only NFET hot carrier degradation contributes to circuit performance degradation has been shown not to be applicable for advanced sub-micron CMOS technologies. The need of a more comprehensive reliability evaluation for realistic lifetime projections is described.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115557435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ICCDCS.2002.1004017
M. Pessatti, C. dos Reis Filho
An implementation in CMOS technology of the ingenious analog sine function generator invented by Barrie Gilbert over two decades ago (Electron. Lett., vol. 13, pp. 506-508, 1977) is described in this paper. New in this circuit is the use of lateral-PNP bipolar transistors to build the core of the sine generator together with MOS transistors in the saturation region making up the rest of the circuit. Experimental results from prototypes of the circuit fabricated in 0.8 /spl mu/m CMOS technology showed that the accuracy of the produced sine is lower than that reported from implementations in bipolar and BiCMOS technologies (dos Reis Filho and Fruett, Proc. ICECS'97, 1997). The measured deviation from ideal sine over the (-/spl pi//2 to +/spl pi//2) range is less than 0.5%. Total harmonic distortion measured for a fundamental frequency at 20 kHz and the next four harmonics is approximately 1%. This circuit could be used in several applications, including the AC excitation of bridge-type sensors as a replacement for sinusoidal oscillators.
在CMOS技术的实现巧妙的模拟正弦函数发生器由巴里·吉尔伯特发明了二十多年前(电子。列托人。(第13卷，第506-508页，1977年)。该电路的新特点是使用横向pnp双极晶体管来构建正弦发生器的核心，并在饱和区域使用MOS晶体管构成电路的其余部分。以0.8 /spl mu/m CMOS技术制造的电路原型的实验结果表明，所产生的正弦精度低于双极和BiCMOS技术实现的精度(dos Reis Filho和Fruett, Proc. ICECS'97, 1997)。在(-/spl pi//2至+/spl pi//2)范围内，与理想正弦值的测量偏差小于0.5%。在20千赫的基频和接下来的四个谐波测量的总谐波失真约为1%。该电路可用于多种应用，包括桥式传感器的交流励磁作为正弦振荡器的替代品。
{"title":"CMOS analog sine function generator using lateral-PNP bipolar transistors","authors":"M. Pessatti, C. dos Reis Filho","doi":"10.1109/ICCDCS.2002.1004017","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004017","url":null,"abstract":"An implementation in CMOS technology of the ingenious analog sine function generator invented by Barrie Gilbert over two decades ago (Electron. Lett., vol. 13, pp. 506-508, 1977) is described in this paper. New in this circuit is the use of lateral-PNP bipolar transistors to build the core of the sine generator together with MOS transistors in the saturation region making up the rest of the circuit. Experimental results from prototypes of the circuit fabricated in 0.8 /spl mu/m CMOS technology showed that the accuracy of the produced sine is lower than that reported from implementations in bipolar and BiCMOS technologies (dos Reis Filho and Fruett, Proc. ICECS'97, 1997). The measured deviation from ideal sine over the (-/spl pi//2 to +/spl pi//2) range is less than 0.5%. Total harmonic distortion measured for a fundamental frequency at 20 kHz and the next four harmonics is approximately 1%. This circuit could be used in several applications, including the AC excitation of bridge-type sensors as a replacement for sinusoidal oscillators.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"24 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116589402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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